From f076c6e7e12f7fd3ec2c6b171c4f154b28e2560b Mon Sep 17 00:00:00 2001 Message-Id: From: Eduardo Habkost Date: Fri, 28 Sep 2012 16:50:19 +0200 Subject: [PATCH 01/21] support TSC deadline MSR with subsection RH-Author: Eduardo Habkost Message-id: <1348851023-31907-15-git-send-email-ehabkost@redhat.com> Patchwork-id: 42521 O-Subject: [RHEL6 qemu-kvm PATCH 14/18] support TSC deadline MSR with subsection Bugzilla: 767944 RH-Acked-by: Alex Williamson RH-Acked-by: Paolo Bonzini RH-Acked-by: Igor Mammedov RH-Acked-by: Orit Wasserman From: "ddugger@redhat.com" Bugzilla: 767944 Upstream status: commit bfc2455ddbb41148494a084d15777e6bed7533c3 Upstream commit: commit bfc2455ddbb41148494a084d15777e6bed7533c3 Author: Liu, Jinsong Date: Sun Sep 25 16:10:48 2011 +0800 kvm: support TSC deadline MSR KVM add emulation of lapic tsc deadline timer for guest. This patch is co-operation work at qemu side. Signed-off-by: Liu, Jinsong Signed-off-by: Marcelo Tosatti [ehabkost: edited patch subject and description to include more clear Bugzilla and upstream status information] [ehabkost: moved the MSR handling code to qemu-kvm-x86.c] Signed-off-by: Don Dugger Signed-off-by: Eduardo Habkost --- qemu-kvm-x86.c | 10 ++++++++++ target-i386/cpu.h | 2 ++ target-i386/machine.c | 21 +++++++++++++++++++++ 3 files changed, 33 insertions(+) Signed-off-by: Michal Novotny --- qemu-kvm-x86.c | 10 ++++++++++ target-i386/cpu.h | 2 ++ target-i386/machine.c | 21 +++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/qemu-kvm-x86.c b/qemu-kvm-x86.c index 8fd82b7..c720124 100644 --- a/qemu-kvm-x86.c +++ b/qemu-kvm-x86.c @@ -30,6 +30,7 @@ static struct kvm_msr_list *kvm_msr_list; extern unsigned int kvm_shadow_memory; static int kvm_has_msr_star; static int kvm_has_vm_hsave_pa; +static int has_msr_tsc_deadline; static int lm_capable_kernel; @@ -800,6 +801,8 @@ int kvm_arch_qemu_create_context(void) kvm_has_msr_star = 1; if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) kvm_has_vm_hsave_pa = 1; + if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) + has_msr_tsc_deadline = 1; } return 0; @@ -848,6 +851,9 @@ static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env) case MSR_VM_HSAVE_PA: env->vm_hsave = entry->data; break; + case MSR_IA32_TSCDEADLINE: + env->tsc_deadline = entry->data; + break; case MSR_KVM_SYSTEM_TIME: env->system_time_msr = entry->data; break; @@ -1070,6 +1076,8 @@ void kvm_arch_load_regs(CPUState *env) set_msr_entry(&msrs[n++], MSR_STAR, env->star); if (kvm_has_vm_hsave_pa) set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); + if (has_msr_tsc_deadline) + set_msr_entry(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); #ifdef TARGET_X86_64 if (lm_capable_kernel) { set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar); @@ -1308,6 +1316,8 @@ void kvm_arch_save_regs(CPUState *env) if (kvm_has_vm_hsave_pa) msrs[n++].index = MSR_VM_HSAVE_PA; + if (has_msr_tsc_deadline) + msrs[n++].index = MSR_IA32_TSCDEADLINE; #ifdef TARGET_X86_64 if (lm_capable_kernel) { msrs[n++].index = MSR_CSTAR; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index ff2afe9..114afda 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -283,6 +283,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe #define MSR_MTRRcap_VCNT 8 @@ -696,6 +697,7 @@ typedef struct CPUX86State { uint64_t pv_eoi_en_msr; uint64_t tsc; + uint64_t tsc_deadline; uint64_t pat; diff --git a/target-i386/machine.c b/target-i386/machine.c index 2e1eeb5..eb4576e 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -437,6 +437,24 @@ static const VMStateDescription vmstate_pv_eoi_msr = { } }; +static bool tscdeadline_needed(void *opaque) +{ + CPUState *env = opaque; + + return env->tsc_deadline != 0; +} + +static const VMStateDescription vmstate_msr_tscdeadline = { + .name = "cpu/msr_tscdeadline", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64(tsc_deadline, CPUState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_cpu = { .name = "cpu", .version_id = CPU_SAVE_VERSION, @@ -549,6 +567,9 @@ static const VMStateDescription vmstate_cpu = { .vmsd = &vmstate_pv_eoi_msr, .needed = pv_eoi_msr_needed, }, { + .vmsd = &vmstate_msr_tscdeadline, + .needed = tscdeadline_needed, + }, { /* empty */ } } -- 1.7.11.4