Index: sys/arch/mips/mips/spl.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/spl.S,v
retrieving revision 1.10
diff -u -p -r1.10 spl.S
--- sys/arch/mips/mips/spl.S	27 Jun 2015 03:29:09 -0000	1.10
+++ sys/arch/mips/mips/spl.S	24 Jul 2016 14:46:28 -0000
@@ -140,8 +140,8 @@ STATIC_XLEAF(_splsw_splx_noprof)		# does
 1:
 	mfc0	v1, MIPS_COP_0_STATUS		# fetch status register
 	NOP_L					# load delay
-	or	v1, MIPS_INT_MASK		# set all INT bits
-	xor	v1, a1				# clear any bits for this IPL
+	xor	a1, MIPS_INT_MASK		# invert SR bits
+	or	v1, a1				# set any bits for this IPL
 	DYNAMIC_STATUS_MASK(v1,t0)		# machine dependent masking
 	mtc0	zero, MIPS_COP_0_STATUS		## disable interrupts
 	COP0_SYNC
@@ -173,8 +173,6 @@ STATIC_LEAF(_splsw_spl0)
 	PTR_L	a3, L_CPU(MIPS_CURLWP)
 	or	v1, MIPS_SR_INT_IE		# mask sure interrupts are on
 	xor	v1, MIPS_INT_MASK		# invert
-	mtc0	zero, MIPS_COP_0_CAUSE		# clear SOFT_INT bits
-	COP0_SYNC
 	mfc0	a0, MIPS_COP_0_STATUS
 	NOP_L					# load delay
 	or	v0, a0, v1