Reading design: ../synth/example_top.prj
WARNING:Xst:29 - Optimization Effort not specified

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_tg.v" into library work
Parsing module <mig_7series_v1_8_axi4_tg>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v" into library work
Parsing module <mig_7series_v1_8_axi4_wrapper>.
INFO:HDLCompiler:693 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v" Line 193. parameter declaration becomes local in mig_7series_v1_8_axi4_wrapper with formal parameter declaration list
INFO:HDLCompiler:693 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v" Line 203. parameter declaration becomes local in mig_7series_v1_8_axi4_wrapper with formal parameter declaration list
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v" into library work
Parsing module <mig_7series_v1_8_cmd_prbs_gen_axi>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_data_gen_chk.v" into library work
Parsing module <mig_7series_v1_8_data_gen_chk>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_tg.v" into library work
Parsing module <mig_7series_v1_8_tg>.
INFO:HDLCompiler:693 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_tg.v" Line 157. parameter declaration becomes local in mig_7series_v1_8_tg with formal parameter declaration list
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/ddr2_ddr3_chipscope.v" into library work
Parsing module <ddr_icon>.
Parsing module <ddr_ila_basic>.
Parsing module <ddr_ila_wrpath>.
Parsing module <ddr_ila_rdpath>.
Parsing module <ddr_vio_sync_async_out72>.
Parsing module <ddr_vio_async_in_sync_out>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" into library work
Parsing module <mig_7series_v1_8_chk_win>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" into library work
Parsing module <example_top>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_addr_decode.v" into library work
Parsing module <mig_7series_v1_8_axi_ctrl_addr_decode>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_read.v" into library work
Parsing module <mig_7series_v1_8_axi_ctrl_read>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg.v" into library work
Parsing module <mig_7series_v1_8_axi_ctrl_reg>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_reg_bank.v" into library work
Parsing module <mig_7series_v1_8_axi_ctrl_reg_bank>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_top.v" into library work
Parsing module <mig_7series_v1_8_axi_ctrl_top>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_ctrl_write.v" into library work
Parsing module <mig_7series_v1_8_axi_ctrl_write>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" into library work
Parsing module <mig_7series_v1_8_axi_mc>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_ar_channel>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_aw_channel>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_b_channel>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_cmd_arbiter>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_cmd_fsm>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_cmd_translator>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_incr_cmd>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_r_channel>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_simple_fifo>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_w_channel>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_wr_cmd_fsm>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v" into library work
Parsing module <mig_7series_v1_8_axi_mc_wrap_cmd>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v" into library work
Parsing module <mig_7series_v1_8_ddr_a_upsizer>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v" into library work
Parsing module <mig_7series_v1_8_ddr_axi_register_slice>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" into library work
Parsing module <mig_7series_v1_8_ddr_axi_upsizer>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v" into library work
Parsing module <mig_7series_v1_8_ddr_axic_register_slice>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v" into library work
Parsing module <mig_7series_v1_8_ddr_carry_and>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v" into library work
Parsing module <mig_7series_v1_8_ddr_carry_latch_and>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v" into library work
Parsing module <mig_7series_v1_8_ddr_carry_latch_or>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v" into library work
Parsing module <mig_7series_v1_8_ddr_carry_or>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v" into library work
Parsing module <mig_7series_v1_8_ddr_command_fifo>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator.v" into library work
Parsing module <mig_7series_v1_8_ddr_comparator>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v" into library work
Parsing module <mig_7series_v1_8_ddr_comparator_sel>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v" into library work
Parsing module <mig_7series_v1_8_ddr_comparator_sel_static>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v" into library work
Parsing module <mig_7series_v1_8_ddr_r_upsizer>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v" into library work
Parsing module <mig_7series_v1_8_ddr_w_upsizer>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v" into library work
Parsing module <mig_7series_v1_8_clk_ibuf>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v" into library work
Parsing module <mig_7series_v1_8_infrastructure>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v" into library work
Parsing module <mig_7series_v1_8_iodelay_ctrl>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v" into library work
Parsing module <mig_7series_v1_8_tempmon>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_mux.v" into library work
Parsing module <mig_7series_v1_8_arb_mux>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v" into library work
Parsing module <mig_7series_v1_8_arb_row_col>.
WARNING:HDLCompiler:248 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v" Line 252: Block identifier is required on this block
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" into library work
Parsing module <mig_7series_v1_8_arb_select>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v" into library work
Parsing module <mig_7series_v1_8_bank_cntrl>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_common.v" into library work
Parsing module <mig_7series_v1_8_bank_common>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v" into library work
Parsing module <mig_7series_v1_8_bank_compare>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_mach.v" into library work
Parsing module <mig_7series_v1_8_bank_mach>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v" into library work
Parsing module <mig_7series_v1_8_bank_queue>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" into library work
Parsing module <mig_7series_v1_8_bank_state>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_col_mach.v" into library work
Parsing module <mig_7series_v1_8_col_mach>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v" into library work
Parsing module <mig_7series_v1_8_mc>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v" into library work
Parsing module <mig_7series_v1_8_rank_cntrl>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_common.v" into library work
Parsing module <mig_7series_v1_8_rank_common>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_mach.v" into library work
Parsing module <mig_7series_v1_8_rank_mach>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v" into library work
Parsing module <mig_7series_v1_8_round_robin_arb>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v" into library work
Parsing module <mig_7series_v1_8_ecc_buf>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_dec_fix.v" into library work
Parsing module <mig_7series_v1_8_ecc_dec_fix>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_gen.v" into library work
Parsing module <mig_7series_v1_8_ecc_gen>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ecc/mig_7series_v1_8_ecc_merge_enc.v" into library work
Parsing module <mig_7series_v1_8_ecc_merge_enc>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v" into library work
Parsing module <mig_7series_v1_8_mem_intfc>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" into library work
Parsing module <mig_7series_v1_8_memc_ui_top_axi>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" into library work
Parsing module <mig_7series_v1_8_ddr_byte_group_io>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" into library work
Parsing module <mig_7series_v1_8_ddr_byte_lane>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" into library work
Parsing module <mig_7series_v1_8_ddr_calib_top>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v" into library work
Parsing module <mig_7series_v1_8_ddr_if_post_fifo>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" into library work
Parsing module <mig_7series_v1_8_ddr_mc_phy>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" into library work
Parsing module <mig_7series_v1_8_ddr_mc_phy_wrapper>.
WARNING:HDLCompiler:248 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 874: Block identifier is required on this block
WARNING:HDLCompiler:248 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 878: Block identifier is required on this block
WARNING:HDLCompiler:248 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 911: Block identifier is required on this block
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v" into library work
Parsing module <mig_7series_v1_8_ddr_of_pre_fifo>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_4lanes>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_dqs_found_cal>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal_hr.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_dqs_found_cal_hr>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_init>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_oclkdelay_cal>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_prbs_rdlvl>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_rdlvl>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_tempmon>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_top>.
WARNING:HDLCompiler:248 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" Line 717: Block identifier is required on this block
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_wrcal>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" into library work
Parsing module <mig_7series_v1_8_ddr_phy_wrlvl>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v" into library work
Parsing module <mig_7series_v1_8_ddr_prbs_gen>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v" into library work
Parsing module <mig_7series_v1_8_ui_cmd>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v" into library work
Parsing module <mig_7series_v1_8_ui_rd_data>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_top.v" into library work
Parsing module <mig_7series_v1_8_ui_top>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v" into library work
Parsing module <mig_7series_v1_8_ui_wr_data>.
Analyzing Verilog file "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" into library work
Parsing module <ddr3_interface_fast>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1312: Port win_bit_select is not connected to this instance

Elaborating module <example_top>.

Elaborating module
<ddr3_interface_fast(TCQ=100,ADDR_CMD_MODE="1T",AL="0",PAYLOAD_WIDTH=32,BANK_WIDTH=3,BURST_MODE="8",BURST_TYPE="SEQ",CA_MIRROR="OFF",CK_WIDTH=1,COL_WIDTH=10,CMD_PIPE_PLUS1="ON",CS_WIDTH=1,nCS_PER_RANK=1,CKE_WIDTH=1,DATA_WIDTH=32,DATA_BUF_ADDR_WIDTH=5,DQ_CNT_WIDTH=5,DQ_PER_DM=8,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_WIDTH=8,ECC="OFF",ECC_WIDTH=0,ECC_TEST="OFF",MC_ERR_ADDR_WIDTH=29,nAL=0,nBANK_MACHS=4,CKE_ODT_AUX="FALSE",ORDERING="NORM",OUTPUT_DRV="HIGH",IBUF_LPWR_MODE="OFF",IODELAY_HP_MODE="ON",DATA_IO_IDLE_PWRDWN="ON",BANK_TYPE="HP_IO",DATA_IO_PRIM_TYPE="HP_LP",REG_CTRL="OFF",RTT_NOM="60",RTT_WR="OFF",CL=9,CWL=7,tCKE=5000,tFAW=30000,tPRDI=1000000,tRAS=35000,tRCD=13750,tREFI=7800000,tRFC=300000,tRP=13750,tRRD=6000,tRTP=7500,tWTR=7500,tZQI=128000000,tZQCS=64,USER_REFRESH="OFF",WRLVL="ON",DEBUG_PORT="ON",RANKS=1,ODT_WIDTH=1,ROW_WIDTH=15,ADDR_WIDTH=29,SIM_BYPASS_INIT_CAL="OFF",SIMULATION="FALSE",BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,DATA_CTL_B0=
4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0,PHY_0_BITLANES=48'b01111111110001111111110001111111110001011111111,PHY_1_BITLANES=48'b01111111111111111111111110000000000000000000000,PHY_2_BITLANES=48'b0,CK_BYTE_MAP=144'b010011,ADDR_MAP=192'b0100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011,BANK_MAP=36'b0100101010000100100101000100100100,CAS_MAP=12'b0100100010,CKE_ODT_BYTE_MAP=8'b0,CKE_MAP=96'b0100011011,ODT_MAP=96'b0100011010,CS_MAP=120'b0100100000,PARITY_MAP=12'b0,RAS_MAP=12'b0100100011,WE_MAP=12'b0100100001,DQS_BYTE_MAP=144'b010000001000000011,DATA0_MAP=96'b0110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000,DATA1_MAP=96'b0100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000,DATA2_MAP=96'b01000100000001001000000001001100000001010000000001010100000001011000000001011100000001100
0,DATA3_MAP=96'b01000000000010000000000011000000000100000000000101000000000110000000000111,DATA4_MAP=96'b0,DATA5_MAP=96'b0,DATA6_MAP=96'b0,DATA7_MAP=96'b0,DATA8_MAP=96'b0,DATA9_MAP=96'b0,DATA10_MAP=96'b0,DATA11_MAP=96'b0,DATA12_MAP=96'b0,DATA13_MAP=96'b0,DATA14_MAP=96'b0,DATA15_MAP=96'b0,DATA16_MAP=96'b0,DATA17_MAP=96'b0,MASK0_MAP=108'b01001000000011001000000101001000000111001,MASK1_MAP=108'b0,CALIB_ROW_ADD=16'b0,CALIB_COL_ADD=12'b0,CALIB_BA_ADD=3'b0,SLOT_0_CONFIG=8'b01,SLOT_1_CONFIG=8'b0,MEM_ADDR_ORDER="BANK_ROW_COLUMN",USE_CS_PORT=1,USE_DM_PORT=1,USE_ODT_PORT=1,PHY_CONTROL_MASTER_BANK=1,TEMP_MON_CONTROL="INTERNAL",DM_WIDTH=4,nCK_PER_CLK=4,tCK=1666,DIFF_TERM_SYSCLK="TRUE",CLKIN_PERIOD=9996,CLKFBOUT_MULT=12,DIVCLK_DIVIDE=1,CLKOUT0_PHASE=337.5,CLKOUT0_DIVIDE=2,CLKOUT1_DIVIDE=2,CLKOUT2_DIVIDE=32,CLKOUT3_DIVIDE=8,C_S_AXI_ID_WIDTH=4,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_MC_nCK_PER_CLK=4,C_S_AXI_SUPPORTS_NARROW_BURST=1,C_RD_WR_ARB_ALGORITHM="ROUND_ROBIN",C_S_AXI_REG_EN0=20'b0,C_S_AXI_REG_EN1=20'b0,C_S_AXI
_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_S_AXI_BASEADDR=32'b0,C_ECC_ONOFF_RESET_VALUE=1,C_ECC_CE_COUNTER_WIDTH=8,SYSCLK_TYPE="SINGLE_ENDED",REFCLK_TYPE="NO_BUFFER",REFCLK_FREQ=200.0,DIFF_TERM_REFCLK="TRUE",IODELAY_GRP="IODELAY_MIG",CAL_WIDTH="HALF",STARVE_LIMIT=2,DRAM_TYPE="DDR3",RST_ACT_LOW=1)>.

Elaborating module <mig_7series_v1_8_iodelay_ctrl(TCQ=100,IODELAY_GRP="IODELAY_MIG",REFCLK_TYPE="NO_BUFFER",SYSCLK_TYPE="SINGLE_ENDED",RST_ACT_LOW=1,DIFF_TERM_REFCLK="TRUE")>.

Elaborating module <BUFG>.

Elaborating module <IDELAYCTRL>.

Elaborating module <mig_7series_v1_8_clk_ibuf(SYSCLK_TYPE="SINGLE_ENDED",DIFF_TERM_SYSCLK="TRUE")>.

Elaborating module <IBUFG(IBUF_LOW_PWR="FALSE")>.

Elaborating module <mig_7series_v1_8_tempmon(TCQ=100,TEMP_MON_CONTROL="INTERNAL",XADC_CLK_PERIOD=5000,tTEMPSAMPLE=10000000)>.

Elaborating module <XADC(INIT_40=16'b1000000000000000,INIT_41=16'b011111100001111,INIT_42=16'b010000000000,INIT_48=16'b0100000000,INIT_49=16'b0,INIT_4A=16'b0,INIT_4B=16'b0,INIT_4C=16'b0,INIT_4D=16'b0,INIT_4E=16'b0,INIT_4F=16'b0,INIT_50=16'b1011010111101101,INIT_51=16'b0101011111100100,INIT_52=16'b1010000101000111,INIT_53=16'b1100101000110011,INIT_54=16'b1010100100111010,INIT_55=16'b0101001011000110,INIT_56=16'b1001010101010101,INIT_57=16'b1010111001001110,INIT_58=16'b0101100110011001,INIT_5C=16'b0101000100010001,SIM_DEVICE="7SERIES")>.

Elaborating module <mig_7series_v1_8_infrastructure(TCQ=100,nCK_PER_CLK=4,CLKIN_PERIOD=9996,SYSCLK_TYPE="SINGLE_ENDED",CLKFBOUT_MULT=12,DIVCLK_DIVIDE=1,CLKOUT0_PHASE=337.5,CLKOUT0_DIVIDE=2,CLKOUT1_DIVIDE=2,CLKOUT2_DIVIDE=32,CLKOUT3_DIVIDE=8,CLKOUT5_DIVIDE=5,RST_ACT_LOW=1)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v" Line 145: Result of 64-bit expression is truncated to fit in 32-bit target.

Elaborating module <PLLE2_ADV(BANDWIDTH="OPTIMIZED",COMPENSATION="INTERNAL",STARTUP_WAIT="FALSE",CLKOUT0_DIVIDE=2,CLKOUT1_DIVIDE=2,CLKOUT2_DIVIDE=32,CLKOUT3_DIVIDE=8,CLKOUT4_DIVIDE=4,CLKOUT5_DIVIDE=5,DIVCLK_DIVIDE=1,CLKFBOUT_MULT=12,CLKFBOUT_PHASE=0.0,CLKIN1_PERIOD=9.996,CLKOUT0_DUTY_CYCLE=0.5,CLKOUT0_PHASE=337.5,CLKOUT1_DUTY_CYCLE=0.5,CLKOUT1_PHASE=0.0,CLKOUT2_DUTY_CYCLE=0.0625,CLKOUT2_PHASE=9.84375,CLKOUT3_DUTY_CYCLE=0.5,CLKOUT3_PHASE=0.0,CLKOUT4_DUTY_CYCLE=0.5,CLKOUT4_PHASE=168.75,CLKOUT5_DUTY_CYCLE=0.5,CLKOUT5_PHASE=0.0,REF_JITTER1=0.01,REF_JITTER2=0.01)>.

Elaborating module <BUFH>.

Elaborating module <MMCME2_ADV(BANDWIDTH="HIGH",CLKOUT4_CASCADE="FALSE",COMPENSATION="BUF_IN",STARTUP_WAIT="FALSE",DIVCLK_DIVIDE=1,CLKFBOUT_MULT_F=5.3312,CLKFBOUT_PHASE=0.0,CLKFBOUT_USE_FINE_PS="FALSE",CLKOUT0_DIVIDE_F=5.3312,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKOUT0_USE_FINE_PS="FALSE",CLKOUT1_PHASE=0.0,CLKOUT1_DUTY_CYCLE=0.5,CLKOUT1_USE_FINE_PS="FALSE",CLKIN1_PERIOD=6.664,REF_JITTER1=0.0)>.

Elaborating module
<mig_7series_v1_8_memc_ui_top_axi(TCQ=100,ADDR_CMD_MODE="1T",AL="0",PAYLOAD_WIDTH=32,BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",BURST_TYPE="SEQ",CA_MIRROR="OFF",CK_WIDTH=1,COL_WIDTH=10,CMD_PIPE_PLUS1="ON",CS_WIDTH=1,nCS_PER_RANK=1,CKE_WIDTH=1,DATA_WIDTH=32,DATA_BUF_ADDR_WIDTH=5,DM_WIDTH=4,DQ_CNT_WIDTH=5,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_TYPE="DDR3",DRAM_WIDTH=8,ECC="OFF",ECC_WIDTH=0,ECC_TEST="OFF",MC_ERR_ADDR_WIDTH=29,REFCLK_FREQ=200.0,nAL=0,nBANK_MACHS=4,CKE_ODT_AUX="FALSE",nCK_PER_CLK=4,ORDERING="NORM",OUTPUT_DRV="HIGH",IBUF_LPWR_MODE="OFF",IODELAY_HP_MODE="ON",DATA_IO_IDLE_PWRDWN="ON",BANK_TYPE="HP_IO",DATA_IO_PRIM_TYPE="HP_LP",IODELAY_GRP="IODELAY_MIG",REG_CTRL="OFF",RTT_NOM="60",RTT_WR="OFF",CL=9,CWL=7,tCK=1666,tCKE=5000,tFAW=30000,tPRDI=1000000,tRAS=35000,tRCD=13750,tREFI=7800000,tRFC=300000,tRP=13750,tRRD=6000,tRTP=7500,tWTR=7500,tZQI=128000000,tZQCS=64,USER_REFRESH="OFF",TEMP_MON_EN="ON",WRLVL="ON",DEBUG_PORT="ON",CAL_WIDTH="HALF",RANK_WIDTH=32'sb01,RANKS=1,ODT_WIDTH=1,ROW_WIDTH=15,A
DDR_WIDTH=29,APP_DATA_WIDTH=256,APP_MASK_WIDTH=32'sb0100000,SIM_BYPASS_INIT_CAL="OFF",BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,DATA_CTL_B0=4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0,PHY_0_BITLANES=48'b01111111110001111111110001111111110001011111111,PHY_1_BITLANES=48'b01111111111111111111111110000000000000000000000,PHY_2_BITLANES=48'b0,CK_BYTE_MAP=144'b010011,ADDR_MAP=192'b0100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011,BANK_MAP=36'b0100101010000100100101000100100100,CAS_MAP=12'b0100100010,CKE_ODT_BYTE_MAP=8'b0,CKE_MAP=96'b0100011011,ODT_MAP=96'b0100011010,CS_MAP=120'b0100100000,PARITY_MAP=12'b0,RAS_MAP=12'b0100100011,WE_MAP=12'b0100100001,DQS_BYTE_MAP=144'b010000001000000011,DATA0_MAP=96'b0110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000,DATA1_MAP=
96'b0100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000,DATA2_MAP=96'b010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000,DATA3_MAP=96'b01000000000010000000000011000000000100000000000101000000000110000000000111,DATA4_MAP=96'b0,DATA5_MAP=96'b0,DATA6_MAP=96'b0,DATA7_MAP=96'b0,DATA8_MAP=96'b0,DATA9_MAP=96'b0,DATA10_MAP=96'b0,DATA11_MAP=96'b0,DATA12_MAP=96'b0,DATA13_MAP=96'b0,DATA14_MAP=96'b0,DATA15_MAP=96'b0,DATA16_MAP=96'b0,DATA17_MAP=96'b0,MASK0_MAP=108'b01001000000011001000000101001000000111001,MASK1_MAP=108'b0,CALIB_ROW_ADD=16'b0,CALIB_COL_ADD=12'b0,CALIB_BA_ADD=3'b0,SLOT_0_CONFIG=8'b01,SLOT_1_CONFIG=8'b0,MEM_ADDR_ORDER="BANK_ROW_COLUMN",STARVE_LIMIT=2,C_S_AXI_ID_WIDTH=4,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_S_AXI_SUPPORTS_NARROW_BURST=1,C_RD_WR_ARB_ALGORITHM="ROUND_ROBIN",C_S_AXI_REG_EN0=20'b0,C_S_AXI_REG_EN1=20'b0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_S_AXI_BASEADDR=32'b0,C_ECC_ONOFF_RESET_VALUE=1,C_EC
C_CE_COUNTER_WIDTH=8,USE_CS_PORT=1,USE_DM_PORT=1,USE_ODT_PORT=1,MASTER_PHY_CTL=1)>.

Elaborating module
<mig_7series_v1_8_mem_intfc(TCQ=100,PAYLOAD_WIDTH=32,ADDR_CMD_MODE="1T",AL="0",BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",BURST_TYPE="SEQ",CA_MIRROR="OFF",CK_WIDTH=1,COL_WIDTH=10,CMD_PIPE_PLUS1="ON",CS_WIDTH=1,nCS_PER_RANK=1,CKE_WIDTH=1,DATA_WIDTH=32,DATA_BUF_ADDR_WIDTH=5,MASTER_PHY_CTL=1,DATA_BUF_OFFSET_WIDTH=1,DDR2_DQSN_ENABLE="YES",DM_WIDTH=4,DQ_CNT_WIDTH=5,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_TYPE="DDR3",DRAM_WIDTH=8,ECC="OFF",ECC_WIDTH=0,MC_ERR_ADDR_WIDTH=29,REFCLK_FREQ=200.0,nAL=0,nBANK_MACHS=4,nCK_PER_CLK=4,ORDERING="NORM",OUTPUT_DRV="HIGH",IBUF_LPWR_MODE="OFF",IODELAY_HP_MODE="ON",BANK_TYPE="HP_IO",DATA_IO_PRIM_TYPE="HP_LP",DATA_IO_IDLE_PWRDWN="ON",IODELAY_GRP="IODELAY_MIG",REG_CTRL="OFF",RTT_NOM="60",RTT_WR="OFF",CL=9,CWL=7,tCK=1666,tCKE=5000,tFAW=30000,tPRDI=1000000,tRAS=35000,tRCD=13750,tREFI=7800000,tRFC=300000,tRP=13750,tRRD=6000,tRTP=7500,tWTR=7500,tZQI=128000000,tZQCS=64,USER_REFRESH="OFF",TEMP_MON_EN="ON",WRLVL="ON",DEBUG_PORT="ON",CAL_WIDTH="HALF",RANK_WIDTH=32'sb01,RANKS=1,ODT
_WIDTH=1,ROW_WIDTH=15,SIM_BYPASS_INIT_CAL="OFF",BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,DATA_CTL_B0=4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0,PHY_0_BITLANES=48'b01111111110001111111110001111111110001011111111,PHY_1_BITLANES=48'b01111111111111111111111110000000000000000000000,PHY_2_BITLANES=48'b0,CK_BYTE_MAP=144'b010011,ADDR_MAP=192'b0100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011,BANK_MAP=36'b0100101010000100100101000100100100,CAS_MAP=12'b0100100010,CKE_ODT_BYTE_MAP=8'b0,CKE_MAP=96'b0100011011,ODT_MAP=96'b0100011010,CKE_ODT_AUX="FALSE",CS_MAP=120'b0100100000,PARITY_MAP=12'b0,RAS_MAP=12'b0100100011,WE_MAP=12'b0100100001,DQS_BYTE_MAP=144'b010000001000000011,DATA0_MAP=96'b0110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000,DATA1_MAP=96'b01000010000001
00010000000100011000000100100000000100101000000100110000000100111000000101000,DATA2_MAP=96'b010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000,DATA3_MAP=96'b01000000000010000000000011000000000100000000000101000000000110000000000111,DATA4_MAP=96'b0,DATA5_MAP=96'b0,DATA6_MAP=96'b0,DATA7_MAP=96'b0,DATA8_MAP=96'b0,DATA9_MAP=96'b0,DATA10_MAP=96'b0,DATA11_MAP=96'b0,DATA12_MAP=96'b0,DATA13_MAP=96'b0,DATA14_MAP=96'b0,DATA15_MAP=96'b0,DATA16_MAP=96'b0,DATA17_MAP=96'b0,MASK0_MAP=108'b01001000000011001000000101001000000111001,MASK1_MAP=108'b0,SLOT_0_CONFIG=8'b01,SLOT_1_CONFIG=8'b0,CALIB_ROW_ADD=16'b0,CALIB_COL_ADD=12'b0,CALIB_BA_ADD=3'b0,STARVE_LIMIT=2,USE_CS_PORT=1,USE_DM_PORT=1,USE_ODT_PORT=1)>.
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v" Line 624: Port idle is not connected to this instance

Elaborating module <mig_7series_v1_8_mc(TCQ=100,PAYLOAD_WIDTH=32,MC_ERR_ADDR_WIDTH=29,ADDR_CMD_MODE="1T",BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",COL_WIDTH=10,CMD_PIPE_PLUS1="ON",CS_WIDTH=1,DATA_WIDTH=32,DATA_BUF_ADDR_WIDTH=5,DATA_BUF_OFFSET_WIDTH=1,DRAM_TYPE="DDR3",CKE_ODT_AUX="FALSE",DQS_WIDTH=4,DQ_WIDTH=32,ECC="OFF",ECC_WIDTH=0,nBANK_MACHS=4,nCK_PER_CLK=4,nSLOTS=1,CL=9,nCS_PER_RANK=1,CWL=7,ORDERING="NORM",RANK_WIDTH=32'sb01,RANKS=1,REG_CTRL="OFF",ROW_WIDTH=15,RTT_NOM="60",RTT_WR="OFF",STARVE_LIMIT=2,SLOT_0_CONFIG=8'b01111,SLOT_1_CONFIG=8'b0,tCK=1666,tCKE=5000,tFAW=30000,tRAS=35000,tRCD=13750,tREFI=7800000,tRFC=300000,tRP=13750,tRRD=6000,tRTP=7500,tWTR=7500,tZQI=128000000,tZQCS=64,tPRDI=1000000,USER_REFRESH="OFF")>.

Elaborating module <mig_7series_v1_8_rank_mach(BURST_MODE="8",CL=9,CWL=7,CS_WIDTH=1,DQRD2DQWR_DLY=4,DRAM_TYPE="DDR3",MAINT_PRESCALER_DIV=32'sb011110,nBANK_MACHS=4,nCKESR=32'sb0101,nCK_PER_CLK=4,nFAW=32'sb010011,nREFRESH_BANK=1,nRRD=32'sb0100,nWTR=32'sb0101,PERIODIC_RD_TIMER_DIV=32'sb0101,RANK_BM_BV_WIDTH=4,RANK_WIDTH=32'sb01,RANKS=1,REFRESH_TIMER_DIV=32'sb0100110,ZQ_TIMER_DIV=32'sb010011100010000000000)>.

Elaborating module <mig_7series_v1_8_rank_cntrl(BURST_MODE="8",ID=0,nBANK_MACHS=4,nCK_PER_CLK=4,CL=9,CWL=7,DQRD2DQWR_DLY=4,nFAW=32'sb010011,nREFRESH_BANK=1,nRRD=32'sb0100,nWTR=32'sb0101,PERIODIC_RD_TIMER_DIV=32'sb0101,RANK_BM_BV_WIDTH=4,RANK_WIDTH=32'sb01,RANKS=1,REFRESH_TIMER_DIV=32'sb0100110)>.

Elaborating module <SRLC32E(INIT=32'b0)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v" Line 220: Net <add_rrd_inhbt> does not have a driver.

Elaborating module <mig_7series_v1_8_rank_common(DRAM_TYPE="DDR3",MAINT_PRESCALER_DIV=32'sb011110,nBANK_MACHS=4,nCKESR=32'sb0101,nCK_PER_CLK=4,PERIODIC_RD_TIMER_DIV=32'sb0101,RANK_WIDTH=32'sb01,RANKS=1,REFRESH_TIMER_DIV=32'sb0100110,ZQ_TIMER_DIV=32'sb010011100010000000000)>.

Elaborating module <mig_7series_v1_8_round_robin_arb(WIDTH=3)>.

Elaborating module <mig_7series_v1_8_round_robin_arb(WIDTH=1)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v" Line 153: Net <channel[0].inh_group[0]> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_mach(TCQ=100,EVEN_CWL_2T_MODE="OFF",ADDR_CMD_MODE="1T",BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",COL_WIDTH=10,CS_WIDTH=1,CL=9,CWL=7,CKE_ODT_AUX="FALSE",DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",EARLY_WR_DATA_ADDR="OFF",ECC="OFF",LOW_IDLE_CNT=0,nBANK_MACHS=4,nCK_PER_CLK=4,nCS_PER_RANK=1,nOP_WAIT=0,nRAS=32'sb010110,nRCD=32'sb01001,nRFC=32'sb010110101,nRP=32'sb01001,nRTP=32'sb0101,nSLOTS=1,nWR=32'sb01010,nXSDLL=512,ORDERING="NORM",RANK_BM_BV_WIDTH=4,RANK_WIDTH=32'sb01,RANKS=1,ROW_WIDTH=15,RTT_NOM="60",RTT_WR="OFF",SLOT_0_CONFIG=8'b01111,SLOT_1_CONFIG=8'b0,STARVE_LIMIT=2,tZQCS=64)>.

Elaborating module <mig_7series_v1_8_bank_cntrl(TCQ=100,ADDR_CMD_MODE="1T",BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",COL_WIDTH=10,CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=0,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRCD=32'sb01001,nRTP=32'sb0101,nRP=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANK_WIDTH=32'sb01,RANKS=1,RAS_TIMER_WIDTH=32'sb011,ROW_WIDTH=15,STARVE_LIMIT=2)>.

Elaborating module <mig_7series_v1_8_bank_compare(BANK_WIDTH=3,TCQ=100,BURST_MODE="8",COL_WIDTH=10,DATA_BUF_ADDR_WIDTH=5,ECC="OFF",RANK_WIDTH=32'sb01,RANKS=1,ROW_WIDTH=15)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v" Line 168: Net <req_rank_r_lcl[0]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v" Line 169: Net <req_rank_ns[0]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v" Line 201: Net <req_col_r[14]> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_state(TCQ=100,ADDR_CMD_MODE="1T",BM_CNT_WIDTH=32'sb010,BURST_MODE="8",CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=0,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRP=32'sb01001,nRTP=32'sb0101,nRCD=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANKS=1,RANK_WIDTH=32'sb01,RAS_TIMER_WIDTH=32'sb011,STARVE_LIMIT=2)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 264: Net <rcd_active_r> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 302: Net <rmw_rd_done> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 303: Net <rd_half_rmw_lcl> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 306: Net <rmw_wait_r> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_queue(TCQ=100,BM_CNT_WIDTH=32'sb010,nBANK_MACHS=4,ORDERING="NORM",ID=0)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v" Line 500: Net <rb_hit_busies_r_lcl[7]> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_cntrl(TCQ=100,ADDR_CMD_MODE="1T",BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",COL_WIDTH=10,CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=1,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRCD=32'sb01001,nRTP=32'sb0101,nRP=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANK_WIDTH=32'sb01,RANKS=1,RAS_TIMER_WIDTH=32'sb011,ROW_WIDTH=15,STARVE_LIMIT=2)>.

Elaborating module <mig_7series_v1_8_bank_state(TCQ=100,ADDR_CMD_MODE="1T",BM_CNT_WIDTH=32'sb010,BURST_MODE="8",CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=1,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRP=32'sb01001,nRTP=32'sb0101,nRCD=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANKS=1,RANK_WIDTH=32'sb01,RAS_TIMER_WIDTH=32'sb011,STARVE_LIMIT=2)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 264: Net <rcd_active_r> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 302: Net <rmw_rd_done> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 303: Net <rd_half_rmw_lcl> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 306: Net <rmw_wait_r> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_queue(TCQ=100,BM_CNT_WIDTH=32'sb010,nBANK_MACHS=4,ORDERING="NORM",ID=1)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v" Line 500: Net <rb_hit_busies_r_lcl[7]> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_cntrl(TCQ=100,ADDR_CMD_MODE="1T",BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",COL_WIDTH=10,CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=2,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRCD=32'sb01001,nRTP=32'sb0101,nRP=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANK_WIDTH=32'sb01,RANKS=1,RAS_TIMER_WIDTH=32'sb011,ROW_WIDTH=15,STARVE_LIMIT=2)>.

Elaborating module <mig_7series_v1_8_bank_state(TCQ=100,ADDR_CMD_MODE="1T",BM_CNT_WIDTH=32'sb010,BURST_MODE="8",CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=2,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRP=32'sb01001,nRTP=32'sb0101,nRCD=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANKS=1,RANK_WIDTH=32'sb01,RAS_TIMER_WIDTH=32'sb011,STARVE_LIMIT=2)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 264: Net <rcd_active_r> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 302: Net <rmw_rd_done> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 303: Net <rd_half_rmw_lcl> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 306: Net <rmw_wait_r> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_queue(TCQ=100,BM_CNT_WIDTH=32'sb010,nBANK_MACHS=4,ORDERING="NORM",ID=2)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v" Line 500: Net <rb_hit_busies_r_lcl[7]> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_cntrl(TCQ=100,ADDR_CMD_MODE="1T",BANK_WIDTH=3,BM_CNT_WIDTH=32'sb010,BURST_MODE="8",COL_WIDTH=10,CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=3,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRCD=32'sb01001,nRTP=32'sb0101,nRP=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANK_WIDTH=32'sb01,RANKS=1,RAS_TIMER_WIDTH=32'sb011,ROW_WIDTH=15,STARVE_LIMIT=2)>.

Elaborating module <mig_7series_v1_8_bank_state(TCQ=100,ADDR_CMD_MODE="1T",BM_CNT_WIDTH=32'sb010,BURST_MODE="8",CWL=7,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",ECC="OFF",ID=3,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRAS_CLKS=32'sb0110,nRP=32'sb01001,nRTP=32'sb0101,nRCD=32'sb01001,nWTP_CLKS=32'sb0111,ORDERING="NORM",RANKS=1,RANK_WIDTH=32'sb01,RAS_TIMER_WIDTH=32'sb011,STARVE_LIMIT=2)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 264: Net <rcd_active_r> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 302: Net <rmw_rd_done> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 303: Net <rd_half_rmw_lcl> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v" Line 306: Net <rmw_wait_r> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_queue(TCQ=100,BM_CNT_WIDTH=32'sb010,nBANK_MACHS=4,ORDERING="NORM",ID=3)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v" Line 500: Net <rb_hit_busies_r_lcl[7]> does not have a driver.

Elaborating module <mig_7series_v1_8_bank_common(TCQ=100,BM_CNT_WIDTH=32'sb010,LOW_IDLE_CNT=0,nBANK_MACHS=4,nCK_PER_CLK=4,nOP_WAIT=0,nRFC=32'sb010110101,nXSDLL=512,RANK_WIDTH=32'sb01,RANKS=1,CWL=7,tZQCS=64)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_common.v" Line 438: Result of 32-bit expression is truncated to fit in 8-bit target.

Elaborating module <mig_7series_v1_8_arb_mux(TCQ=100,EVEN_CWL_2T_MODE="OFF",ADDR_CMD_MODE="1T",BANK_VECT_INDX=11,BANK_WIDTH=3,BURST_MODE="8",CS_WIDTH=1,CL=9,CWL=7,DATA_BUF_ADDR_VECT_INDX=19,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",EARLY_WR_DATA_ADDR="OFF",ECC="OFF",nBANK_MACHS=4,nCK_PER_CLK=4,nCS_PER_RANK=1,nRAS=32'sb010110,nRCD=32'sb01001,CKE_ODT_AUX="FALSE",nSLOTS=1,nWR=32'sb01010,RANKS=1,RANK_VECT_INDX=32'sb011,RANK_WIDTH=32'sb01,ROW_VECT_INDX=59,ROW_WIDTH=15,RTT_NOM="60",RTT_WR="OFF",SLOT_0_CONFIG=8'b01111,SLOT_1_CONFIG=8'b0)>.

Elaborating module <mig_7series_v1_8_arb_row_col(TCQ=100,ADDR_CMD_MODE="1T",CWL=7,EARLY_WR_DATA_ADDR="OFF",nBANK_MACHS=4,nCK_PER_CLK=4,nRAS=32'sb010110,nRCD=32'sb01001,nWR=32'sb01010)>.

Elaborating module <mig_7series_v1_8_round_robin_arb(WIDTH=4)>.

Elaborating module <mig_7series_v1_8_arb_select(TCQ=100,EVEN_CWL_2T_MODE="OFF",ADDR_CMD_MODE="1T",BANK_VECT_INDX=11,BANK_WIDTH=3,BURST_MODE="8",CS_WIDTH=1,CL=9,CWL=7,DATA_BUF_ADDR_VECT_INDX=19,DATA_BUF_ADDR_WIDTH=5,DRAM_TYPE="DDR3",EARLY_WR_DATA_ADDR="OFF",ECC="OFF",CKE_ODT_AUX="FALSE",nBANK_MACHS=4,nCK_PER_CLK=4,nCS_PER_RANK=1,nSLOTS=1,RANKS=1,RANK_VECT_INDX=32'sb011,RANK_WIDTH=32'sb01,ROW_VECT_INDX=59,ROW_WIDTH=15,RTT_NOM="60",RTT_WR="OFF",SLOT_0_CONFIG=8'b01111,SLOT_1_CONFIG=8'b0)>.
WARNING:HDLCompiler:872 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" Line 360: Using initial value of pre_cmd_r since it is never assigned
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" Line 288: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" Line 296: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" Line 304: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" Line 202: Net <col_cmd_r[21]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" Line 203: Net <row_cmd_r[21]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v" Line 390: Net <col_mux.col_row_r[14]> does not have a driver.

Elaborating module <mig_7series_v1_8_col_mach(TCQ=100,BANK_WIDTH=3,BURST_MODE="8",COL_WIDTH=10,CS_WIDTH=1,DATA_BUF_ADDR_WIDTH=5,DATA_BUF_OFFSET_WIDTH=1,DELAY_WR_DATA_CNTRL=1,DQS_WIDTH=4,DRAM_TYPE="DDR3",EARLY_WR_DATA_ADDR="OFF",ECC="OFF",MC_ERR_ADDR_WIDTH=29,nCK_PER_CLK=4,nPHY_WRLAT=2,RANK_WIDTH=32'sb01,ROW_WIDTH=15)>.

Elaborating module <RAM32M(INIT_A=64'b0,INIT_B=64'b0,INIT_C=64'b0,INIT_D=64'b0)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_col_mach.v" Line 148: Net <offset_r[1]> does not have a driver.

Elaborating module
<mig_7series_v1_8_ddr_phy_top(TCQ=100,REFCLK_FREQ=200.0,BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,PHY_0_BITLANES=48'b01111111110001111111110001111111110001011111111,PHY_1_BITLANES=48'b01111111111111111111111110000000000000000000000,PHY_2_BITLANES=48'b0,CA_MIRROR="OFF",CK_BYTE_MAP=144'b010011,ADDR_MAP=192'b0100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011,BANK_MAP=36'b0100101010000100100101000100100100,CAS_MAP=12'b0100100010,CKE_ODT_BYTE_MAP=8'b0,CKE_MAP=96'b0100011011,ODT_MAP=96'b0100011010,CKE_ODT_AUX="FALSE",CS_MAP=120'b0100100000,PARITY_MAP=12'b0,RAS_MAP=12'b0100100011,WE_MAP=12'b0100100001,DQS_BYTE_MAP=144'b010000001000000011,DATA0_MAP=96'b0110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000,DATA1_MAP=96'b010000100000010001000000010001100000010010000000010010100000010011000000010011
1000000101000,DATA2_MAP=96'b010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000,DATA3_MAP=96'b01000000000010000000000011000000000100000000000101000000000110000000000111,DATA4_MAP=96'b0,DATA5_MAP=96'b0,DATA6_MAP=96'b0,DATA7_MAP=96'b0,DATA8_MAP=96'b0,DATA9_MAP=96'b0,DATA10_MAP=96'b0,DATA11_MAP=96'b0,DATA12_MAP=96'b0,DATA13_MAP=96'b0,DATA14_MAP=96'b0,DATA15_MAP=96'b0,DATA16_MAP=96'b0,DATA17_MAP=96'b0,MASK0_MAP=108'b01001000000011001000000101001000000111001,MASK1_MAP=108'b0,CALIB_ROW_ADD=16'b0,CALIB_COL_ADD=12'b0,CALIB_BA_ADD=3'b0,nCS_PER_RANK=1,CS_WIDTH=1,nCK_PER_CLK=4,PRE_REV3ES="OFF",CKE_WIDTH=1,DATA_CTL_B0=4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0,DDR2_DQSN_ENABLE="YES",DRAM_TYPE="DDR3",BANK_WIDTH=3,CK_WIDTH=1,COL_WIDTH=10,DM_WIDTH=4,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_WIDTH=8,PHYCTL_CMD_FIFO="FALSE",ROW_WIDTH=15,AL="0",ADDR_CMD_MODE="1T",BURST_MODE="8",BURST_TYPE="SEQ",CL=9,CWL=7,tRFC=300000,tCK=1666,OUTPUT_DRV="HIGH",RANKS=1,O
DT_WIDTH=1,REG_CTRL="OFF",RTT_NOM="60",RTT_WR="OFF",SLOT_1_CONFIG=8'b0,WRLVL="ON",IODELAY_HP_MODE="ON",BANK_TYPE="HP_IO",DATA_IO_PRIM_TYPE="HP_LP",DATA_IO_IDLE_PWRDWN="ON",IODELAY_GRP="IODELAY_MIG",USE_CS_PORT=1,USE_DM_PORT=1,USE_ODT_PORT=1,MASTER_PHY_CTL=1,DEBUG_PORT="ON")>.
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 1293: Port afull is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 1321: Port of_data_a_full is not connected to this instance

Elaborating module
<mig_7series_v1_8_ddr_mc_phy_wrapper(TCQ=100,tCK=1666,BANK_TYPE="HP_IO",DATA_IO_PRIM_TYPE="HP_LP",DATA_IO_IDLE_PWRDWN="ON",IODELAY_GRP="IODELAY_MIG",nCK_PER_CLK=4,nCS_PER_RANK=1,BANK_WIDTH=3,CKE_WIDTH=1,CS_WIDTH=1,CK_WIDTH=1,LP_DDR_CK_WIDTH=2,DDR2_DQSN_ENABLE="YES",CWL=7,DM_WIDTH=4,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_TYPE="DDR3",RANKS=1,ODT_WIDTH=1,REG_CTRL="OFF",ROW_WIDTH=15,USE_CS_PORT=1,USE_DM_PORT=1,USE_ODT_PORT=1,IBUF_LPWR_MODE="OFF",PHYCTL_CMD_FIFO="FALSE",DATA_CTL_B0=4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0,BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,PHY_0_BITLANES=48'b01111111110001111111110001111111110001011111111,PHY_1_BITLANES=48'b01111111111111111111111110000000000000000000000,PHY_2_BITLANES=48'b0,HIGHEST_BANK=2,HIGHEST_LANE=8,CK_BYTE_MAP=144'b010011,ADDR_MAP=192'b0100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100
101000000100100111000100100110000100101011,BANK_MAP=36'b0100101010000100100101000100100100,CAS_MAP=12'b0100100010,CKE_ODT_BYTE_MAP=8'b0,CKE_MAP=96'b0100011011,ODT_MAP=96'b0100011010,CKE_ODT_AUX="FALSE",CS_MAP=120'b0100100000,PARITY_MAP=12'b0,RAS_MAP=12'b0100100011,WE_MAP=12'b0100100001,DQS_BYTE_MAP=144'b010000001000000011,DATA0_MAP=96'b0110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000,DATA1_MAP=96'b0100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000,DATA2_MAP=96'b010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000,DATA3_MAP=96'b01000000000010000000000011000000000100000000000101000000000110000000000111,DATA4_MAP=96'b0,DATA5_MAP=96'b0,DATA6_MAP=96'b0,DATA7_MAP=96'b0,DATA8_MAP=96'b0,DATA9_MAP=96'b0,DATA10_MAP=96'b0,DATA11_MAP=96'b0,DATA12_MAP=96'b0,DATA13_MAP=96'b0,DATA14_MAP=96'b0,DATA15_MAP=96'b0,DATA16_MAP=96'b0,DATA17_MAP=96'b0,MASK0_MAP=108'b01001000000011001000000101001000000111001,MASK1
_MAP=108'b0,SIM_CAL_OPTION="NONE",MASTER_PHY_CTL=1)>.

Elaborating module <OBUF>.

Elaborating module <OBUFT>.

Elaborating module <IOBUF_DCIEN(IBUF_LOW_PWR="FALSE")>.

Elaborating module <IOBUFDS_DCIEN(IBUF_LOW_PWR="FALSE",DQS_BIAS="TRUE")>.

Elaborating module <mig_7series_v1_8_ddr_of_pre_fifo(TCQ=25,DEPTH=8,WIDTH=44)>.

Elaborating module
<mig_7series_v1_8_ddr_mc_phy(BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,DATA_CTL_B0=4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0,PHY_0_BITLANES=48'b01111111110001111111110001111111110001011111111,PHY_1_BITLANES=48'b01111111111111111111111110000000000000000000000,PHY_2_BITLANES=48'b0,PHY_0_BITLANES_OUTONLY=48'b01000000000001000000000001000000000001000000000,PHY_1_BITLANES_OUTONLY=48'b0,PHY_2_BITLANES_OUTONLY=48'b0,RCLK_SELECT_BANK=1,RCLK_SELECT_LANE="B",GENERATE_DDR_CK_MAP=16'b011000101000100,BYTELANES_DDR_CK=72'b01000000000000000000000000000,NUM_DDR_CK=1,LP_DDR_CK_WIDTH=2,PO_CTL_COARSE_BYPASS="FALSE",PHYCTL_CMD_FIFO="FALSE",PHY_CLK_RATIO=4,MASTER_PHY_CTL=1,PHY_FOUR_WINDOW_CLOCKS=63,PHY_EVENTS_DELAY=18,PHY_COUNT_EN="FALSE",PHY_SYNC_MODE="FALSE",SYNTHESIS="TRUE",PHY_DISABLE_SEQ_MATCH="TRUE",PHY_0_GENERATE_IDELAYCTRL="FALSE",PHY_0_A_PI_FREQ_REF_DIV="NONE",PHY_0_CMD_OFFSET=8,PHY_0_RD_CMD_OFFSET_0=10,PHY_0_RD_CMD_OFFSET_1=10,P
HY_0_RD_CMD_OFFSET_2=10,PHY_0_RD_CMD_OFFSET_3=10,PHY_0_RD_DURATION_0=6,PHY_0_RD_DURATION_1=6,PHY_0_RD_DURATION_2=6,PHY_0_RD_DURATION_3=6,PHY_0_WR_CMD_OFFSET_0=8,PHY_0_WR_CMD_OFFSET_1=8,PHY_0_WR_CMD_OFFSET_2=8,PHY_0_WR_CMD_OFFSET_3=8,PHY_0_WR_DURATION_0=7,PHY_0_WR_DURATION_1=7,PHY_0_WR_DURATION_2=7,PHY_0_WR_DURATION_3=7,PHY_0_AO_TOGGLE=4'b01,PHY_0_A_PO_OCLK_DELAY=30,PHY_0_B_PO_OCLK_DELAY=30,PHY_0_C_PO_OCLK_DELAY=30,PHY_0_D_PO_OCLK_DELAY=30,PHY_0_A_PO_OCLKDELAY_INV="TRUE",PHY_0_A_IDELAYE2_IDELAY_VALUE=0,PHY_0_B_IDELAYE2_IDELAY_VALUE=0,PHY_0_C_IDELAYE2_IDELAY_VALUE=0,PHY_0_D_IDELAYE2_IDELAY_VALUE=0,PHY_1_GENERATE_IDELAYCTRL="FALSE",PHY_1_A_PO_OCLK_DELAY=30,PHY_1_B_PO_OCLK_DELAY=30,PHY_1_C_PO_OCLK_DELAY=30,PHY_1_D_PO_OCLK_DELAY=30,PHY_1_A_IDELAYE2_IDELAY_VALUE=0,PHY_1_B_IDELAYE2_IDELAY_VALUE=0,PHY_1_C_IDELAYE2_IDELAY_VALUE=0,PHY_1_D_IDELAYE2_IDELAY_VALUE=0,PHY_2_GENERATE_IDELAYCTRL="FALSE",PHY_2_A_PO_OCLK_DELAY=30,PHY_2_B_PO_OCLK_DELAY=30,PHY_2_C_PO_OCLK_DELAY=30,PHY_2_D_PO_OCLK_DELAY=30,PHY_2_A_IDELAYE2_IDELAY_V
ALUE=0,PHY_2_B_IDELAYE2_IDELAY_VALUE=0,PHY_2_C_IDELAYE2_IDELAY_VALUE=0,PHY_2_D_IDELAYE2_IDELAY_VALUE=0,TCK=1666,PHY_0_IODELAY_GRP="IODELAY_MIG",PHY_1_IODELAY_GRP="IODELAY_MIG",PHY_2_IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",CKE_ODT_AUX="FALSE")>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" Line 634: Result of 64-bit expression is truncated to fit in 32-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" Line 635: Result of 64-bit expression is truncated to fit in 32-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" Line 650: Result of 64-bit expression is truncated to fit in 32-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" Line 878: Result of 48-bit expression is truncated to fit in 2-bit target.

Elaborating module
<mig_7series_v1_8_ddr_phy_4lanes(BYTE_LANES=4'b1111,DATA_CTL_N=4'b1111,PO_CTL_COARSE_BYPASS="FALSE",PO_FINE_DELAY=60,BITLANES=48'b01111111110001111111110001111111110001011111111,BITLANES_OUTONLY=48'b01000000000001000000000001000000000001000000000,BYTELANES_DDR_CK=72'b0,LAST_BANK="FALSE",LANE_REMAP=16'b011001000010000,OF_ALMOST_FULL_VALUE=1,IF_ALMOST_EMPTY_VALUE=1,GENERATE_IDELAYCTRL="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",NUM_DDR_CK=1,TCK=1666,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",PC_CLK_RATIO=4,PC_EVENTS_DELAY=18,PC_FOUR_WINDOW_CLOCKS=63,PC_BURST_MODE="TRUE",PC_SYNC_MODE="FALSE",PC_MULTI_REGION="TRUE",PC_PHY_COUNT_EN="FALSE",PC_DISABLE_SEQ_MATCH="TRUE",PC_CMD_OFFSET=8,PC_RD_CMD_OFFSET_0=10,PC_RD_CMD_OFFSET_1=10,PC_RD_CMD_OFFSET_2=10,PC_RD_CMD_OFFSET_3=10,PC_RD_DURATION_0=6,PC_RD_DURATION_1=6,PC_RD_DURATION_2=6,PC_RD_DURATION_3=6,PC_WR_CMD_OFFSET_0=8,PC_WR_CMD_OFFSET_1=8,PC_WR_CMD_OFFSET_2=8,PC_WR_CMD_OFFSET_3=8,PC_WR_DURATION_0=7,PC_WR_DURATION_1=7,PC_WR_DURATION_2=7,PC_W
R_DURATION_3=7,PC_AO_WRLVL_EN=0,PC_AO_TOGGLE=4'b01,PI_SEL_CLK_OFFSET=6,A_PI_FINE_DELAY=33,B_PI_FINE_DELAY=33,C_PI_FINE_DELAY=33,D_PI_FINE_DELAY=33,A_PI_FREQ_REF_DIV="NONE",A_PI_BURST_MODE="TRUE",A_PI_OUTPUT_CLK_SRC="DELAYED_REF",B_PI_OUTPUT_CLK_SRC="DELAYED_REF",C_PI_OUTPUT_CLK_SRC="DELAYED_REF",D_PI_OUTPUT_CLK_SRC="DELAYED_REF",A_PO_OUTPUT_CLK_SRC="DELAYED_REF",A_PO_OCLK_DELAY=30,A_PO_OCLKDELAY_INV="TRUE",A_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",B_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",C_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",D_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",A_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",B_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",C_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",D_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",A_OS_DATA_RATE="UNDECLARED",A_OS_DATA_WIDTH="UNDECLARED",B_OS_DATA_RATE="UNDECLARED",B_OS_DATA_WIDTH="UNDECLARED",C_OS_DATA_RATE="UNDECLARED",C_OS_DATA_WIDTH="UNDECLARED",D_OS_DATA_RATE="UNDECLARED",D_OS_DATA_WIDTH="UNDECLARED",A_IDELAYE2_IDELAY_TYPE="VARIABLE",A_IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" Line 617: Assignment to if_full ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" Line 618: Assignment to of_empty ignored, since the identifier is never used

Elaborating module <BUFIO>.

Elaborating module <mig_7series_v1_8_ddr_byte_lane(ABCD="A",PO_DATA_CTL="TRUE",BITLANES=12'b01011111111,BITLANES_OUTONLY=12'b01000000000,OF_ALMOST_EMPTY_VALUE=1,OF_ALMOST_FULL_VALUE=1,OF_SYNCHRONOUS_MODE="FALSE",IF_ALMOST_EMPTY_VALUE=1,IF_ALMOST_FULL_VALUE=1,IF_SYNCHRONOUS_MODE="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",BYTELANES_DDR_CK=72'b0,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",TCK=1666,PC_CLK_RATIO=4,PI_BURST_MODE="TRUE",PI_CLKOUT_DIV=2,PI_FREQ_REF_DIV="NONE",PI_FINE_DELAY=33,PI_OUTPUT_CLK_SRC="DELAYED_REF",PI_SYNC_IN_DIV_RST="TRUE",PI_SEL_CLK_OFFSET=6,PO_CLKOUT_DIV=2,PO_FINE_DELAY=60,PO_COARSE_BYPASS="FALSE",PO_COARSE_DELAY=0,PO_OCLK_DELAY=30,PO_OCLKDELAY_INV="TRUE",PO_OUTPUT_CLK_SRC="DELAYED_REF",PO_SYNC_IN_DIV_RST="TRUE",OSERDES_DATA_RATE="UNDECLARED",OSERDES_DATA_WIDTH="UNDECLARED",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.

Elaborating module <mig_7series_v1_8_ddr_if_post_fifo(TCQ=25,DEPTH=4,WIDTH=80)>.

Elaborating module <mig_7series_v1_8_ddr_of_pre_fifo(TCQ=25,DEPTH=9,WIDTH=80)>.

Elaborating module <PHASER_IN_PHY(BURST_MODE="TRUE",CLKOUT_DIV=2,DQS_AUTO_RECAL=0,DQS_FIND_PATTERN="000",SEL_CLK_OFFSET=6,FINE_DELAY=33,FREQ_REF_DIV="NONE",OUTPUT_CLK_SRC="DELAYED_REF",SYNC_IN_DIV_RST="TRUE",REFCLK_PERIOD=1.666,MEMREFCLK_PERIOD=1.666,PHASEREFCLK_PERIOD=1.666)>.
WARNING:HDLCompiler:413 - "/build/xfndry10/P.49d/rtf/devlib/verilog/src/iSE/unisim_comp.v" Line 28433: Result of 22-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:1843 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 435: Possible conversion of parameter value of DQS_FIND_PATTERN to fit the type of formal

Elaborating module <PHASER_OUT_PHY(CLKOUT_DIV=2,DATA_CTL_N="TRUE",FINE_DELAY=60,COARSE_BYPASS="FALSE",COARSE_DELAY=0,OCLK_DELAY=30,OCLKDELAY_INV="TRUE",OUTPUT_CLK_SRC="DELAYED_REF",SYNC_IN_DIV_RST="TRUE",REFCLK_PERIOD=1.666,PHASEREFCLK_PERIOD=1,PO=3'b111,MEMREFCLK_PERIOD=1.666)>.

Elaborating module <IN_FIFO(ALMOST_EMPTY_VALUE=1,ALMOST_FULL_VALUE=1,ARRAY_MODE="ARRAY_MODE_4_X_8",SYNCHRONOUS_MODE="FALSE")>.

Elaborating module <OUT_FIFO(ALMOST_EMPTY_VALUE=1,ALMOST_FULL_VALUE=1,ARRAY_MODE="ARRAY_MODE_8_X_4",OUTPUT_DISABLE="FALSE",SYNCHRONOUS_MODE="FALSE")>.
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 184: Port Q7 is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 308: Port D7 is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 356: Port TBYTEOUT is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 398: Port TBYTEOUT is not connected to this instance

Elaborating module <mig_7series_v1_8_ddr_byte_group_io(PO_DATA_CTL="TRUE",BITLANES=12'b01011111111,BITLANES_OUTONLY=12'b01000000000,OSERDES_DATA_RATE="DDR",OSERDES_DATA_WIDTH=4,IODELAY_GRP="IODELAY_MIG",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,SYNTHESIS="TRUE")>.

Elaborating module <ISERDESE2(DATA_RATE="DDR",DATA_WIDTH=4,DYN_CLKDIV_INV_EN="FALSE",DYN_CLK_INV_EN="FALSE",INIT_Q1=1'b0,INIT_Q2=1'b0,INIT_Q3=1'b0,INIT_Q4=1'b0,INTERFACE_TYPE="MEMORY_DDR3",NUM_CE=2,IOBDELAY="IFD",OFB_USED="FALSE",SERDES_MODE="MASTER",SRVAL_Q1=1'b0,SRVAL_Q2=1'b0,SRVAL_Q3=1'b0,SRVAL_Q4=1'b0)>.

Elaborating module <IDELAYE2(CINVCTRL_SEL="FALSE",DELAY_SRC="IDATAIN",HIGH_PERFORMANCE_MODE="TRUE",IDELAY_TYPE="VARIABLE",IDELAY_VALUE=0,PIPE_SEL="FALSE",REFCLK_FREQUENCY=200.0,SIGNAL_PATTERN="DATA")>.

Elaborating module <OSERDESE2(DATA_RATE_OQ="DDR",DATA_RATE_TQ="DDR",DATA_WIDTH=4,INIT_OQ=1'b1,INIT_TQ=1'b1,SERDES_MODE="MASTER",SRVAL_OQ=1'b1,SRVAL_TQ=1'b1,TRISTATE_WIDTH=4,TBYTE_CTL="TRUE",TBYTE_SRC="TRUE")>.

Elaborating module <OSERDESE2(DATA_RATE_OQ="DDR",DATA_RATE_TQ="DDR",DATA_WIDTH=4,INIT_OQ=1'b1,INIT_TQ=1'b1,SERDES_MODE="MASTER",SRVAL_OQ=1'b1,SRVAL_TQ=1'b1,TRISTATE_WIDTH=4,TBYTE_CTL="TRUE",TBYTE_SRC="FALSE")>.

Elaborating module <ODDR(DDR_CLK_EDGE="SAME_EDGE")>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 136: Net <oserdes_dq_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 137: Net <oserdes_dqts_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 263: Net <dummy_i5[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 264: Net <dummy_i6[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 266: Net <of_dqbus[47]> does not have a driver.

Elaborating module <mig_7series_v1_8_ddr_byte_lane(ABCD="B",PO_DATA_CTL="TRUE",BITLANES=12'b01111111110,BITLANES_OUTONLY=12'b01000000000,OF_ALMOST_EMPTY_VALUE=1,OF_ALMOST_FULL_VALUE=1,OF_SYNCHRONOUS_MODE="FALSE",IF_ALMOST_EMPTY_VALUE=1,IF_ALMOST_FULL_VALUE=1,IF_SYNCHRONOUS_MODE="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",BYTELANES_DDR_CK=72'b0,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",TCK=1666,PC_CLK_RATIO=4,PI_BURST_MODE="TRUE",PI_CLKOUT_DIV=2,PI_FREQ_REF_DIV="NONE",PI_FINE_DELAY=33,PI_OUTPUT_CLK_SRC="DELAYED_REF",PI_SYNC_IN_DIV_RST="TRUE",PI_SEL_CLK_OFFSET=6,PO_CLKOUT_DIV=2,PO_FINE_DELAY=60,PO_COARSE_BYPASS="FALSE",PO_COARSE_DELAY=0,PO_OCLK_DELAY=30,PO_OCLKDELAY_INV="TRUE",PO_OUTPUT_CLK_SRC="DELAYED_REF",PO_SYNC_IN_DIV_RST="TRUE",OSERDES_DATA_RATE="UNDECLARED",OSERDES_DATA_WIDTH="UNDECLARED",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.

Elaborating module <mig_7series_v1_8_ddr_byte_group_io(PO_DATA_CTL="TRUE",BITLANES=12'b01111111110,BITLANES_OUTONLY=12'b01000000000,OSERDES_DATA_RATE="DDR",OSERDES_DATA_WIDTH=4,IODELAY_GRP="IODELAY_MIG",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,SYNTHESIS="TRUE")>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 136: Net <oserdes_dq_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 137: Net <oserdes_dqts_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 263: Net <dummy_i5[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 264: Net <dummy_i6[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 266: Net <of_dqbus[47]> does not have a driver.

Elaborating module <mig_7series_v1_8_ddr_byte_lane(ABCD="C",PO_DATA_CTL="TRUE",BITLANES=12'b01111111110,BITLANES_OUTONLY=12'b01000000000,OF_ALMOST_EMPTY_VALUE=1,OF_ALMOST_FULL_VALUE=1,OF_SYNCHRONOUS_MODE="FALSE",IF_ALMOST_EMPTY_VALUE=1,IF_ALMOST_FULL_VALUE=1,IF_SYNCHRONOUS_MODE="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",BYTELANES_DDR_CK=72'b0,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",TCK=1666,PC_CLK_RATIO=4,PI_BURST_MODE="TRUE",PI_CLKOUT_DIV=2,PI_FREQ_REF_DIV="NONE",PI_FINE_DELAY=33,PI_OUTPUT_CLK_SRC="DELAYED_REF",PI_SYNC_IN_DIV_RST="TRUE",PI_SEL_CLK_OFFSET=6,PO_CLKOUT_DIV=2,PO_FINE_DELAY=60,PO_COARSE_BYPASS="FALSE",PO_COARSE_DELAY=0,PO_OCLK_DELAY=30,PO_OCLKDELAY_INV="TRUE",PO_OUTPUT_CLK_SRC="DELAYED_REF",PO_SYNC_IN_DIV_RST="TRUE",OSERDES_DATA_RATE="UNDECLARED",OSERDES_DATA_WIDTH="UNDECLARED",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 263: Net <dummy_i5[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 264: Net <dummy_i6[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 266: Net <of_dqbus[47]> does not have a driver.

Elaborating module <mig_7series_v1_8_ddr_byte_lane(ABCD="D",PO_DATA_CTL="TRUE",BITLANES=12'b01111111110,BITLANES_OUTONLY=12'b01000000000,OF_ALMOST_EMPTY_VALUE=1,OF_ALMOST_FULL_VALUE=1,OF_SYNCHRONOUS_MODE="FALSE",IF_ALMOST_EMPTY_VALUE=1,IF_ALMOST_FULL_VALUE=1,IF_SYNCHRONOUS_MODE="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",BYTELANES_DDR_CK=72'b0,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",TCK=1666,PC_CLK_RATIO=4,PI_BURST_MODE="TRUE",PI_CLKOUT_DIV=2,PI_FREQ_REF_DIV="NONE",PI_FINE_DELAY=33,PI_OUTPUT_CLK_SRC="DELAYED_REF",PI_SYNC_IN_DIV_RST="TRUE",PI_SEL_CLK_OFFSET=6,PO_CLKOUT_DIV=2,PO_FINE_DELAY=60,PO_COARSE_BYPASS="FALSE",PO_COARSE_DELAY=0,PO_OCLK_DELAY=30,PO_OCLKDELAY_INV="TRUE",PO_OUTPUT_CLK_SRC="DELAYED_REF",PO_SYNC_IN_DIV_RST="TRUE",OSERDES_DATA_RATE="UNDECLARED",OSERDES_DATA_WIDTH="UNDECLARED",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 263: Net <dummy_i5[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 264: Net <dummy_i6[3]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 266: Net <of_dqbus[47]> does not have a driver.

Elaborating module <PHY_CONTROL(AO_WRLVL_EN=0,AO_TOGGLE=4'b01,BURST_MODE="TRUE",CO_DURATION=1,CLK_RATIO=4,DATA_CTL_A_N="TRUE",DATA_CTL_B_N="TRUE",DATA_CTL_C_N="TRUE",DATA_CTL_D_N="TRUE",DI_DURATION=1,DO_DURATION=1,EVENTS_DELAY=18,FOUR_WINDOW_CLOCKS=63,MULTI_REGION="TRUE",PHY_COUNT_ENABLE="FALSE",DISABLE_SEQ_MATCH="TRUE",SYNC_MODE="FALSE",CMD_OFFSET=8,RD_CMD_OFFSET_0=10,RD_CMD_OFFSET_1=10,RD_CMD_OFFSET_2=10,RD_CMD_OFFSET_3=10,RD_DURATION_0=6,RD_DURATION_1=6,RD_DURATION_2=6,RD_DURATION_3=6,WR_CMD_OFFSET_0=8,WR_CMD_OFFSET_1=8,WR_CMD_OFFSET_2=8,WR_CMD_OFFSET_3=8,WR_DURATION_0=7,WR_DURATION_1=7,WR_DURATION_2=7,WR_DURATION_3=7)>.

Elaborating module <PHASER_REF>.

Elaborating module
<mig_7series_v1_8_ddr_phy_4lanes(BYTE_LANES=4'b1110,DATA_CTL_N=4'b0,PO_CTL_COARSE_BYPASS="FALSE",PO_FINE_DELAY=60,BITLANES=48'b01111111111111111111111110000000000000000000000,BITLANES_OUTONLY=48'b0,BYTELANES_DDR_CK=72'b01000,LAST_BANK="FALSE",LANE_REMAP=16'b011001000010000,OF_ALMOST_FULL_VALUE=1,IF_ALMOST_EMPTY_VALUE=1,GENERATE_IDELAYCTRL="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",NUM_DDR_CK=1,TCK=1666,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",PC_CLK_RATIO=4,PC_EVENTS_DELAY=18,PC_FOUR_WINDOW_CLOCKS=63,PC_BURST_MODE="TRUE",PC_SYNC_MODE="FALSE",PC_MULTI_REGION="TRUE",PC_PHY_COUNT_EN="FALSE",PC_DISABLE_SEQ_MATCH="TRUE",PC_CMD_OFFSET=8,PC_RD_CMD_OFFSET_0=10,PC_RD_CMD_OFFSET_1=10,PC_RD_CMD_OFFSET_2=10,PC_RD_CMD_OFFSET_3=10,PC_RD_DURATION_0=6,PC_RD_DURATION_1=6,PC_RD_DURATION_2=6,PC_RD_DURATION_3=6,PC_WR_CMD_OFFSET_0=8,PC_WR_CMD_OFFSET_1=8,PC_WR_CMD_OFFSET_2=8,PC_WR_CMD_OFFSET_3=8,PC_WR_DURATION_0=7,PC_WR_DURATION_1=7,PC_WR_DURATION_2=7,PC_WR_DURATION_3=7,PC_AO_WRLVL_EN=0,PC_AO_TOGGLE=
4'b01,PI_SEL_CLK_OFFSET=6,A_PI_FINE_DELAY=32'sb010000,B_PI_FINE_DELAY=32'sb010000,C_PI_FINE_DELAY=32'sb010000,D_PI_FINE_DELAY=32'sb010000,A_PI_FREQ_REF_DIV="NONE",A_PI_BURST_MODE="TRUE",A_PI_OUTPUT_CLK_SRC="DELAYED_REF",B_PI_OUTPUT_CLK_SRC="DELAYED_MEM_REF",C_PI_OUTPUT_CLK_SRC="DELAYED_REF",D_PI_OUTPUT_CLK_SRC="DELAYED_REF",A_PO_OUTPUT_CLK_SRC="DELAYED_REF",A_PO_OCLK_DELAY=30,A_PO_OCLKDELAY_INV="TRUE",A_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",B_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",C_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",D_OF_ARRAY_MODE="ARRAY_MODE_8_X_4",A_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",B_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",C_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",D_IF_ARRAY_MODE="ARRAY_MODE_8_X_4",A_OS_DATA_RATE="UNDECLARED",A_OS_DATA_WIDTH="UNDECLARED",B_OS_DATA_RATE="UNDECLARED",B_OS_DATA_WIDTH="UNDECLARED",C_OS_DATA_RATE="UNDECLARED",C_OS_DATA_WIDTH="UNDECLARED",D_OS_DATA_RATE="UNDECLARED",D_OS_DATA_WIDTH="UNDECLARED",A_IDELAYE2_IDELAY_TYPE="VARIABLE",A_IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" Line 617: Assignment to if_full ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" Line 618: Assignment to of_empty ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ddr_byte_lane(ABCD="B",PO_DATA_CTL="FALSE",BITLANES=12'b110000000000,BITLANES_OUTONLY=12'b0,OF_ALMOST_EMPTY_VALUE=1,OF_ALMOST_FULL_VALUE=1,OF_SYNCHRONOUS_MODE="FALSE",IF_ALMOST_EMPTY_VALUE=1,IF_ALMOST_FULL_VALUE=1,IF_SYNCHRONOUS_MODE="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",BYTELANES_DDR_CK=72'b01000,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",TCK=1666,PC_CLK_RATIO=4,PI_BURST_MODE="TRUE",PI_CLKOUT_DIV=2,PI_FREQ_REF_DIV="NONE",PI_FINE_DELAY=32'sb010000,PI_OUTPUT_CLK_SRC="DELAYED_MEM_REF",PI_SYNC_IN_DIV_RST="TRUE",PI_SEL_CLK_OFFSET=6,PO_CLKOUT_DIV=4,PO_FINE_DELAY=60,PO_COARSE_BYPASS="FALSE",PO_COARSE_DELAY=0,PO_OCLK_DELAY=30,PO_OCLKDELAY_INV="TRUE",PO_OUTPUT_CLK_SRC="DELAYED_REF",PO_SYNC_IN_DIV_RST="TRUE",OSERDES_DATA_RATE="UNDECLARED",OSERDES_DATA_WIDTH="UNDECLARED",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.

Elaborating module <PHASER_OUT_PHY(CLKOUT_DIV=4,DATA_CTL_N="FALSE",FINE_DELAY=60,COARSE_BYPASS="FALSE",COARSE_DELAY=0,OCLK_DELAY=30,OCLKDELAY_INV="TRUE",OUTPUT_CLK_SRC="DELAYED_REF",SYNC_IN_DIV_RST="TRUE",REFCLK_PERIOD=1.666,PHASEREFCLK_PERIOD=1,PO=3'b111,MEMREFCLK_PERIOD=1.666)>.

Elaborating module <OUT_FIFO(ALMOST_EMPTY_VALUE=1,ALMOST_FULL_VALUE=1,ARRAY_MODE="ARRAY_MODE_4_X_4",OUTPUT_DISABLE="FALSE",SYNCHRONOUS_MODE="FALSE")>.

Elaborating module <mig_7series_v1_8_ddr_byte_group_io(PO_DATA_CTL="FALSE",BITLANES=12'b110000000000,BITLANES_OUTONLY=12'b0,OSERDES_DATA_RATE="SDR",OSERDES_DATA_WIDTH=4,IODELAY_GRP="IODELAY_MIG",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,SYNTHESIS="TRUE")>.

Elaborating module <OSERDESE2(DATA_RATE_OQ="SDR",DATA_RATE_TQ="SDR",DATA_WIDTH=4,INIT_OQ=1'b0,INIT_TQ=1'b1,SERDES_MODE="MASTER",SRVAL_OQ=1'b0,SRVAL_TQ=1'b1,TRISTATE_WIDTH=1)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 136: Net <oserdes_dq_buf[9]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 137: Net <oserdes_dqts_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 138: Net <oserdes_dqs_buf> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 139: Net <oserdes_dqsts_buf> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 269: Net <iserdes_clk> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 270: Net <iserdes_clkdiv> does not have a driver.

Elaborating module <mig_7series_v1_8_ddr_byte_lane(ABCD="C",PO_DATA_CTL="FALSE",BITLANES=12'b111111111111,BITLANES_OUTONLY=12'b0,OF_ALMOST_EMPTY_VALUE=1,OF_ALMOST_FULL_VALUE=1,OF_SYNCHRONOUS_MODE="FALSE",IF_ALMOST_EMPTY_VALUE=1,IF_ALMOST_FULL_VALUE=1,IF_SYNCHRONOUS_MODE="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",BYTELANES_DDR_CK=72'b01000,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",TCK=1666,PC_CLK_RATIO=4,PI_BURST_MODE="TRUE",PI_CLKOUT_DIV=2,PI_FREQ_REF_DIV="NONE",PI_FINE_DELAY=32'sb010000,PI_OUTPUT_CLK_SRC="DELAYED_REF",PI_SYNC_IN_DIV_RST="TRUE",PI_SEL_CLK_OFFSET=6,PO_CLKOUT_DIV=4,PO_FINE_DELAY=60,PO_COARSE_BYPASS="FALSE",PO_COARSE_DELAY=0,PO_OCLK_DELAY=30,PO_OCLKDELAY_INV="TRUE",PO_OUTPUT_CLK_SRC="DELAYED_REF",PO_SYNC_IN_DIV_RST="TRUE",OSERDES_DATA_RATE="UNDECLARED",OSERDES_DATA_WIDTH="UNDECLARED",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.

Elaborating module <mig_7series_v1_8_ddr_byte_group_io(PO_DATA_CTL="FALSE",BITLANES=12'b111111111111,BITLANES_OUTONLY=12'b0,OSERDES_DATA_RATE="SDR",OSERDES_DATA_WIDTH=4,IODELAY_GRP="IODELAY_MIG",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,SYNTHESIS="TRUE")>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 137: Net <oserdes_dqts_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 138: Net <oserdes_dqs_buf> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 139: Net <oserdes_dqsts_buf> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 269: Net <iserdes_clk> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 270: Net <iserdes_clkdiv> does not have a driver.

Elaborating module <mig_7series_v1_8_ddr_byte_lane(ABCD="D",PO_DATA_CTL="FALSE",BITLANES=12'b01111111111,BITLANES_OUTONLY=12'b0,OF_ALMOST_EMPTY_VALUE=1,OF_ALMOST_FULL_VALUE=1,OF_SYNCHRONOUS_MODE="FALSE",IF_ALMOST_EMPTY_VALUE=1,IF_ALMOST_FULL_VALUE=1,IF_SYNCHRONOUS_MODE="FALSE",IODELAY_GRP="IODELAY_MIG",BANK_TYPE="HP_IO",BYTELANES_DDR_CK=72'b01000,RCLK_SELECT_LANE="B",USE_PRE_POST_FIFO="TRUE",SYNTHESIS="TRUE",TCK=1666,PC_CLK_RATIO=4,PI_BURST_MODE="TRUE",PI_CLKOUT_DIV=2,PI_FREQ_REF_DIV="NONE",PI_FINE_DELAY=32'sb010000,PI_OUTPUT_CLK_SRC="DELAYED_REF",PI_SYNC_IN_DIV_RST="TRUE",PI_SEL_CLK_OFFSET=6,PO_CLKOUT_DIV=4,PO_FINE_DELAY=60,PO_COARSE_BYPASS="FALSE",PO_COARSE_DELAY=0,PO_OCLK_DELAY=30,PO_OCLKDELAY_INV="TRUE",PO_OUTPUT_CLK_SRC="DELAYED_REF",PO_SYNC_IN_DIV_RST="TRUE",OSERDES_DATA_RATE="UNDECLARED",OSERDES_DATA_WIDTH="UNDECLARED",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,CKE_ODT_AUX="FALSE")>.

Elaborating module <mig_7series_v1_8_ddr_byte_group_io(PO_DATA_CTL="FALSE",BITLANES=12'b01111111111,BITLANES_OUTONLY=12'b0,OSERDES_DATA_RATE="SDR",OSERDES_DATA_WIDTH=4,IODELAY_GRP="IODELAY_MIG",IDELAYE2_IDELAY_TYPE="VARIABLE",IDELAYE2_IDELAY_VALUE=0,SYNTHESIS="TRUE")>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 136: Net <oserdes_dq_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 137: Net <oserdes_dqts_buf[11]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 138: Net <oserdes_dqs_buf> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v" Line 139: Net <oserdes_dqsts_buf> does not have a driver.

Elaborating module <OBUFDS>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 269: Net <iserdes_clk> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" Line 270: Net <iserdes_clkdiv> does not have a driver.

Elaborating module <PHY_CONTROL(AO_WRLVL_EN=0,AO_TOGGLE=4'b01,BURST_MODE="TRUE",CO_DURATION=1,CLK_RATIO=4,DATA_CTL_A_N="FALSE",DATA_CTL_B_N="FALSE",DATA_CTL_C_N="FALSE",DATA_CTL_D_N="FALSE",DI_DURATION=1,DO_DURATION=1,EVENTS_DELAY=18,FOUR_WINDOW_CLOCKS=63,MULTI_REGION="TRUE",PHY_COUNT_ENABLE="FALSE",DISABLE_SEQ_MATCH="TRUE",SYNC_MODE="FALSE",CMD_OFFSET=8,RD_CMD_OFFSET_0=10,RD_CMD_OFFSET_1=10,RD_CMD_OFFSET_2=10,RD_CMD_OFFSET_3=10,RD_DURATION_0=6,RD_DURATION_1=6,RD_DURATION_2=6,RD_DURATION_3=6,WR_CMD_OFFSET_0=8,WR_CMD_OFFSET_1=8,WR_CMD_OFFSET_2=8,WR_CMD_OFFSET_3=8,WR_DURATION_0=7,WR_DURATION_1=7,WR_DURATION_2=7,WR_DURATION_3=7)>.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" Line 415: Net <A_pi_dqs_out_of_range> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" Line 427: Net <pi_fine_overflow_w[2]> does not have a driver.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 1438: Size mismatch in connection of port <phyGo>. Formal port size is 1-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 1480: Size mismatch in connection of port <calib_zero_lanes>. Formal port size is 8-bit while actual signal size is 32-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 1505: Size mismatch in connection of port <pi_dqs_found_lanes>. Formal port size is 8-bit while actual signal size is 12-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 1513: Size mismatch in connection of port <pi_phase_locked_lanes>. Formal port size is 8-bit while actual signal size is 12-bit.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 525: Net <mem_dqs_in[7]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 528: Net <mem_dq_in[79]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 546: Net <phy_dout[639]> does not have a driver.
WARNING:HDLCompiler:552 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" Line 1414: Input port auxout_clk is not connected on this instance
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" Line 974: Assignment to phy_data_full ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" Line 1005: Assignment to pi_dqs_out_of_range ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ddr_calib_top(TCQ=100,nCK_PER_CLK=4,PRE_REV3ES="OFF",tCK=1666,CLK_PERIOD=6664,N_CTL_LANES=32'b011,CTL_BYTE_LANE=8'b0111001,CTL_BANK=3'b01,DRAM_TYPE="DDR3",PRBS_WIDTH=8,DQS_BYTE_MAP=144'b010000001000000011,HIGHEST_BANK=2,BANK_TYPE="HP_IO",HIGHEST_LANE=8,BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,DATA_CTL_B0=4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0,SLOT_1_CONFIG=8'b0,BANK_WIDTH=3,CA_MIRROR="OFF",COL_WIDTH=10,CKE_ODT_AUX="FALSE",nCS_PER_RANK=1,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_WIDTH=8,ROW_WIDTH=15,RANKS=1,CS_WIDTH=1,CKE_WIDTH=1,DDR2_DQSN_ENABLE="YES",PER_BIT_DESKEW="OFF",CALIB_ROW_ADD=16'b0,CALIB_COL_ADD=12'b0,CALIB_BA_ADD=3'b0,AL="0",BURST_MODE="8",BURST_TYPE="SEQ",nCL=9,nCWL=7,tRFC=300000,OUTPUT_DRV="HIGH",REG_CTRL="OFF",ADDR_CMD_MODE="1T",RTT_NOM="60",RTT_WR="OFF",WRLVL="ON",USE_ODT_PORT=1,SIM_INIT_OPTION="NONE",SIM_CAL_OPTION="NONE",DEBUG_PORT="ON")>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" Line 718: Assignment to tempmon_sel_pi_incdec_r ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ddr_prbs_gen(TCQ=100,PRBS_WIDTH=64)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v" Line 144: Result of 8-bit expression is truncated to fit in 7-bit target.

Elaborating module <mig_7series_v1_8_ddr_phy_init(TCQ=100,nCK_PER_CLK=4,CLK_PERIOD=6664,DRAM_TYPE="DDR3",PRBS_WIDTH=8,BANK_WIDTH=3,CA_MIRROR="OFF",COL_WIDTH=10,nCS_PER_RANK=1,DQ_WIDTH=32,DQS_WIDTH=4,DQS_CNT_WIDTH=2,ROW_WIDTH=15,CS_WIDTH=1,RANKS=1,CKE_WIDTH=1,CALIB_ROW_ADD=16'b0,CALIB_COL_ADD=12'b0,CALIB_BA_ADD=3'b0,AL="0",BURST_MODE="8",BURST_TYPE="SEQ",nCL=9,nCWL=7,tRFC=300000,OUTPUT_DRV="HIGH",REG_CTRL="OFF",ADDR_CMD_MODE="1T",RTT_NOM="60",RTT_WR="OFF",WRLVL="ON",USE_ODT_PORT=1,DDR2_DQSN_ENABLE="YES",nSLOTS=1,SIM_INIT_OPTION="NONE",SIM_CAL_OPTION="NONE",CKE_ODT_AUX="FALSE",PRE_REV3ES="OFF",TEST_AL="0")>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1089: Assignment to wrlvl_final_r ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1122: Result of 32-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1173: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1283: Result of 8-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1310: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1347: Result of 15-bit expression is truncated to fit in 14-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1393: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1402: Result of 10-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1455: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1470: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1486: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1507: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1558: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1571: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1607: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:1308 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 1651: Found full_case directive in module mig_7series_v1_8_ddr_phy_init. Use of full_case directives may cause differences between RTL and post-synthesis simulation
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2221: Assignment to read_calib_r ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2253: Result of 15-bit expression is truncated to fit in 14-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2652: Result of 32-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2663: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2674: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2685: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2708: Result of 32-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2729: Assignment to rdlvl_wr_r ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 2814: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 3315: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 4413: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 4423: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v" Line 4433: Result of 11-bit expression is truncated to fit in 10-bit target.

Elaborating module <mig_7series_v1_8_ddr_phy_wrcal(TCQ=100,nCK_PER_CLK=4,CLK_PERIOD=6664,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_WIDTH=8,SIM_CAL_OPTION="NONE",PRE_REV3ES="OFF",PO_TAP_DLY=1)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 400: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1151: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1154: Assignment to rden_wait_r ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1271: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1280: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1289: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1307: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1310: Assignment to cal2_state_r1 ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1489: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1515: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1557: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1586: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1591: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1638: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1691: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1719: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1722: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1785: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1799: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1807: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v" Line 1819: Assignment to cal2_done_r3 ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ddr_phy_wrlvl(TCQ=100,DQS_CNT_WIDTH=2,DQ_WIDTH=32,DQS_WIDTH=4,DRAM_WIDTH=8,RANKS=1,CLK_PERIOD=6664,nCK_PER_CLK=4,SIM_CAL_OPTION="NONE")>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 335: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 345: Result of 32-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 571: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 577: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 688: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 757: Assignment to oclk_count_w ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 765: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 905: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 938: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 959: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 968: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 1003: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 1032: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 1034: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 1036: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 1038: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 1070: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v" Line 777: Assignment to final_corse_dec ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay(TCQ=100,tCK=1666,DQS_CNT_WIDTH=2,N_CTL_LANES=32'b011,SIM_CAL_OPTION="NONE")>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v" Line 133: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v" Line 191: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v" Line 200: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v" Line 211: Result of 4-bit expression is truncated to fit in 3-bit target.

Elaborating module <mig_7series_v1_8_ddr_phy_oclkdelay_cal(TCQ=100,tCK=1666,nCK_PER_CLK=4,DRAM_TYPE="DDR3",DRAM_WIDTH=8,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DQ_WIDTH=32,SIM_CAL_OPTION="NONE",OCAL_EN="ON")>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 318: Assignment to oclk_init_delay_start_r ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 325: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 357: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 400: Assignment to ocal_wrlvl_done_r ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 586: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 616: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 675: Assignment to stg3_tap_cnt_eq_0 ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 802: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 809: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 861: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 865: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 868: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 906: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 954: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 962: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 964: Result of 32-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 977: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 979: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 982: Result of 32-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 1020: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 1025: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 1031: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 1059: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 1061: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v" Line 1114: Result of 4-bit expression is truncated to fit in 3-bit target.

Elaborating module <mig_7series_v1_8_ddr_phy_dqs_found_cal(TCQ=100,nCK_PER_CLK=4,nCL=9,AL="0",nCWL=7,RANKS=1,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_WIDTH=8,REG_CTRL="OFF",SIM_CAL_OPTION="NONE",DRAM_TYPE="DDR3",NUM_DQSFOUND_CAL=1020,N_CTL_LANES=32'b011,HIGHEST_LANE=8,HIGHEST_BANK=2,BYTE_LANES_B0=4'b1111,BYTE_LANES_B1=4'b1110,BYTE_LANES_B2=4'b0,BYTE_LANES_B3=4'b0,BYTE_LANES_B4=4'b0,DATA_CTL_B0=4'b1111,DATA_CTL_B1=4'b0,DATA_CTL_B2=4'b0,DATA_CTL_B3=4'b0,DATA_CTL_B4=4'b0)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 381: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 464: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 471: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 552: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 591: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 593: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 600: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 653: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 681: Assignment to dqsfound_retry_r1 ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 930: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 940: Result of 11-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 976: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 991: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 1122: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 1148: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v" Line 1165: Result of 32-bit expression is truncated to fit in 6-bit target.

Elaborating module <mig_7series_v1_8_ddr_phy_rdlvl(TCQ=100,nCK_PER_CLK=4,CLK_PERIOD=6664,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_WIDTH=8,RANKS=1,PER_BIT_DESKEW="OFF",SIM_CAL_OPTION="NONE",DEBUG_PORT="ON",DRAM_TYPE="DDR3",OCAL_EN="ON")>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 778: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 911: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 921: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 995: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 1017: Assignment to regl_dqs_cnt_timing ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 1051: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 1067: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 1198: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 1967: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 1978: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2351: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2375: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2452: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2582: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2584: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2637: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2639: Result of 32-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2816: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2851: Result of 8-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2867: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 2959: Result of 32-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 3067: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 3112: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 3143: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 3219: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v" Line 3228: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" Line 1772: Assignment to rdlvl_stg1_err ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ddr_phy_prbs_rdlvl(TCQ=100,nCK_PER_CLK=4,DQ_WIDTH=32,DQS_CNT_WIDTH=2,DQS_WIDTH=4,DRAM_WIDTH=8,RANKS=1,SIM_CAL_OPTION="NONE",PRBS_WIDTH=8)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 335: Assignment to rd_valid_r3 ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 360: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 380: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 399: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 534: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 536: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 560: Assignment to prbs_final_dqs_tap_cnt_r ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 597: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 708: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 716: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 738: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 768: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 795: Result of 32-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 838: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v" Line 846: Result of 4-bit expression is truncated to fit in 3-bit target.

Elaborating module <mig_7series_v1_8_ddr_phy_tempmon(TCQ=100)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v" Line 326: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v" Line 328: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" Line 1157: Assignment to calib_rank_cnt ignored, since the identifier is never used
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" Line 1175: Size mismatch in connection of port <pi_dqs_found_lanes>. Formal port size is 8-bit while actual signal size is 12-bit.
WARNING:HDLCompiler:552 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" Line 939: Input port po_counter_load_val[8] is not connected on this instance
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" Line 715: Assignment to init_wrcal_complete ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ui_top(TCQ=100,APP_DATA_WIDTH=256,APP_MASK_WIDTH=32'sb0100000,BANK_WIDTH=3,COL_WIDTH=10,CWL=7,DATA_BUF_ADDR_WIDTH=5,ECC="OFF",ECC_TEST="OFF",nCK_PER_CLK=4,ORDERING="NORM",RANKS=1,RANK_WIDTH=32'sb01,ROW_WIDTH=15,MEM_ADDR_ORDER="BANK_ROW_COLUMN")>.

Elaborating module <mig_7series_v1_8_ui_cmd(TCQ=100,ADDR_WIDTH=32'sb011101,BANK_WIDTH=3,COL_WIDTH=10,DATA_BUF_ADDR_WIDTH=5,RANK_WIDTH=32'sb01,ROW_WIDTH=15,RANKS=1,MEM_ADDR_ORDER="BANK_ROW_COLUMN")>.

Elaborating module <mig_7series_v1_8_ui_wr_data(TCQ=100,APP_DATA_WIDTH=256,APP_MASK_WIDTH=32'sb0100000,nCK_PER_CLK=4,ECC="OFF",ECC_TEST="OFF",CWL=8)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v" Line 235: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v" Line 264: Assignment to app_wdf_rdy_r_copy4 ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ui_rd_data(TCQ=100,APP_DATA_WIDTH=256,DATA_BUF_ADDR_WIDTH=5,nCK_PER_CLK=4,ECC="OFF",ORDERING="NORM")>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v" Line 184: Result of 7-bit expression is truncated to fit in 6-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v" Line 422: Result of 6-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v" Line 202: Net <app_ecc_multiple_err_r[7]> does not have a driver.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" Line 856: Size mismatch in connection of port <app_ecc_multiple_err>. Formal port size is 8-bit while actual signal size is 4-bit.

Elaborating module <mig_7series_v1_8_axi_mc(C_FAMILY="virtex7",C_S_AXI_ID_WIDTH=4,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_MC_DATA_WIDTH=256,C_MC_ADDR_WIDTH=29,C_MC_BURST_MODE="8",C_MC_nCK_PER_CLK=4,C_S_AXI_SUPPORTS_NARROW_BURST=1,C_RD_WR_ARB_ALGORITHM="ROUND_ROBIN",C_S_AXI_REG_EN0=20'b0,C_S_AXI_REG_EN1=20'b0,C_ECC="OFF")>.

Elaborating module <mig_7series_v1_8_ddr_axi_register_slice(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=0,C_REG_CONFIG_W=0,C_REG_CONFIG_B=0,C_REG_CONFIG_AR=0,C_REG_CONFIG_R=0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=66,C_REG_CONFIG=0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=32'sb010010101,C_REG_CONFIG=0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=6,C_REG_CONFIG=0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=135,C_REG_CONFIG=0)>.

Elaborating module <mig_7series_v1_8_ddr_axi_upsizer(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=256,C_M_AXI_AW_REGISTER=32'sb01,C_M_AXI_W_REGISTER=32'sb0,C_M_AXI_AR_REGISTER=32'sb01,C_S_AXI_R_REGISTER=32'sb0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_PACKING_LEVEL=2,C_SUPPORT_BURSTS=1,C_SINGLE_THREAD=0)>.

Elaborating module <mig_7series_v1_8_ddr_axi_register_slice(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_REG_CONFIG_AW=32'b0111,C_REG_CONFIG_AR=32'b0111)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=66,C_REG_CONFIG=32'b0111)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=32'sb010010101,C_REG_CONFIG=32'b0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=6,C_REG_CONFIG=32'b0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=135,C_REG_CONFIG=32'b0)>.

Elaborating module <mig_7series_v1_8_ddr_axi_register_slice(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=256,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_RUSER_WIDTH=1,C_REG_CONFIG_R=1)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=66,C_REG_CONFIG=32'b0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=32'sb0100100101,C_REG_CONFIG=32'b0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=263,C_REG_CONFIG=1)>.

Elaborating module <mig_7series_v1_8_ddr_a_upsizer(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=256,C_M_AXI_REGISTER=32'sb01,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AUSER_WIDTH=1,C_AXI_CHANNEL=0,C_PACKING_LEVEL=2,C_SUPPORT_BURSTS=1,C_SINGLE_THREAD=0,C_S_AXI_BYTES_LOG=32'sb0100,C_M_AXI_BYTES_LOG=32'sb0101)>.

Elaborating module <MUXCY>.

Elaborating module <XORCY>.

Elaborating module <mig_7series_v1_8_ddr_carry_latch_and(C_FAMILY="virtex7")>.

Elaborating module <AND2B1L>.

Elaborating module <mig_7series_v1_8_ddr_carry_and(C_FAMILY="virtex7")>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v" Line 722: Result of 9-bit expression is truncated to fit in 8-bit target.

Elaborating module <mig_7series_v1_8_ddr_command_fifo(C_FAMILY="virtex7",C_ENABLE_S_VALID_CARRY=1,C_ENABLE_REGISTERED_OUTPUT=1,C_FIFO_DEPTH_LOG=5,C_FIFO_WIDTH=32'sb0101010)>.

Elaborating module <mig_7series_v1_8_ddr_carry_latch_or(C_FAMILY="virtex7")>.

Elaborating module <OR2L>.

Elaborating module <FDRE(INIT=1'b0)>.

Elaborating module <mig_7series_v1_8_ddr_w_upsizer(C_FAMILY="virtex7",C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=256,C_M_AXI_REGISTER=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_WUSER_WIDTH=1,C_PACKING_LEVEL=2,C_SUPPORT_BURSTS=1,C_S_AXI_BYTES_LOG=32'sb0100,C_M_AXI_BYTES_LOG=32'sb0101,C_RATIO=32'sb010,C_RATIO_LOG=32'sb01)>.

Elaborating module <mig_7series_v1_8_ddr_comparator_sel_static(C_FAMILY="virtex7",C_VALUE=5'b0,C_DATA_WIDTH=32'sb0101)>.

Elaborating module <mig_7series_v1_8_ddr_carry_or(C_FAMILY="virtex7")>.

Elaborating module <LUT6_2(INIT=64'b0101101001011010010110100110011011110000111100001111000011001100)>.

Elaborating module <LUT6_2(INIT=64'b011001100111100010101010101101011111111111100001111111111110000)>.

Elaborating module <LUT4(INIT=16'b1100110011001010)>.

Elaborating module <LUT6(INIT=64'b1010101010101100101010101010110010101010101011001010101010101100)>.

Elaborating module <FDSE(INIT=1'b1)>.

Elaborating module <mig_7series_v1_8_ddr_comparator_sel_static(C_FAMILY="virtex7",C_VALUE=8'b0,C_DATA_WIDTH=8)>.

Elaborating module <mig_7series_v1_8_ddr_comparator_sel(C_FAMILY="virtex7",C_DATA_WIDTH=32'sb0101)>.

Elaborating module <LUT6(INIT=64'b1111000011110000111100001111000011001100110011000000000010101010)>.

Elaborating module <mig_7series_v1_8_ddr_a_upsizer(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=256,C_M_AXI_REGISTER=32'sb01,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AUSER_WIDTH=1,C_AXI_CHANNEL=1,C_PACKING_LEVEL=2,C_SUPPORT_BURSTS=1,C_SINGLE_THREAD=0,C_S_AXI_BYTES_LOG=32'sb0100,C_M_AXI_BYTES_LOG=32'sb0101)>.

Elaborating module <mig_7series_v1_8_ddr_r_upsizer(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_S_AXI_DATA_WIDTH=128,C_M_AXI_DATA_WIDTH=256,C_S_AXI_REGISTER=32'sb0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_RUSER_WIDTH=1,C_PACKING_LEVEL=2,C_SUPPORT_BURSTS=1,C_S_AXI_BYTES_LOG=32'sb0100,C_M_AXI_BYTES_LOG=32'sb0101,C_RATIO=32'sb010,C_RATIO_LOG=32'sb01)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v" Line 874: Assignment to M_AXI_RLAST_I ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_ddr_axi_register_slice(C_FAMILY="virtex7",C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=256,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=32'sb0,C_REG_CONFIG_W=32'sb0,C_REG_CONFIG_B=32'sb0,C_REG_CONFIG_AR=0,C_REG_CONFIG_R=32'sb0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=66,C_REG_CONFIG=32'sb0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=32'sb0100100101,C_REG_CONFIG=32'sb0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=6,C_REG_CONFIG=32'sb0)>.

Elaborating module <mig_7series_v1_8_ddr_axic_register_slice(C_FAMILY="virtex7",C_DATA_WIDTH=263,C_REG_CONFIG=32'sb0)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" Line 805: Assignment to wlast_d3 ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_axi_mc_aw_channel(C_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_MC_ADDR_WIDTH=29,C_DATA_WIDTH=256,C_AXSIZE=32'sb0101,C_MC_nCK_PER_CLK=4,C_MC_BURST_LEN=1,C_ECC="OFF")>.

Elaborating module <mig_7series_v1_8_axi_mc_cmd_translator(C_AXI_ADDR_WIDTH=32,C_MC_ADDR_WIDTH=29,C_DATA_WIDTH=256,C_MC_BURST_LEN=1,C_MC_nCK_PER_CLK=4,C_AXSIZE=32'sb0101)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v" Line 149: Result of 32-bit expression is truncated to fit in 29-bit target.

Elaborating module <mig_7series_v1_8_axi_mc_incr_cmd(C_AXI_ADDR_WIDTH=32,C_MC_ADDR_WIDTH=29,C_DATA_WIDTH=256,C_MC_BURST_LEN=1,C_AXSIZE=32'sb0101)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v" Line 186: Result of 32-bit expression is truncated to fit in 9-bit target.

Elaborating module <mig_7series_v1_8_axi_mc_wrap_cmd(C_AXI_ADDR_WIDTH=32,C_MC_ADDR_WIDTH=29,C_MC_BURST_LEN=1,C_DATA_WIDTH=256,C_AXSIZE=32'sb0101)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v" Line 212: Result of 32-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v" Line 246: Result of 33-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v" Line 247: Result of 34-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v" Line 285: Result of 32-bit expression is truncated to fit in 5-bit target.

Elaborating module <mig_7series_v1_8_axi_mc_wr_cmd_fsm(C_MC_BURST_LEN=1,C_MC_RD_INST=0)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" Line 890: Assignment to b_awlen ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_axi_mc_w_channel(C_DATA_WIDTH=256,C_AXI_ADDR_WIDTH=32,C_MC_BURST_LEN=1)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v" Line 183: Result of 32-bit expression is truncated to fit in 5-bit target.

Elaborating module <mig_7series_v1_8_axi_mc_simple_fifo(C_WIDTH=32'sb0100100000,C_AWIDTH=3,C_DEPTH=8)>.

Elaborating module <mig_7series_v1_8_axi_mc_b_channel(C_ID_WIDTH=4)>.

Elaborating module <mig_7series_v1_8_axi_mc_simple_fifo(C_WIDTH=4,C_AWIDTH=2,C_DEPTH=4)>.

Elaborating module <mig_7series_v1_8_axi_mc_ar_channel(C_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_MC_ADDR_WIDTH=29,C_DATA_WIDTH=256,C_AXSIZE=32'sb0101,C_MC_nCK_PER_CLK=4,C_MC_BURST_LEN=1)>.

Elaborating module <mig_7series_v1_8_axi_mc_cmd_fsm(C_MC_BURST_LEN=1,C_MC_RD_INST=1)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v" Line 195: Assignment to b_push ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v" Line 198: Assignment to w_push ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_axi_mc_r_channel(C_ID_WIDTH=4,C_DATA_WIDTH=256,C_AXI_ADDR_WIDTH=32,C_MC_BURST_MODE="8",C_MC_BURST_LEN=1)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" Line 236: Assignment to mc_app_rd_data_r ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_axi_mc_simple_fifo(C_WIDTH=257,C_AWIDTH=5,C_DEPTH=32)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" Line 271: Assignment to rd_full ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_axi_mc_simple_fifo(C_WIDTH=7,C_AWIDTH=5,C_DEPTH=32)>.

Elaborating module <mig_7series_v1_8_axi_mc_cmd_arbiter(C_MC_ADDR_WIDTH=29,C_MC_BURST_LEN=1,C_RD_WR_ARB_ALGORITHM="ROUND_ROBIN")>.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" Line 955: Size mismatch in connection of port <mc_app_ecc_multiple_err>. Formal port size is 8-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" Line 510: Net <error> does not have a driver.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1053: Assignment to ddr3_parity ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1055: Assignment to bank_mach_next ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1079: Assignment to dbg_calib_top ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1085: Assignment to dbg_final_po_fine_tap_cnt ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1086: Assignment to dbg_final_po_coarse_tap_cnt ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1087: Assignment to dbg_rd_data_edge_detect ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1093: Assignment to dbg_wrlvl_fine_tap_cnt ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1094: Assignment to dbg_wrlvl_coarse_tap_cnt ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1095: Assignment to dbg_tap_cnt_during_wrlvl ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1096: Assignment to dbg_wl_edge_detect_valid ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1122: Assignment to dbg_oclkdelay_rd_data ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1178: Assignment to s_axi_ctrl_awready ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1182: Assignment to s_axi_ctrl_wready ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1185: Assignment to s_axi_ctrl_bvalid ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1187: Assignment to s_axi_ctrl_bresp ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1190: Assignment to s_axi_ctrl_arready ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1193: Assignment to s_axi_ctrl_rvalid ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1195: Assignment to s_axi_ctrl_rdata ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1196: Assignment to s_axi_ctrl_rresp ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1198: Assignment to interrupt ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1235: Assignment to dbg_bit ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 1389: Result of 256-bit expression is truncated to fit in 255-bit target.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 670: Net <s_axi_ctrl_awvalid> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 672: Net <s_axi_ctrl_awaddr[31]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 674: Net <s_axi_ctrl_wvalid> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 676: Net <s_axi_ctrl_wdata[31]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 679: Net <s_axi_ctrl_bready> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 682: Net <s_axi_ctrl_arvalid> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 684: Net <s_axi_ctrl_araddr[31]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 687: Net <s_axi_ctrl_rready> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" Line 700: Net <device_temp_i[11]> does not have a driver.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 978: Assignment to app_sr_active ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 980: Assignment to app_ref_ack ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 982: Assignment to app_zq_ack ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_axi4_tg(C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_AXI_NBURST_SUPPORT=0,C_EN_WRAP_TRANS=0,C_BEGIN_ADDRESS=32'b0,C_END_ADDRESS=32'b0111111111111111111111111,PRBS_EADDR_MASK_POS=32'b11111111000000000000000000000000,DBG_WR_STS_WIDTH=32,DBG_RD_STS_WIDTH=32,ENFORCE_RD_WR=0,ENFORCE_RD_WR_CMD=8'b010001,EN_UPSIZER=1,ENFORCE_RD_WR_PATTERN=3'b0)>.

Elaborating module <mig_7series_v1_8_axi4_wrapper(C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_AXI_NBURST_SUPPORT=0,C_BEGIN_ADDRESS=32'b0,C_END_ADDRESS=32'b0111111111111111111111111,CTL_SIG_WIDTH=3,WR_STS_WIDTH=16,RD_STS_WIDTH=16,EN_UPSIZER=1,WDG_TIMER_WIDTH=11)>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v" Line 319: Result of 12-bit expression is truncated to fit in 11-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v" Line 477: Result of 4-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v" Line 477: Assignment to awid ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v" Line 631: Result of 12-bit expression is truncated to fit in 11-bit target.

Elaborating module <mig_7series_v1_8_tg(C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=128,C_AXI_NBURST_SUPPORT=0,C_BEGIN_ADDRESS=32'b0,C_END_ADDRESS=32'b0111111111111111111111111,C_EN_WRAP_TRANS=0,CTL_SIG_WIDTH=3,WR_STS_WIDTH=16,RD_STS_WIDTH=16,DBG_WR_STS_WIDTH=32,DBG_RD_STS_WIDTH=32,ENFORCE_RD_WR=0,ENFORCE_RD_WR_CMD=8'b010001,PRBS_EADDR_MASK_POS=32'b11111111000000000000000000000000,PRBS_SADDR_MASK_POS=32'b010000000000000,ENFORCE_RD_WR_PATTERN=3'b0)>.

Elaborating module <mig_7series_v1_8_data_gen_chk(C_AXI_DATA_WIDTH=128)>.

Elaborating module <mig_7series_v1_8_cmd_prbs_gen_axi(PRBS_CMD="BLEN",PRBS_WIDTH=32,SEED_WIDTH=32,ADDR_WIDTH=32)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v" Line 98: Assignment to ZEROS ignored, since the identifier is never used

Elaborating module <mig_7series_v1_8_cmd_prbs_gen_axi(FAMILY="VIRTEX7",ADDR_WIDTH=32,PRBS_CMD="ADDRESS",PRBS_WIDTH=32,SEED_WIDTH=32,PRBS_EADDR_MASK_POS=32'b11111111000000000000000000000000,PRBS_SADDR_MASK_POS=32'b010000000000000,PRBS_EADDR=32'b0111111111111111111111111,PRBS_SADDR=32'b0)>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v" Line 98: Assignment to ZEROS ignored, since the identifier is never used
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1101: Size mismatch in connection of port <axi_wlock>. Formal port size is 2-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1108: Size mismatch in connection of port <axi_wd_wid>. Formal port size is 4-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1108: Assignment to s_axi_wid ignored, since the identifier is never used
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1127: Size mismatch in connection of port <axi_rlock>. Formal port size is 2-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1145: Assignment to test_cmptd ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1146: Assignment to write_cmptd ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1147: Assignment to read_cmptd ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1148: Assignment to cmptd_one_wr_rd ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1151: Assignment to dbg_wr_sts_vld ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1152: Assignment to dbg_wr_sts ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1153: Assignment to dbg_rd_sts_vld ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1154: Assignment to dbg_rd_sts ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1166: Result of 4-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1167: Result of 3-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1168: Result of 4-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1169: Result of 2-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1170: Result of 8-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1173: Result of 3-bit expression is truncated to fit in 1-bit target.

Elaborating module <ddr_icon>.

Elaborating module <ddr_ila_basic>.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1191: Size mismatch in connection of port <TRIG0>. Formal port size is 32-bit while actual signal size is 24-bit.

Elaborating module <ddr_ila_wrpath>.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1199: Size mismatch in connection of port <TRIG0>. Formal port size is 32-bit while actual signal size is 24-bit.

Elaborating module <ddr_ila_rdpath>.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1207: Size mismatch in connection of port <TRIG0>. Formal port size is 64-bit while actual signal size is 24-bit.

Elaborating module <ddr_vio_sync_async_out72>.

Elaborating module <ddr_vio_async_in_sync_out>.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1267: Result of 64-bit expression is truncated to fit in 32-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1293: Result of 8-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1298: Result of 32-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1306: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1308: Result of 4-bit expression is truncated to fit in 3-bit target.

Elaborating module <mig_7series_v1_8_chk_win(TCQ=100,nCK_PER_CLK=4,DLY_WIDTH=26,DQ_PER_DQS=8,DQ_WIDTH=32,SC_WIDTH=3,SDC_WIDTH=5,WIN_SIZE=6,SIM_OPTION="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 230: Assignment to po_curr_tap_cnt_r2 ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 354: Result of 5-bit expression is truncated to fit in 4-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 369: Result of 10-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 371: Result of 32-bit expression is truncated to fit in 9-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 373: Result of 9-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 373: Assignment to win_offset_cntr ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 393: Result of 27-bit expression is truncated to fit in 26-bit target.

Elaborating module <RAM128X1D(INIT=64'b0)>.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 452: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 467: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 452: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 467: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 452: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 467: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 452: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 467: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 452: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 467: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 452: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 467: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 488: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 503: Size mismatch in connection of port <A>. Formal port size is 7-bit while actual signal size is 4-bit.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 577: Result of 4-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 599: Result of 32-bit expression is truncated to fit in 5-bit target.
WARNING:HDLCompiler:1127 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v" Line 718: Assignment to po_stg23_sel_d ignored, since the identifier is never used
WARNING:HDLCompiler:189 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1332: Size mismatch in connection of port <cmp_data>. Formal port size is 256-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 646: Net <app_rd_data_valid> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 647: Net <app_rd_data[255]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 648: Net <mem_pattern_init_done> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 716: Net <ddr3_ila_basic_w[127]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 726: Net <ddr3_vio_async_in_twm[127]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1332: Net <CHIPSCOPE_INST.cmp_data> does not have a driver.
WARNING:HDLCompiler:552 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" Line 1324: Input port win_bit_select[6] is not connected on this instance

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <example_top>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v".
        BL_WIDTH = 10
        PORT_MODE = "BI_MODE"
        DATA_MODE = 4'b0010
        ADDR_MODE = 4'b0011
        TST_MEM_INSTR_MODE = "R_W_INSTR_MODE"
        EYE_TEST = "FALSE"
        DATA_PATTERN = "DGEN_ALL"
        CMD_PATTERN = "CGEN_ALL"
        BEGIN_ADDRESS = 32'b00000000000000000000000000000000
        END_ADDRESS = 32'b00000000111111111111111111111111
        PRBS_EADDR_MASK_POS = 32'b11111111000000000000000000000000
        CMD_WDT = 32'b00000000000000000000001111111111
        WR_WDT = 32'b00000000000000000001111111111111
        RD_WDT = 32'b00000000000000000000001111111111
        SEL_VICTIM_LINE = 0
        ENFORCE_RD_WR = 0
        ENFORCE_RD_WR_CMD = 8'b00010001
        ENFORCE_RD_WR_PATTERN = 3'b000
        C_EN_WRAP_TRANS = 0
        C_AXI_NBURST_TEST = 0
        BANK_WIDTH = 3
        CK_WIDTH = 1
        COL_WIDTH = 10
        CS_WIDTH = 1
        nCS_PER_RANK = 1
        CKE_WIDTH = 1
        DATA_BUF_ADDR_WIDTH = 5
        DQ_CNT_WIDTH = 5
        DQ_PER_DM = 8
        DM_WIDTH = 4
        DQ_WIDTH = 32
        DQS_WIDTH = 4
        DQS_CNT_WIDTH = 2
        DRAM_WIDTH = 8
        ECC = "OFF"
        nBANK_MACHS = 4
        RANKS = 1
        ODT_WIDTH = 1
        ROW_WIDTH = 15
        ADDR_WIDTH = 29
        USE_CS_PORT = 1
        USE_DM_PORT = 1
        USE_ODT_PORT = 1
        PHY_CONTROL_MASTER_BANK = 1
        MEM_DENSITY = "4Gb"
        MEM_SPEEDGRADE = "125"
        MEM_DEVICE_WIDTH = 16
        AL = "0"
        nAL = 0
        BURST_MODE = "8"
        BURST_TYPE = "SEQ"
        CL = 9
        CWL = 7
        OUTPUT_DRV = "HIGH"
        RTT_NOM = "60"
        RTT_WR = "OFF"
        ADDR_CMD_MODE = "1T"
        REG_CTRL = "OFF"
        CA_MIRROR = "OFF"
        CLKIN_PERIOD = 9996
        CLKFBOUT_MULT = 12
        DIVCLK_DIVIDE = 1
        CLKOUT0_PHASE = 337.500000
        CLKOUT0_DIVIDE = 2
        CLKOUT1_DIVIDE = 2
        CLKOUT2_DIVIDE = 32
        CLKOUT3_DIVIDE = 8
        tCKE = 5000
        tFAW = 30000
        tRAS = 35000
        tRCD = 13750
        tREFI = 7800000
        tRFC = 300000
        tRP = 13750
        tRRD = 6000
        tRTP = 7500
        tWTR = 7500
        tZQI = 128000000
        tZQCS = 64
        SIM_BYPASS_INIT_CAL = "OFF"
        SIMULATION = "FALSE"
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        PHY_0_BITLANES = 48'b001111111110001111111110001111111110001011111111
        PHY_1_BITLANES = 48'b001111111111111111111111110000000000000000000000
        PHY_2_BITLANES = 48'b000000000000000000000000000000000000000000000000
        CK_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
        ADDR_MAP = 192'b000000000000000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011
        BANK_MAP = 36'b000100101010000100100101000100100100
        CAS_MAP = 12'b000100100010
        CKE_ODT_BYTE_MAP = 8'b00000000
        CKE_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
        ODT_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
        CS_MAP = 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000
        PARITY_MAP = 12'b000000000000
        RAS_MAP = 12'b000100100011
        WE_MAP = 12'b000100100001
        DQS_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
        DATA0_MAP = 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
        DATA1_MAP = 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
        DATA2_MAP = 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
        DATA3_MAP = 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
        DATA4_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA5_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA6_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA7_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA8_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA9_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA10_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA11_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA12_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA13_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA14_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA15_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA16_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA17_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        MASK0_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
        MASK1_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        SLOT_0_CONFIG = 8'b00000001
        SLOT_1_CONFIG = 8'b00000000
        MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
        IODELAY_HP_MODE = "ON"
        IBUF_LPWR_MODE = "OFF"
        DATA_IO_IDLE_PWRDWN = "ON"
        BANK_TYPE = "HP_IO"
        DATA_IO_PRIM_TYPE = "HP_LP"
        CKE_ODT_AUX = "FALSE"
        USER_REFRESH = "OFF"
        WRLVL = "ON"
        ORDERING = "NORM"
        CALIB_ROW_ADD = 16'b0000000000000000
        CALIB_COL_ADD = 12'b000000000000
        CALIB_BA_ADD = 3'b000
        TCQ = 100
        IODELAY_GRP = "IODELAY_MIG"
        SYSCLK_TYPE = "SINGLE_ENDED"
        REFCLK_TYPE = "NO_BUFFER"
        DRAM_TYPE = "DDR3"
        CAL_WIDTH = "HALF"
        STARVE_LIMIT = 2
        REFCLK_FREQ = 200.000000
        DIFF_TERM_REFCLK = "TRUE"
        tCK = 1666
        nCK_PER_CLK = 4
        DIFF_TERM_SYSCLK = "TRUE"
        C_S_AXI_ID_WIDTH = 4
        C_S_AXI_MEM_SIZE = "2147483648"
        C_S_AXI_ADDR_WIDTH = 32
        C_S_AXI_DATA_WIDTH = 128
        C_MC_nCK_PER_CLK = 4
        C_S_AXI_SUPPORTS_NARROW_BURST = 1
        C_RD_WR_ARB_ALGORITHM = "ROUND_ROBIN"
        C_S_AXI_REG_EN0 = 20'b00000000000000000000
        C_S_AXI_REG_EN1 = 20'b00000000000000000000
        C_S_AXI_CTRL_ADDR_WIDTH = 32
        C_S_AXI_CTRL_DATA_WIDTH = 32
        C_S_AXI_BASEADDR = 32'b00000000000000000000000000000000
        C_ECC_ONOFF_RESET_VALUE = 1
        C_ECC_CE_COUNTER_WIDTH = 8
        DEBUG_PORT = "ON"
        TEMP_MON_CONTROL = "INTERNAL"
        RST_ACT_LOW = 1
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<127:104>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<103>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<102:94>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<93:85>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<84:76>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<75:69>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<68:65>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<64:58>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<57:26>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<25>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<24:19>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<18:13>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<12:7>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<6:1>>.
    Set property "KEEP = TRUE" for signal <ddr3_vio_async_in_twm<0>>.
WARNING:Xst:2898 - Port 'win_bit_select', unconnected in block instance 'CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win', is tied to GND.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 950: Output port <app_sr_active> of the instance <u_ddr3_interface_fast> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 950: Output port <app_ref_ack> of the instance <u_ddr3_interface_fast> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 950: Output port <app_zq_ack> of the instance <u_ddr3_interface_fast> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <axi_wd_wid> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <dbg_wr_sts> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <dbg_rd_sts> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <test_cmptd> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <write_cmptd> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <read_cmptd> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <cmptd_one_wr_rd> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <dbg_wr_sts_vld> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1083: Output port <dbg_rd_sts_vld> of the instance <mig_7series_v1_8_axi4_tg_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1211: Output port <ASYNC_OUT> of the instance <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1324: Output port <win_clr_error> of the instance <CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/example_top.v" line 1324: Output port <po_win_tg_rst> of the instance <CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <app_rd_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ddr3_ila_basic_w<127:120>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ddr3_vio_async_in_twm<127:104>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <app_rd_data_valid> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_pattern_init_done> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <CHIPSCOPE_INST.cmp_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 129-bit register for signal <ddr3_ila_basic>.
    Found 46-bit register for signal <ddr3_vio_sync_out>.
    Found 256-bit register for signal <ddr3_ila_wrpath>.
    Found 1024-bit register for signal <ddr3_ila_rdpath>.
    Found 1-bit register for signal <app_rd_data_valid_r1>.
    Found 1-bit register for signal <app_rd_data_valid_r2>.
    Found 7-bit register for signal <win_byte_select>.
    Found 3-bit register for signal <dbg_byte_sel_r>.
    Found 1-bit register for signal <aresetn>.
    Found 7-bit adder for signal <win_byte_select[6]_GND_1_o_add_26_OUT> created at line 1293.
    Found 7-bit subtractor for signal <GND_1_o_GND_1_o_sub_30_OUT<6:0>> created at line 1298.
    WARNING:Xst:2404 -  FFs/Latches <app_rd_data_r1<255:0>> (without init value) have a constant value of 0 in block <example_top>.
    WARNING:Xst:2404 -  FFs/Latches <app_rd_data_r2<255:0>> (without init value) have a constant value of 0 in block <example_top>.
    WARNING:Xst:2404 -  FFs/Latches <ddr3_ila_basic<255:129>> (without init value) have a constant value of 0 in block <example_top>.
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal ddr3_vio_async_in_twm<103> may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal ddr3_vio_async_in_twm<127:104> may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal ddr3_vio_async_in_twm<93:85> may hinder XST clustering optimizations.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 1468 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <example_top> synthesized.

Synthesizing Unit <ddr3_interface_fast>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v".
        BANK_WIDTH = 3
        CK_WIDTH = 1
        COL_WIDTH = 10
        CS_WIDTH = 1
        nCS_PER_RANK = 1
        CKE_WIDTH = 1
        DATA_BUF_ADDR_WIDTH = 5
        DQ_CNT_WIDTH = 5
        DQ_PER_DM = 8
        DM_WIDTH = 4
        DQ_WIDTH = 32
        DQS_WIDTH = 4
        DQS_CNT_WIDTH = 2
        DRAM_WIDTH = 8
        ECC = "OFF"
        DATA_WIDTH = 32
        ECC_TEST = "OFF"
        PAYLOAD_WIDTH = 32
        ECC_WIDTH = 0
        MC_ERR_ADDR_WIDTH = 29
        nBANK_MACHS = 4
        RANKS = 1
        ODT_WIDTH = 1
        ROW_WIDTH = 15
        ADDR_WIDTH = 29
        USE_CS_PORT = 1
        USE_DM_PORT = 1
        USE_ODT_PORT = 1
        PHY_CONTROL_MASTER_BANK = 1
        MEM_DENSITY = "4Gb"
        MEM_SPEEDGRADE = "125"
        MEM_DEVICE_WIDTH = 16
        AL = "0"
        nAL = 0
        BURST_MODE = "8"
        BURST_TYPE = "SEQ"
        CL = 9
        CWL = 7
        OUTPUT_DRV = "HIGH"
        RTT_NOM = "60"
        RTT_WR = "OFF"
        ADDR_CMD_MODE = "1T"
        REG_CTRL = "OFF"
        CA_MIRROR = "OFF"
        CLKIN_PERIOD = 9996
        CLKFBOUT_MULT = 12
        DIVCLK_DIVIDE = 1
        CLKOUT0_PHASE = 337.500000
        CLKOUT0_DIVIDE = 2
        CLKOUT1_DIVIDE = 2
        CLKOUT2_DIVIDE = 32
        CLKOUT3_DIVIDE = 8
        CLKOUT5_DIVIDE = 5
        tCKE = 5000
        tFAW = 30000
        tPRDI = 1000000
        tRAS = 35000
        tRCD = 13750
        tREFI = 7800000
        tRFC = 300000
        tRP = 13750
        tRRD = 6000
        tRTP = 7500
        tWTR = 7500
        tZQI = 128000000
        tZQCS = 64
        SIM_BYPASS_INIT_CAL = "OFF"
        SIMULATION = "FALSE"
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        PHY_0_BITLANES = 48'b001111111110001111111110001111111110001011111111
        PHY_1_BITLANES = 48'b001111111111111111111111110000000000000000000000
        PHY_2_BITLANES = 48'b000000000000000000000000000000000000000000000000
        CK_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
        ADDR_MAP = 192'b000000000000000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011
        BANK_MAP = 36'b000100101010000100100101000100100100
        CAS_MAP = 12'b000100100010
        CKE_ODT_BYTE_MAP = 8'b00000000
        CKE_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
        ODT_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
        CS_MAP = 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000
        PARITY_MAP = 12'b000000000000
        RAS_MAP = 12'b000100100011
        WE_MAP = 12'b000100100001
        DQS_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
        DATA0_MAP = 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
        DATA1_MAP = 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
        DATA2_MAP = 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
        DATA3_MAP = 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
        DATA4_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA5_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA6_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA7_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA8_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA9_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA10_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA11_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA12_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA13_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA14_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA15_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA16_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA17_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        MASK0_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
        MASK1_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        SLOT_0_CONFIG = 8'b00000001
        SLOT_1_CONFIG = 8'b00000000
        MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
        IODELAY_HP_MODE = "ON"
        IBUF_LPWR_MODE = "OFF"
        DATA_IO_IDLE_PWRDWN = "ON"
        BANK_TYPE = "HP_IO"
        DATA_IO_PRIM_TYPE = "HP_LP"
        CKE_ODT_AUX = "FALSE"
        USER_REFRESH = "OFF"
        WRLVL = "ON"
        ORDERING = "NORM"
        CALIB_ROW_ADD = 16'b0000000000000000
        CALIB_COL_ADD = 12'b000000000000
        CALIB_BA_ADD = 3'b000
        TCQ = 100
        IODELAY_GRP = "IODELAY_MIG"
        SYSCLK_TYPE = "SINGLE_ENDED"
        REFCLK_TYPE = "NO_BUFFER"
        CMD_PIPE_PLUS1 = "ON"
        DRAM_TYPE = "DDR3"
        CAL_WIDTH = "HALF"
        STARVE_LIMIT = 2
        REFCLK_FREQ = 200.000000
        DIFF_TERM_REFCLK = "TRUE"
        tCK = 1666
        nCK_PER_CLK = 4
        DIFF_TERM_SYSCLK = "TRUE"
        C_S_AXI_ID_WIDTH = 4
        C_S_AXI_MEM_SIZE = "2147483648"
        C_S_AXI_ADDR_WIDTH = 32
        C_S_AXI_DATA_WIDTH = 128
        C_MC_nCK_PER_CLK = 4
        C_S_AXI_SUPPORTS_NARROW_BURST = 1
        C_RD_WR_ARB_ALGORITHM = "ROUND_ROBIN"
        C_S_AXI_REG_EN0 = 20'b00000000000000000000
        C_S_AXI_REG_EN1 = 20'b00000000000000000000
        C_S_AXI_CTRL_ADDR_WIDTH = 32
        C_S_AXI_CTRL_DATA_WIDTH = 32
        C_S_AXI_BASEADDR = 32'b00000000000000000000000000000000
        C_ECC_ONOFF_RESET_VALUE = 1
        C_ECC_CE_COUNTER_WIDTH = 8
        DEBUG_PORT = "ON"
        TEMP_MON_CONTROL = "INTERNAL"
        RST_ACT_LOW = 1
WARNING:Xst:647 - Input <ddr3_vio_sync_out<8:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ddr3_vio_sync_out<35:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 863: Output port <auxout_clk> of the instance <u_ddr3_infrastructure> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <bank_mach_next> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <app_ecc_multiple_err_o> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_rd_data_edge_detect> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_tap_cnt_during_wrlvl> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_final_po_fine_tap_cnt> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_final_po_coarse_tap_cnt> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_bresp> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_rdata> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_rresp> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_wrlvl_fine_tap_cnt> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_wrlvl_coarse_tap_cnt> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_calib_top> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_oclkdelay_rd_data> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <ddr_parity> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <dbg_wl_edge_detect_valid> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_awready> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_wready> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_bvalid> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_arready> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <s_axi_ctrl_rvalid> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ddr3_interface_fast.v" line 1026: Output port <interrupt> of the instance <u_mig_7series_v1_8_memc_ui_top_axi> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <ddr3_ila_wrpath<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ddr3_ila_rdpath<1023:875>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_awaddr> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_wdata> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_araddr> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <device_temp_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_awvalid> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_wvalid> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_bready> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_arvalid> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <s_axi_ctrl_rready> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 64-bit register for signal <dbg_rddata_r>.
    Found 1-bit register for signal <dbg_rddata_valid_r>.
    Found 8-bit adder for signal <n0253> created at line 1278.
    Found 8-bit adder for signal <n0256> created at line 1279.
    Found 8-bit adder for signal <n0259> created at line 1280.
    Found 8-bit adder for signal <GND_2_o_PWR_2_o_add_18_OUT> created at line 1282.
    Found 8-bit adder for signal <GND_2_o_PWR_2_o_add_20_OUT> created at line 1284.
    Found 8-bit adder for signal <GND_2_o_PWR_2_o_add_22_OUT> created at line 1286.
    Found 8-bit adder for signal <GND_2_o_PWR_2_o_add_24_OUT> created at line 1288.
    Found 504-bit shifter logical right for signal <n0230> created at line 1277
    Found 504-bit shifter logical right for signal <n0232> created at line 1278
    Found 504-bit shifter logical right for signal <n0234> created at line 1279
    Found 504-bit shifter logical right for signal <n0236> created at line 1280
    Found 504-bit shifter logical right for signal <n0238> created at line 1282
    Found 504-bit shifter logical right for signal <n0240> created at line 1284
    Found 504-bit shifter logical right for signal <n0242> created at line 1286
    Found 504-bit shifter logical right for signal <n0244> created at line 1288
    Found 102-bit shifter logical right for signal <n0168> created at line 1305
    Found 4x2-bit multiplier for signal <n0245> created at line 1306.
    Found 51-bit shifter logical right for signal <n0167> created at line 1306
    Found 4x3-bit multiplier for signal <n0246> created at line 1311.
    Found 102-bit shifter logical right for signal <n0165> created at line 1311
    Found 42-bit shifter logical right for signal <n0185> created at line 1372
    Found 42-bit shifter logical right for signal <n0184> created at line 1373
    Found 42-bit shifter logical right for signal <n0183> created at line 1374
    Found 4x3-bit multiplier for signal <n0247> created at line 1375.
    Found 35-bit shifter logical right for signal <n0182> created at line 1375
    Found 1-bit 9-to-1 multiplexer for signal <ddr3_ila_wrpath<11>> created at line 1304.
    Summary:
	inferred   3 Multiplier(s).
	inferred   7 Adder/Subtractor(s).
	inferred  65 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred  15 Combinational logic shifter(s).
Unit <ddr3_interface_fast> synthesized.

Synthesizing Unit <mig_7series_v1_8_iodelay_ctrl>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_iodelay_ctrl.v".
        TCQ = 100
        IODELAY_GRP = "IODELAY_MIG"
        REFCLK_TYPE = "NO_BUFFER"
        SYSCLK_TYPE = "SINGLE_ENDED"
        RST_ACT_LOW = 1
        DIFF_TERM_REFCLK = "TRUE"
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <u_idelayctrl>.
    Set property "syn_maxfan = 10" for signal <rst_ref_sync_r>.
    Set property "KEEP = TRUE" for signal <rst_ref_sync_r>.
    Set property "MAX_FANOUT = 10" for signal <rst_ref_sync_r>.
WARNING:Xst:647 - Input <clk_ref_p> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_ref_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 15-bit register for signal <rst_ref_sync_r>.
    Summary:
	inferred  15 D-type flip-flop(s).
Unit <mig_7series_v1_8_iodelay_ctrl> synthesized.

Synthesizing Unit <mig_7series_v1_8_clk_ibuf>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_clk_ibuf.v".
        SYSCLK_TYPE = "SINGLE_ENDED"
        DIFF_TERM_SYSCLK = "TRUE"
    Set property "KEEP = TRUE" for signal <sys_clk_ibufg>.
WARNING:Xst:647 - Input <sys_clk_p> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sys_clk_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_clk_ibuf> synthesized.

Synthesizing Unit <mig_7series_v1_8_tempmon>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v".
        TCQ = 100
        TEMP_MON_CONTROL = "INTERNAL"
        XADC_CLK_PERIOD = 5000
        tTEMPSAMPLE = 10000000
    Set property "ASYNC_REG = TRUE" for signal <device_temp_sync_r1>.
    Set property "ASYNC_REG = TRUE" for signal <device_temp_sync_r2>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_srlstyle". This constraint/property is not supported by the current software release and will be ignored.
    Set property "ASYNC_REG = TRUE" for signal <device_temp_sync_r3>.
    Set property "ASYNC_REG = TRUE" for signal <device_temp_sync_r4>.
    Set property "ASYNC_REG = TRUE" for signal <device_temp_sync_r5>.
    Set property "ASYNC_REG = TRUE" for signal <device_temp_r>.
    Set property "ASYNC_REG = TRUE" for signal <xadc_supplied_temperature.rst_r1>.
    Set property "ASYNC_REG = TRUE" for signal <xadc_supplied_temperature.rst_r2>.
WARNING:Xst:647 - Input <device_temp_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 12-bit register for signal <device_temp_sync_r2>.
    Found 12-bit register for signal <device_temp_sync_r3>.
    Found 12-bit register for signal <device_temp_sync_r4>.
    Found 12-bit register for signal <device_temp_sync_r5>.
    Found 1-bit register for signal <device_temp_sync_r4_neq_r3>.
    Found 4-bit register for signal <sync_cntr>.
    Found 12-bit register for signal <device_temp_r>.
    Found 1-bit register for signal <xadc_supplied_temperature.rst_r1>.
    Found 1-bit register for signal <xadc_supplied_temperature.rst_r2>.
    Found 11-bit register for signal <xadc_supplied_temperature.sample_timer>.
    Found 3-bit register for signal <xadc_supplied_temperature.tempmon_state>.
    Found 1-bit register for signal <xadc_supplied_temperature.sample_en>.
    Found 1-bit register for signal <xadc_supplied_temperature.sample_timer_clr>.
    Found 1-bit register for signal <xadc_supplied_temperature.sample_timer_en>.
    Found 1-bit register for signal <xadc_supplied_temperature.xadc_den>.
    Found 1-bit register for signal <xadc_supplied_temperature.xadc_drdy_r>.
    Found 12-bit register for signal <xadc_supplied_temperature.xadc_do_r<15:4>>.
    Found 12-bit register for signal <device_temp_lcl>.
    Found 12-bit register for signal <device_temp_sync_r1>.
    Found finite state machine <FSM_0> for signal <xadc_supplied_temperature.tempmon_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | xadc_clk (rising_edge)                         |
    | Reset              | xadc_supplied_temperature.rst_r2 (positive)       |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <sync_cntr[3]_GND_9_o_add_9_OUT> created at line 165.
    Found 11-bit adder for signal <xadc_supplied_temperature.sample_timer[10]_GND_9_o_add_20_OUT> created at line 228.
    Found 12-bit comparator not equal for signal <n0000> created at line 157
INFO:Xst:2774 - HDL ADVISOR - ASYNC_REG property attached to signal device_temp_sync_r1 may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - ASYNC_REG property attached to signal device_temp_sync_r2 may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - ASYNC_REG property attached to signal device_temp_sync_r3 may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - ASYNC_REG property attached to signal device_temp_sync_r4 may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal rst may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - ASYNC_REG property attached to signal xadc_supplied_temperature.rst_r1 may hinder XST clustering optimizations.
INFO:Xst:2774 - HDL ADVISOR - ASYNC_REG property attached to signal xadc_supplied_temperature.rst_r2 may hinder XST clustering optimizations.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 119 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_tempmon> synthesized.

Synthesizing Unit <mig_7series_v1_8_infrastructure>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/clocking/mig_7series_v1_8_infrastructure.v".
        SIMULATION = "FALSE"
        TCQ = 100
        CLKIN_PERIOD = 9996
        nCK_PER_CLK = 4
        SYSCLK_TYPE = "SINGLE_ENDED"
        CLKFBOUT_MULT = 12
        DIVCLK_DIVIDE = 1
        CLKOUT0_PHASE = 337.500000
        CLKOUT0_DIVIDE = 2
        CLKOUT1_DIVIDE = 2
        CLKOUT2_DIVIDE = 32
        CLKOUT3_DIVIDE = 8
        CLKOUT5_DIVIDE = 5
        RST_ACT_LOW = 1
    Set property "syn_maxfan = 10" for signal <rstdiv0_sync_r>.
    Set property "KEEP = TRUE" for signal <rstdiv0_sync_r>.
    Set property "MAX_FANOUT = 10" for signal <rstdiv0_sync_r>.
    Set property "syn_maxfan = 10" for signal <rst_phaser_ref_sync_r>.
    Set property "KEEP = TRUE" for signal <rst_phaser_ref_sync_r>.
    Set property "MAX_FANOUT = 10" for signal <rst_phaser_ref_sync_r>.
    Set property "KEEP = TRUE" for signal <pll_locked_i>.
    Set property "MAX_FANOUT = 10" for signal <pll_locked_i>.
    Set property "syn_maxfan = 10" for signal <pll_locked_i>.
    Found 13-bit register for signal <rst_phaser_ref_sync_r>.
    Found 13-bit register for signal <rstdiv0_sync_r>.
    Summary:
	inferred  26 D-type flip-flop(s).
Unit <mig_7series_v1_8_infrastructure> synthesized.

Synthesizing Unit <mig_7series_v1_8_memc_ui_top_axi>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v".
        TCQ = 100
        PAYLOAD_WIDTH = 32
        ADDR_CMD_MODE = "1T"
        AL = "0"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        BURST_TYPE = "SEQ"
        CA_MIRROR = "OFF"
        CK_WIDTH = 1
        CL = 9
        COL_WIDTH = 10
        CMD_PIPE_PLUS1 = "ON"
        CS_WIDTH = 1
        CKE_WIDTH = 1
        CWL = 7
        DATA_WIDTH = 32
        DATA_BUF_ADDR_WIDTH = 5
        DATA_BUF_OFFSET_WIDTH = 1
        DDR2_DQSN_ENABLE = "YES"
        DM_WIDTH = 4
        DQ_CNT_WIDTH = 5
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_TYPE = "DDR3"
        DRAM_WIDTH = 8
        ECC = "OFF"
        ECC_WIDTH = 0
        ECC_TEST = "OFF"
        MC_ERR_ADDR_WIDTH = 29
        MASTER_PHY_CTL = 1
        nAL = 0
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        ORDERING = "NORM"
        IBUF_LPWR_MODE = "OFF"
        IODELAY_HP_MODE = "ON"
        BANK_TYPE = "HP_IO"
        DATA_IO_PRIM_TYPE = "HP_LP"
        DATA_IO_IDLE_PWRDWN = "ON"
        IODELAY_GRP = "IODELAY_MIG"
        OUTPUT_DRV = "HIGH"
        REG_CTRL = "OFF"
        RTT_NOM = "60"
        RTT_WR = "OFF"
        STARVE_LIMIT = 2
        tCK = 1666
        tCKE = 5000
        tFAW = 30000
        tPRDI = 1000000
        tRAS = 35000
        tRCD = 13750
        tREFI = 7800000
        tRFC = 300000
        tRP = 13750
        tRRD = 6000
        tRTP = 7500
        tWTR = 7500
        tZQI = 128000000
        tZQCS = 64
        USER_REFRESH = "OFF"
        TEMP_MON_EN = "ON"
        WRLVL = "ON"
        DEBUG_PORT = "ON"
        CAL_WIDTH = "HALF"
        RANK_WIDTH = 1
        RANKS = 1
        ODT_WIDTH = 1
        ROW_WIDTH = 15
        ADDR_WIDTH = 29
        APP_MASK_WIDTH = 32
        APP_DATA_WIDTH = 256
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        PHY_0_BITLANES = 48'b001111111110001111111110001111111110001011111111
        PHY_1_BITLANES = 48'b001111111111111111111111110000000000000000000000
        PHY_2_BITLANES = 48'b000000000000000000000000000000000000000000000000
        CK_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
        ADDR_MAP = 192'b000000000000000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011
        BANK_MAP = 36'b000100101010000100100101000100100100
        CAS_MAP = 12'b000100100010
        CKE_ODT_BYTE_MAP = 8'b00000000
        CKE_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
        ODT_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
        CKE_ODT_AUX = "FALSE"
        CS_MAP = 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000
        PARITY_MAP = 12'b000000000000
        RAS_MAP = 12'b000100100011
        WE_MAP = 12'b000100100001
        DQS_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
        DATA0_MAP = 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
        DATA1_MAP = 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
        DATA2_MAP = 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
        DATA3_MAP = 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
        DATA4_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA5_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA6_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA7_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA8_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA9_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA10_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA11_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA12_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA13_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA14_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA15_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA16_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA17_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        MASK0_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
        MASK1_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        SLOT_0_CONFIG = 8'b00000001
        SLOT_1_CONFIG = 8'b00000000
        MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
        CALIB_ROW_ADD = 16'b0000000000000000
        CALIB_COL_ADD = 12'b000000000000
        CALIB_BA_ADD = 3'b000
        SIM_BYPASS_INIT_CAL = "OFF"
        REFCLK_FREQ = 200.000000
        USE_CS_PORT = 1
        USE_DM_PORT = 1
        USE_ODT_PORT = 1
        C_S_AXI_ID_WIDTH = 4
        C_S_AXI_ADDR_WIDTH = 32
        C_S_AXI_DATA_WIDTH = 128
        C_S_AXI_SUPPORTS_NARROW_BURST = 1
        C_RD_WR_ARB_ALGORITHM = "ROUND_ROBIN"
        C_S_AXI_REG_EN0 = 20'b00000000000000000000
        C_S_AXI_REG_EN1 = 20'b00000000000000000000
        C_S_AXI_CTRL_ADDR_WIDTH = 32
        C_S_AXI_CTRL_DATA_WIDTH = 32
        C_S_AXI_BASEADDR = 32'b00000000000000000000000000000000
        C_ECC_ONOFF_RESET_VALUE = 1
        C_ECC_CE_COUNTER_WIDTH = 8
    Set property "KEEP = TRUE" for signal <reset>.
    Set property "MAX_FANOUT = 30" for signal <reset>.
WARNING:Xst:647 - Input <s_axi_ctrl_awaddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <s_axi_ctrl_wdata> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <s_axi_ctrl_araddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <s_axi_ctrl_awvalid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <s_axi_ctrl_wvalid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <s_axi_ctrl_bready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <s_axi_ctrl_arvalid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <s_axi_ctrl_rready> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" line 654: Output port <ecc_err_addr> of the instance <mem_intfc0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" line 654: Output port <ecc_single> of the instance <mem_intfc0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_axi.v" line 654: Output port <init_wrcal_complete> of the instance <mem_intfc0> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <error> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <reset>.
    Found 1-bit register for signal <init_calib_complete_r>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <mig_7series_v1_8_memc_ui_top_axi> synthesized.

Synthesizing Unit <mig_7series_v1_8_mem_intfc>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ip_top/mig_7series_v1_8_mem_intfc.v".
        TCQ = 100
        PAYLOAD_WIDTH = 32
        ADDR_CMD_MODE = "1T"
        AL = "0"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        BURST_TYPE = "SEQ"
        CA_MIRROR = "OFF"
        CK_WIDTH = 1
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        PHY_0_BITLANES = 48'b001111111110001111111110001111111110001011111111
        PHY_1_BITLANES = 48'b001111111111111111111111110000000000000000000000
        PHY_2_BITLANES = 48'b000000000000000000000000000000000000000000000000
        CK_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
        ADDR_MAP = 192'b000000000000000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011
        BANK_MAP = 36'b000100101010000100100101000100100100
        CAS_MAP = 12'b000100100010
        CKE_ODT_BYTE_MAP = 8'b00000000
        CKE_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
        ODT_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
        CKE_ODT_AUX = "FALSE"
        CS_MAP = 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000
        PARITY_MAP = 12'b000000000000
        RAS_MAP = 12'b000100100011
        WE_MAP = 12'b000100100001
        DQS_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
        DATA0_MAP = 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
        DATA1_MAP = 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
        DATA2_MAP = 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
        DATA3_MAP = 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
        DATA4_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA5_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA6_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA7_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA8_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA9_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA10_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA11_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA12_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA13_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA14_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA15_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA16_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA17_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        MASK0_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
        MASK1_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        CALIB_ROW_ADD = 16'b0000000000000000
        CALIB_COL_ADD = 12'b000000000000
        CALIB_BA_ADD = 3'b000
        CL = 9
        COL_WIDTH = 10
        CMD_PIPE_PLUS1 = "ON"
        CS_WIDTH = 1
        CKE_WIDTH = 1
        CWL = 7
        DATA_WIDTH = 32
        DATA_BUF_ADDR_WIDTH = 5
        DATA_BUF_OFFSET_WIDTH = 1
        DDR2_DQSN_ENABLE = "YES"
        DM_WIDTH = 4
        DQ_CNT_WIDTH = 5
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_TYPE = "DDR3"
        DRAM_WIDTH = 8
        ECC = "OFF"
        ECC_WIDTH = 0
        MC_ERR_ADDR_WIDTH = 29
        nAL = 0
        nBANK_MACHS = 4
        PRE_REV3ES = "OFF"
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        PHYCTL_CMD_FIFO = "FALSE"
        ORDERING = "NORM"
        PHASE_DETECT = "OFF"
        IBUF_LPWR_MODE = "OFF"
        IODELAY_HP_MODE = "ON"
        BANK_TYPE = "HP_IO"
        DATA_IO_PRIM_TYPE = "HP_LP"
        DATA_IO_IDLE_PWRDWN = "ON"
        IODELAY_GRP = "IODELAY_MIG"
        OUTPUT_DRV = "HIGH"
        REG_CTRL = "OFF"
        RTT_NOM = "60"
        RTT_WR = "OFF"
        STARVE_LIMIT = 2
        tCK = 1666
        tCKE = 5000
        tFAW = 30000
        tPRDI = 1000000
        tRAS = 35000
        tRCD = 13750
        tREFI = 7800000
        tRFC = 300000
        tRP = 13750
        tRRD = 6000
        tRTP = 7500
        tWTR = 7500
        tZQI = 128000000
        tZQCS = 64
        WRLVL = "ON"
        DEBUG_PORT = "ON"
        CAL_WIDTH = "HALF"
        RANK_WIDTH = 1
        RANKS = 1
        ODT_WIDTH = 1
        ROW_WIDTH = 15
        SLOT_0_CONFIG = 8'b00000001
        SLOT_1_CONFIG = 8'b00000000
        SIM_BYPASS_INIT_CAL = "OFF"
        REFCLK_FREQ = 200.000000
        nDQS_COL0 = 4
        nDQS_COL1 = 0
        nDQS_COL2 = 0
        nDQS_COL3 = 0
        DQS_LOC_COL0 = 144'b000100010001000000001111000011100000110100001100000010110000101000001001000010000000011100000110000001010000010000000011000000100000000100000000
        DQS_LOC_COL1 = 0
        DQS_LOC_COL2 = 0
        DQS_LOC_COL3 = 0
        USE_CS_PORT = 1
        USE_DM_PORT = 1
        USE_ODT_PORT = 1
        MASTER_PHY_CTL = 1
        USER_REFRESH = "OFF"
        TEMP_MON_EN = "ON"
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_mem_intfc> synthesized.

Synthesizing Unit <mig_7series_v1_8_mc>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        CL = 9
        CMD_PIPE_PLUS1 = "ON"
        COL_WIDTH = 10
        CS_WIDTH = 1
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DATA_BUF_OFFSET_WIDTH = 1
        DATA_WIDTH = 32
        DQ_WIDTH = 32
        DQS_WIDTH = 4
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ECC_WIDTH = 0
        MAINT_PRESCALER_PERIOD = 200000
        MC_ERR_ADDR_WIDTH = 29
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        nREFRESH_BANK = 1
        nSLOTS = 1
        ORDERING = "NORM"
        PAYLOAD_WIDTH = 32
        RANK_WIDTH = 1
        RANKS = 1
        REG_CTRL = "OFF"
        ROW_WIDTH = 15
        RTT_NOM = "60"
        RTT_WR = "OFF"
        SLOT_0_CONFIG = 8'b00001111
        SLOT_1_CONFIG = 8'b00000000
        STARVE_LIMIT = 2
        tCK = 1666
        tCKE = 5000
        tFAW = 30000
        tRAS = 35000
        tRCD = 13750
        tREFI = 7800000
        CKE_ODT_AUX = "FALSE"
        tRFC = 300000
        tRP = 13750
        tRRD = 6000
        tRTP = 7500
        tWTR = 7500
        tZQCS = 64
        tZQI = 128000000
        tPRDI = 1000000
        USER_REFRESH = "OFF"
    Set property "KEEP = TRUE" for signal <wr_data_addr>.
    Set property "MAX_FANOUT = 30" for signal <wr_data_addr>.
    Set property "KEEP = TRUE" for signal <wr_data_offset>.
    Set property "MAX_FANOUT = 30" for signal <wr_data_offset>.
WARNING:Xst:647 - Input <raw_not_ecc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <correct_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v" line 667: Output port <sent_col_r> of the instance <bank_mach0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v" line 667: Output port <idle> of the instance <bank_mach0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v" line 771: Output port <ecc_status_valid> of the instance <col_mach0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_mc.v" line 771: Output port <wr_ecc_buf> of the instance <col_mach0> is unconnected or connected to loadless signal.
    Found 12-bit register for signal <mc_bank>.
    Found 4-bit register for signal <mc_cas_n>.
    Found 4-bit register for signal <mc_cs_n>.
    Found 2-bit register for signal <mc_odt>.
    Found 4-bit register for signal <mc_cke>.
    Found 4-bit register for signal <mc_aux_out0>.
    Found 4-bit register for signal <mc_aux_out1>.
    Found 3-bit register for signal <mc_cmd>.
    Found 4-bit register for signal <mc_ras_n>.
    Found 4-bit register for signal <mc_we_n>.
    Found 6-bit register for signal <mc_data_offset>.
    Found 6-bit register for signal <mc_data_offset_1>.
    Found 6-bit register for signal <mc_data_offset_2>.
    Found 2-bit register for signal <mc_cas_slot>.
    Found 1-bit register for signal <mc_wrdata_en>.
    Found 5-bit register for signal <wr_data_addr>.
    Found 1-bit register for signal <wr_data_en>.
    Found 1-bit register for signal <wr_data_offset>.
    Found 1-bit register for signal <mc_read_idle_r>.
    Found 1-bit register for signal <mc_ref_zq_wip_r>.
    Found 60-bit register for signal <mc_address>.
    Found 1-bit register for signal <mc_rank_cnt>.
    WARNING:Xst:2404 -  FFs/Latches <mc_rank_cnt<1:1>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_mc>.
    Summary:
	inferred 136 D-type flip-flop(s).
Unit <mig_7series_v1_8_mc> synthesized.

Synthesizing Unit <mig_7series_v1_8_rank_mach>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_mach.v".
        BURST_MODE = "8"
        CS_WIDTH = 1
        DRAM_TYPE = "DDR3"
        MAINT_PRESCALER_DIV = 30
        nBANK_MACHS = 4
        nCKESR = 5
        nCK_PER_CLK = 4
        CL = 9
        CWL = 7
        DQRD2DQWR_DLY = 4
        nFAW = 19
        nREFRESH_BANK = 1
        nRRD = 4
        nWTR = 5
        PERIODIC_RD_TIMER_DIV = 5
        RANK_BM_BV_WIDTH = 4
        RANK_WIDTH = 1
        RANKS = 1
        REFRESH_TIMER_DIV = 38
        ZQ_TIMER_DIV = 640000
    Summary:
	no macro.
Unit <mig_7series_v1_8_rank_mach> synthesized.

Synthesizing Unit <mig_7series_v1_8_rank_cntrl>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_cntrl.v".
        TCQ = 100
        BURST_MODE = "8"
        DQRD2DQWR_DLY = 4
        CL = 9
        CWL = 7
        ID = 0
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nFAW = 19
        nREFRESH_BANK = 1
        nRRD = 4
        nWTR = 5
        PERIODIC_RD_TIMER_DIV = 5
        RANK_BM_BV_WIDTH = 4
        RANK_WIDTH = 1
        RANKS = 1
        REFRESH_TIMER_DIV = 38
WARNING:Xst:2935 - Signal 'add_rrd_inhbt', unconnected in block 'mig_7series_v1_8_rank_cntrl', is tied to its initial value (0).
    Found 1-bit register for signal <inhbt_act_faw_r>.
    Found 2-bit register for signal <wtr_timer.wtr_cnt_r>.
    Found 2-bit register for signal <rtw_timer.rtw_cnt_r>.
    Found 1-bit register for signal <refresh_generation.refresh_bank_r>.
    Found 1-bit register for signal <periodic_rd_generation.read_this_rank_r>.
    Found 1-bit register for signal <periodic_rd_generation.periodic_rd_cntr1_r>.
    Found 3-bit register for signal <periodic_rd_generation.periodic_rd_timer_r>.
    Found 1-bit register for signal <periodic_rd_generation.periodic_rd_request_r>.
    Found 3-bit register for signal <inhbt_act_faw.faw_cnt_r>.
    Found 3-bit subtractor for signal <inhbt_act_faw.faw_cnt_r[2]_GND_20_o_sub_5_OUT> created at line 295.
    Found 2-bit subtractor for signal <wtr_timer.wtr_cnt_r[1]_GND_20_o_sub_14_OUT> created at line 346.
    Found 2-bit subtractor for signal <rtw_timer.rtw_cnt_r[1]_GND_20_o_sub_24_OUT> created at line 393.
    Found 3-bit subtractor for signal <periodic_rd_generation.periodic_rd_timer_r[2]_GND_20_o_sub_44_OUT> created at line 516.
    Found 3-bit adder for signal <inhbt_act_faw.faw_cnt_r[2]_GND_20_o_add_2_OUT> created at line 294.
    Found 1-bit adder for signal <refresh_generation.refresh_bank_r[0]_GND_20_o_add_32_OUT<0>> created at line 438.
    Found 1-bit adder for signal <periodic_rd_generation.periodic_rd_cntr1_r_PWR_18_o_add_40_OUT<0>> created at line 497.
    Summary:
	inferred   7 Adder/Subtractor(s).
	inferred  15 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <mig_7series_v1_8_rank_cntrl> synthesized.

Synthesizing Unit <mig_7series_v1_8_rank_common>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_common.v".
        TCQ = 100
        DRAM_TYPE = "DDR3"
        MAINT_PRESCALER_DIV = 30
        nBANK_MACHS = 4
        nCKESR = 5
        nCK_PER_CLK = 4
        PERIODIC_RD_TIMER_DIV = 5
        RANK_WIDTH = 1
        RANKS = 1
        REFRESH_TIMER_DIV = 38
        ZQ_TIMER_DIV = 640000
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_common.v" line 294: Output port <grant_ns> of the instance <maintenance_request.maint_arb0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_rank_common.v" line 447: Output port <grant_r> of the instance <periodic_read_request.periodic_rd_arb0> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <maint_prescaler_tick_r_lcl>.
    Found 6-bit register for signal <refresh_timer.refresh_timer_r>.
    Found 20-bit register for signal <zq_cntrl.zq_timer.zq_timer_r>.
    Found 1-bit register for signal <zq_cntrl.zq_request_logic.zq_request_r>.
    Found 1-bit register for signal <sr_cntrl.sre_request_logic.sre_request_r>.
    Found 2-bit register for signal <sr_cntrl.ckesr_timer.ckesr_timer_r>.
    Found 1-bit register for signal <maintenance_request.upd_last_master_r>.
    Found 1-bit register for signal <maintenance_request.new_maint_rank_r>.
    Found 1-bit register for signal <maint_req_r_lcl>.
    Found 1-bit register for signal <maint_rank_r_lcl>.
    Found 1-bit register for signal <maint_zq_r_lcl>.
    Found 1-bit register for signal <maint_sre_r_lcl>.
    Found 1-bit register for signal <maint_srx_r_lcl>.
    Found 1-bit register for signal <app_sr_active_r>.
    Found 1-bit register for signal <app_ref_r>.
    Found 1-bit register for signal <app_ref_ack_r>.
    Found 1-bit register for signal <app_zq_r>.
    Found 1-bit register for signal <app_zq_ack_r>.
    Found 1-bit register for signal <periodic_read_request.upd_last_master_r>.
    Found 1-bit register for signal <periodic_rd_r_lcl>.
    Found 1-bit register for signal <periodic_read_request.periodic_rd_r_cnt>.
    Found 1-bit register for signal <periodic_read_request.periodic_rd_grant_r>.
    Found 1-bit register for signal <periodic_rd_rank_r_lcl>.
    Found 1-bit register for signal <maint_ref_zq_wip_r>.
    Found 5-bit register for signal <maint_prescaler.maint_prescaler_r>.
    Found 5-bit subtractor for signal <maint_prescaler.maint_prescaler_r[4]_GND_22_o_sub_3_OUT> created at line 125.
    Found 6-bit subtractor for signal <refresh_timer.refresh_timer_r[5]_GND_22_o_sub_10_OUT> created at line 150.
    Found 20-bit subtractor for signal <zq_cntrl.zq_timer.zq_timer_r[19]_GND_22_o_sub_17_OUT> created at line 178.
    Found 2-bit subtractor for signal <sr_cntrl.ckesr_timer.ckesr_timer_r[1]_GND_22_o_sub_26_OUT> created at line 243.
    Found 1-bit adder for signal <n0207> created at line 334.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_38_OUT<0>> created at line 337.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_39_OUT<0>> created at line 337.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_40_OUT<0>> created at line 337.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_41_OUT<0>> created at line 337.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_42_OUT<0>> created at line 337.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_43_OUT<0>> created at line 337.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_44_OUT<0>> created at line 337.
    Found 1-bit adder for signal <maint_rank_r_lcl[0]_PWR_22_o_add_45_OUT<0>> created at line 337.
    Summary:
	inferred  13 Adder/Subtractor(s).
	inferred  54 D-type flip-flop(s).
	inferred  21 Multiplexer(s).
Unit <mig_7series_v1_8_rank_common> synthesized.

Synthesizing Unit <mig_7series_v1_8_round_robin_arb_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v".
        TCQ = 100
        WIDTH = 3
    Found 3-bit register for signal <last_master_r>.
    Found 3-bit register for signal <grant_r>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <mig_7series_v1_8_round_robin_arb_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_round_robin_arb_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v".
        TCQ = 100
        WIDTH = 1
WARNING:Xst:647 - Input <current_master> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <upd_last_master> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <channel[0].inh_group> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <grant_r>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_round_robin_arb_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_mach>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_mach.v".
        TCQ = 100
        EVEN_CWL_2T_MODE = "OFF"
        ADDR_CMD_MODE = "1T"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        COL_WIDTH = 10
        CS_WIDTH = 1
        CL = 9
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        EARLY_WR_DATA_ADDR = "OFF"
        ECC = "OFF"
        LOW_IDLE_CNT = 0
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        nOP_WAIT = 0
        nRAS = 22
        nRCD = 9
        nRFC = 181
        nRTP = 5
        CKE_ODT_AUX = "FALSE"
        nRP = 9
        nSLOTS = 1
        nWR = 10
        nXSDLL = 512
        ORDERING = "NORM"
        RANK_BM_BV_WIDTH = 4
        RANK_WIDTH = 1
        RANKS = 1
        ROW_WIDTH = 15
        RTT_NOM = "60"
        RTT_WR = "OFF"
        STARVE_LIMIT = 2
        SLOT_0_CONFIG = 8'b00001111
        SLOT_1_CONFIG = 8'b00000000
        tZQCS = 64
    Summary:
	no macro.
Unit <mig_7series_v1_8_bank_mach> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_cntrl_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        COL_WIDTH = 10
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 0
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRCD = 9
        nRTP = 5
        nRP = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANK_WIDTH = 1
        RANKS = 1
        RAS_TIMER_WIDTH = 3
        ROW_WIDTH = 15
        STARVE_LIMIT = 2
    Summary:
	no macro.
Unit <mig_7series_v1_8_bank_cntrl_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_compare>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_compare.v".
        BANK_WIDTH = 3
        TCQ = 100
        BURST_MODE = "8"
        COL_WIDTH = 10
        DATA_BUF_ADDR_WIDTH = 5
        ECC = "OFF"
        RANK_WIDTH = 1
        RANKS = 1
        ROW_WIDTH = 15
WARNING:Xst:647 - Input <size> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'req_rank_r_lcl', unconnected in block 'mig_7series_v1_8_bank_compare', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'req_rank_ns', unconnected in block 'mig_7series_v1_8_bank_compare', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'req_col_r<14>', unconnected in block 'mig_7series_v1_8_bank_compare', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'req_col_r<11:10>', unconnected in block 'mig_7series_v1_8_bank_compare', is tied to its initial value (00).
    Found 1-bit register for signal <req_periodic_rd_r_lcl>.
    Found 3-bit register for signal <req_cmd_r>.
    Found 1-bit register for signal <rd_wr_r_lcl>.
    Found 3-bit register for signal <req_bank_r_lcl>.
    Found 15-bit register for signal <req_row_r_lcl>.
    Found 1-bit register for signal <req_col_r<9>>.
    Found 1-bit register for signal <req_col_r<8>>.
    Found 1-bit register for signal <req_col_r<7>>.
    Found 1-bit register for signal <req_col_r<6>>.
    Found 1-bit register for signal <req_col_r<5>>.
    Found 1-bit register for signal <req_col_r<4>>.
    Found 1-bit register for signal <req_col_r<3>>.
    Found 1-bit register for signal <req_col_r<2>>.
    Found 1-bit register for signal <req_col_r<1>>.
    Found 1-bit register for signal <req_col_r<0>>.
    Found 1-bit register for signal <req_wr_r_lcl>.
    Found 1-bit register for signal <req_priority_r>.
    Found 1-bit register for signal <rb_hit_busy_r>.
    Found 1-bit register for signal <row_hit_r>.
    Found 1-bit register for signal <rank_busy_r>.
    Found 5-bit register for signal <req_data_buf_addr_r>.
    Found 1-bit shifter logical left for signal <PWR_30_o_req_rank_ns[0]_shift_left_30_OUT<0>> created at line 281
    Found 3-bit comparator equal for signal <bank_hit> created at line 221
    Found 15-bit comparator equal for signal <row_hit_ns> created at line 230
    Summary:
	inferred  43 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   5 Multiplexer(s).
	inferred   1 Combinational logic shifter(s).
Unit <mig_7series_v1_8_bank_compare> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_state_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 0
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRP = 9
        nRTP = 5
        nRCD = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANKS = 1
        RANK_WIDTH = 1
        RAS_TIMER_WIDTH = 3
        STARVE_LIMIT = 2
WARNING:Xst:647 - Input <rd_data_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_data_buf_addr_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<23:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_rank_r_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rddata_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rd_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <low_idle_cnt_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <op_exit_grant> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tail_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rcd_active_r', unconnected in block 'mig_7series_v1_8_bank_state_1', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'mig_7series_v1_8_bank_state_1', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'mig_7series_v1_8_bank_state_1', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'mig_7series_v1_8_bank_state_1', is tied to its initial value (0).
    Found 1-bit register for signal <act_wait_r_lcl>.
    Found 1-bit register for signal <col_wait_r>.
    Found 3-bit register for signal <ras_timer_r>.
    Found 1-bit register for signal <ras_timer_zero_r>.
    Found 2-bit register for signal <rtp_timer_r>.
    Found 1-bit register for signal <pre_wait_r>.
    Found 1-bit register for signal <rp_timer_r>.
    Found 2-bit register for signal <act_starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_act_priority_r>.
    Found 1-bit register for signal <act_this_rank_r>.
    Found 1-bit register for signal <req_bank_rdy_r>.
    Found 3-bit register for signal <starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_priority_r>.
    Found 1-bit register for signal <demanded_prior_r>.
    Found 1-bit register for signal <phy_mc_ctl_full_r>.
    Found 1-bit register for signal <phy_mc_cmd_full_r>.
    Found 1-bit register for signal <ofs_rdy_r>.
    Found 1-bit register for signal <override_demand_r>.
    Found 1-bit register for signal <wr_this_rank_r>.
    Found 1-bit register for signal <rd_this_rank_r>.
    Found 1-bit register for signal <bm_end_r1>.
    Found 3-bit subtractor for signal <ras_timer_r[2]_GND_29_o_sub_10_OUT> created at line 370.
    Found 2-bit subtractor for signal <rtp_timer_r[1]_GND_29_o_sub_24_OUT> created at line 407.
    Found 1-bit adder for signal <rp_timer_r[0]_GND_29_o_add_31_OUT<0>> created at line 524.
    Found 2-bit adder for signal <act_starve_limit_cntr_r[1]_GND_29_o_add_36_OUT> created at line 602.
    Found 3-bit adder for signal <starve_limit_cntr_r[2]_GND_29_o_add_49_OUT> created at line 708.
    Found 3-bit comparator lessequal for signal <n0027> created at line 369
    Found 1-bit comparator equal for signal <rnk_config[0]_req_rank_r[0]_equal_59_o> created at line 800
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   9 Multiplexer(s).
Unit <mig_7series_v1_8_bank_state_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_queue_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v".
        TCQ = 100
        BM_CNT_WIDTH = 2
        nBANK_MACHS = 4
        ORDERING = "NORM"
        ID = 0
WARNING:Xst:647 - Input <bm_end_in<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bm_end_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:4>', unconnected in block 'mig_7series_v1_8_bank_queue_1', is tied to its initial value (0000).
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<0>', unconnected in block 'mig_7series_v1_8_bank_queue_1', is tied to its initial value (0).
    Found 1-bit register for signal <head_r_lcl>.
    Found 1-bit register for signal <tail_r_lcl>.
    Found 1-bit register for signal <idle_r_lcl>.
    Found 1-bit register for signal <pass_open_bank_r_lcl>.
    Found 1-bit register for signal <auto_pre_r_lcl>.
    Found 1-bit register for signal <pre_bm_end_r>.
    Found 1-bit register for signal <pre_passing_open_bank_r>.
    Found 1-bit register for signal <ordered_r_lcl>.
    Found 2-bit register for signal <order_q_r>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<3>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<2>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<1>>.
    Found 1-bit register for signal <q_has_rd_r>.
    Found 1-bit register for signal <q_has_priority_r>.
    Found 1-bit register for signal <wait_for_maint_r_lcl>.
    Found 2-bit register for signal <q_entry_r>.
    Found 2-bit subtractor for signal <temp[1]_GND_30_o_sub_5_OUT> created at line 278.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_30_o_sub_6_OUT> created at line 282.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_30_o_sub_18_OUT> created at line 306.
    Found 2-bit subtractor for signal <q_entry_r[1]_GND_30_o_sub_20_OUT> created at line 309.
    Found 2-bit subtractor for signal <idle_cnt[1]_GND_30_o_sub_23_OUT> created at line 311.
    Found 2-bit subtractor for signal <order_cnt[1]_GND_30_o_sub_36_OUT> created at line 484.
    Found 2-bit subtractor for signal <order_q_r[1]_GND_30_o_sub_40_OUT> created at line 486.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  18 D-type flip-flop(s).
	inferred  15 Multiplexer(s).
Unit <mig_7series_v1_8_bank_queue_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_cntrl_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        COL_WIDTH = 10
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 1
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRCD = 9
        nRTP = 5
        nRP = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANK_WIDTH = 1
        RANKS = 1
        RAS_TIMER_WIDTH = 3
        ROW_WIDTH = 15
        STARVE_LIMIT = 2
    Summary:
	no macro.
Unit <mig_7series_v1_8_bank_cntrl_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_state_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 1
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRP = 9
        nRTP = 5
        nRCD = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANKS = 1
        RANK_WIDTH = 1
        RAS_TIMER_WIDTH = 3
        STARVE_LIMIT = 2
WARNING:Xst:647 - Input <rd_data_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_data_buf_addr_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<23:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_rank_r_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rddata_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rd_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <low_idle_cnt_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <op_exit_grant> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tail_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rcd_active_r', unconnected in block 'mig_7series_v1_8_bank_state_2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'mig_7series_v1_8_bank_state_2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'mig_7series_v1_8_bank_state_2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'mig_7series_v1_8_bank_state_2', is tied to its initial value (0).
    Found 1-bit register for signal <act_wait_r_lcl>.
    Found 1-bit register for signal <col_wait_r>.
    Found 3-bit register for signal <ras_timer_r>.
    Found 1-bit register for signal <ras_timer_zero_r>.
    Found 2-bit register for signal <rtp_timer_r>.
    Found 1-bit register for signal <pre_wait_r>.
    Found 1-bit register for signal <rp_timer_r>.
    Found 2-bit register for signal <act_starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_act_priority_r>.
    Found 1-bit register for signal <act_this_rank_r>.
    Found 1-bit register for signal <req_bank_rdy_r>.
    Found 3-bit register for signal <starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_priority_r>.
    Found 1-bit register for signal <demanded_prior_r>.
    Found 1-bit register for signal <phy_mc_ctl_full_r>.
    Found 1-bit register for signal <phy_mc_cmd_full_r>.
    Found 1-bit register for signal <ofs_rdy_r>.
    Found 1-bit register for signal <override_demand_r>.
    Found 1-bit register for signal <wr_this_rank_r>.
    Found 1-bit register for signal <rd_this_rank_r>.
    Found 1-bit register for signal <bm_end_r1>.
    Found 3-bit subtractor for signal <ras_timer_r[2]_GND_32_o_sub_10_OUT> created at line 370.
    Found 2-bit subtractor for signal <rtp_timer_r[1]_GND_32_o_sub_24_OUT> created at line 407.
    Found 1-bit adder for signal <rp_timer_r[0]_GND_32_o_add_31_OUT<0>> created at line 524.
    Found 2-bit adder for signal <act_starve_limit_cntr_r[1]_GND_32_o_add_36_OUT> created at line 602.
    Found 3-bit adder for signal <starve_limit_cntr_r[2]_GND_32_o_add_49_OUT> created at line 708.
    Found 3-bit comparator lessequal for signal <n0027> created at line 369
    Found 1-bit comparator equal for signal <rnk_config[0]_req_rank_r[0]_equal_59_o> created at line 800
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   9 Multiplexer(s).
Unit <mig_7series_v1_8_bank_state_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_queue_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v".
        TCQ = 100
        BM_CNT_WIDTH = 2
        nBANK_MACHS = 4
        ORDERING = "NORM"
        ID = 1
WARNING:Xst:647 - Input <bm_end_in<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bm_end_in<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:5>', unconnected in block 'mig_7series_v1_8_bank_queue_2', is tied to its initial value (000).
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<1:0>', unconnected in block 'mig_7series_v1_8_bank_queue_2', is tied to its initial value (00).
    Found 1-bit register for signal <head_r_lcl>.
    Found 1-bit register for signal <tail_r_lcl>.
    Found 1-bit register for signal <idle_r_lcl>.
    Found 1-bit register for signal <pass_open_bank_r_lcl>.
    Found 1-bit register for signal <auto_pre_r_lcl>.
    Found 1-bit register for signal <pre_bm_end_r>.
    Found 1-bit register for signal <pre_passing_open_bank_r>.
    Found 1-bit register for signal <ordered_r_lcl>.
    Found 2-bit register for signal <order_q_r>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<4>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<3>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<2>>.
    Found 1-bit register for signal <q_has_rd_r>.
    Found 1-bit register for signal <q_has_priority_r>.
    Found 1-bit register for signal <wait_for_maint_r_lcl>.
    Found 2-bit register for signal <q_entry_r>.
    Found 2-bit subtractor for signal <temp[1]_GND_33_o_sub_5_OUT> created at line 278.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_33_o_sub_6_OUT> created at line 282.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_33_o_sub_18_OUT> created at line 306.
    Found 2-bit subtractor for signal <q_entry_r[1]_GND_33_o_sub_20_OUT> created at line 309.
    Found 2-bit subtractor for signal <idle_cnt[1]_GND_33_o_sub_23_OUT> created at line 311.
    Found 2-bit subtractor for signal <order_cnt[1]_GND_33_o_sub_36_OUT> created at line 484.
    Found 2-bit subtractor for signal <order_q_r[1]_GND_33_o_sub_40_OUT> created at line 486.
    Found 2-bit adder for signal <temp> created at line 274.
    Summary:
	inferred   7 Adder/Subtractor(s).
	inferred  18 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <mig_7series_v1_8_bank_queue_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_cntrl_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        COL_WIDTH = 10
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 2
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRCD = 9
        nRTP = 5
        nRP = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANK_WIDTH = 1
        RANKS = 1
        RAS_TIMER_WIDTH = 3
        ROW_WIDTH = 15
        STARVE_LIMIT = 2
    Summary:
	no macro.
Unit <mig_7series_v1_8_bank_cntrl_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_state_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 2
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRP = 9
        nRTP = 5
        nRCD = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANKS = 1
        RANK_WIDTH = 1
        RAS_TIMER_WIDTH = 3
        STARVE_LIMIT = 2
WARNING:Xst:647 - Input <rd_data_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_data_buf_addr_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<8:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<23:18>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_rank_r_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rddata_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rd_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <low_idle_cnt_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <op_exit_grant> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tail_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rcd_active_r', unconnected in block 'mig_7series_v1_8_bank_state_3', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'mig_7series_v1_8_bank_state_3', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'mig_7series_v1_8_bank_state_3', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'mig_7series_v1_8_bank_state_3', is tied to its initial value (0).
    Found 1-bit register for signal <act_wait_r_lcl>.
    Found 1-bit register for signal <col_wait_r>.
    Found 3-bit register for signal <ras_timer_r>.
    Found 1-bit register for signal <ras_timer_zero_r>.
    Found 2-bit register for signal <rtp_timer_r>.
    Found 1-bit register for signal <pre_wait_r>.
    Found 1-bit register for signal <rp_timer_r>.
    Found 2-bit register for signal <act_starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_act_priority_r>.
    Found 1-bit register for signal <act_this_rank_r>.
    Found 1-bit register for signal <req_bank_rdy_r>.
    Found 3-bit register for signal <starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_priority_r>.
    Found 1-bit register for signal <demanded_prior_r>.
    Found 1-bit register for signal <phy_mc_ctl_full_r>.
    Found 1-bit register for signal <phy_mc_cmd_full_r>.
    Found 1-bit register for signal <ofs_rdy_r>.
    Found 1-bit register for signal <override_demand_r>.
    Found 1-bit register for signal <wr_this_rank_r>.
    Found 1-bit register for signal <rd_this_rank_r>.
    Found 1-bit register for signal <bm_end_r1>.
    Found 3-bit subtractor for signal <ras_timer_r[2]_GND_35_o_sub_10_OUT> created at line 370.
    Found 2-bit subtractor for signal <rtp_timer_r[1]_GND_35_o_sub_24_OUT> created at line 407.
    Found 1-bit adder for signal <rp_timer_r[0]_GND_35_o_add_31_OUT<0>> created at line 524.
    Found 2-bit adder for signal <act_starve_limit_cntr_r[1]_GND_35_o_add_36_OUT> created at line 602.
    Found 3-bit adder for signal <starve_limit_cntr_r[2]_GND_35_o_add_49_OUT> created at line 708.
    Found 3-bit comparator lessequal for signal <n0027> created at line 369
    Found 1-bit comparator equal for signal <rnk_config[0]_req_rank_r[0]_equal_59_o> created at line 800
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   9 Multiplexer(s).
Unit <mig_7series_v1_8_bank_state_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_queue_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v".
        TCQ = 100
        BM_CNT_WIDTH = 2
        nBANK_MACHS = 4
        ORDERING = "NORM"
        ID = 2
WARNING:Xst:647 - Input <bm_end_in<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bm_end_in<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7:6>', unconnected in block 'mig_7series_v1_8_bank_queue_3', is tied to its initial value (00).
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<2:0>', unconnected in block 'mig_7series_v1_8_bank_queue_3', is tied to its initial value (000).
    Found 1-bit register for signal <head_r_lcl>.
    Found 1-bit register for signal <tail_r_lcl>.
    Found 1-bit register for signal <idle_r_lcl>.
    Found 1-bit register for signal <pass_open_bank_r_lcl>.
    Found 1-bit register for signal <auto_pre_r_lcl>.
    Found 1-bit register for signal <pre_bm_end_r>.
    Found 1-bit register for signal <pre_passing_open_bank_r>.
    Found 1-bit register for signal <ordered_r_lcl>.
    Found 2-bit register for signal <order_q_r>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<5>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<4>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<3>>.
    Found 1-bit register for signal <q_has_rd_r>.
    Found 1-bit register for signal <q_has_priority_r>.
    Found 1-bit register for signal <wait_for_maint_r_lcl>.
    Found 2-bit register for signal <q_entry_r>.
    Found 2-bit subtractor for signal <temp[1]_GND_36_o_sub_5_OUT> created at line 278.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_36_o_sub_6_OUT> created at line 282.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_36_o_sub_18_OUT> created at line 306.
    Found 2-bit subtractor for signal <q_entry_r[1]_GND_36_o_sub_20_OUT> created at line 309.
    Found 2-bit subtractor for signal <idle_cnt[1]_GND_36_o_sub_23_OUT> created at line 311.
    Found 2-bit subtractor for signal <order_cnt[1]_GND_36_o_sub_36_OUT> created at line 484.
    Found 2-bit subtractor for signal <order_q_r[1]_GND_36_o_sub_40_OUT> created at line 486.
    Found 2-bit adder for signal <n0210> created at line 229.
    Found 2-bit adder for signal <temp> created at line 274.
    Summary:
	inferred   8 Adder/Subtractor(s).
	inferred  18 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <mig_7series_v1_8_bank_queue_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_cntrl_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_cntrl.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BANK_WIDTH = 3
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        COL_WIDTH = 10
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 3
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRCD = 9
        nRTP = 5
        nRP = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANK_WIDTH = 1
        RANKS = 1
        RAS_TIMER_WIDTH = 3
        ROW_WIDTH = 15
        STARVE_LIMIT = 2
    Summary:
	no macro.
Unit <mig_7series_v1_8_bank_cntrl_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_state_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_state.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        BM_CNT_WIDTH = 2
        BURST_MODE = "8"
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        ECC = "OFF"
        ID = 3
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRAS_CLKS = 6
        nRP = 9
        nRTP = 5
        nRCD = 9
        nWTP_CLKS = 7
        ORDERING = "NORM"
        RANKS = 1
        RANK_WIDTH = 1
        RAS_TIMER_WIDTH = 3
        STARVE_LIMIT = 2
WARNING:Xst:647 - Input <rd_data_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_data_buf_addr_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ras_timer_ns_in<23:21>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busies_r<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <req_rank_r_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_rcd_in<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_act_priority_in<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <demand_priority_in<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rddata_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rd_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <low_idle_cnt_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <op_exit_grant> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tail_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rcd_active_r', unconnected in block 'mig_7series_v1_8_bank_state_4', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_rd_done', unconnected in block 'mig_7series_v1_8_bank_state_4', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rd_half_rmw_lcl', unconnected in block 'mig_7series_v1_8_bank_state_4', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rmw_wait_r', unconnected in block 'mig_7series_v1_8_bank_state_4', is tied to its initial value (0).
    Found 1-bit register for signal <act_wait_r_lcl>.
    Found 1-bit register for signal <col_wait_r>.
    Found 3-bit register for signal <ras_timer_r>.
    Found 1-bit register for signal <ras_timer_zero_r>.
    Found 2-bit register for signal <rtp_timer_r>.
    Found 1-bit register for signal <pre_wait_r>.
    Found 1-bit register for signal <rp_timer_r>.
    Found 2-bit register for signal <act_starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_act_priority_r>.
    Found 1-bit register for signal <act_this_rank_r>.
    Found 1-bit register for signal <req_bank_rdy_r>.
    Found 3-bit register for signal <starve_limit_cntr_r>.
    Found 1-bit register for signal <demand_priority_r>.
    Found 1-bit register for signal <demanded_prior_r>.
    Found 1-bit register for signal <phy_mc_ctl_full_r>.
    Found 1-bit register for signal <phy_mc_cmd_full_r>.
    Found 1-bit register for signal <ofs_rdy_r>.
    Found 1-bit register for signal <override_demand_r>.
    Found 1-bit register for signal <wr_this_rank_r>.
    Found 1-bit register for signal <rd_this_rank_r>.
    Found 1-bit register for signal <bm_end_r1>.
    Found 3-bit subtractor for signal <ras_timer_r[2]_GND_38_o_sub_10_OUT> created at line 370.
    Found 2-bit subtractor for signal <rtp_timer_r[1]_GND_38_o_sub_24_OUT> created at line 407.
    Found 1-bit adder for signal <rp_timer_r[0]_GND_38_o_add_31_OUT<0>> created at line 524.
    Found 2-bit adder for signal <act_starve_limit_cntr_r[1]_GND_38_o_add_36_OUT> created at line 602.
    Found 3-bit adder for signal <starve_limit_cntr_r[2]_GND_38_o_add_49_OUT> created at line 708.
    Found 3-bit comparator lessequal for signal <n0027> created at line 369
    Found 1-bit comparator equal for signal <rnk_config[0]_req_rank_r[0]_equal_59_o> created at line 800
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   9 Multiplexer(s).
Unit <mig_7series_v1_8_bank_state_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_queue_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_queue.v".
        TCQ = 100
        BM_CNT_WIDTH = 2
        nBANK_MACHS = 4
        ORDERING = "NORM"
        ID = 3
WARNING:Xst:647 - Input <bm_end_in<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bm_end_in<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rb_hit_busy_ns_in<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank_in<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<7>', unconnected in block 'mig_7series_v1_8_bank_queue_4', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'rb_hit_busies_r_lcl<3:0>', unconnected in block 'mig_7series_v1_8_bank_queue_4', is tied to its initial value (0000).
    Found 1-bit register for signal <head_r_lcl>.
    Found 1-bit register for signal <tail_r_lcl>.
    Found 1-bit register for signal <idle_r_lcl>.
    Found 1-bit register for signal <pass_open_bank_r_lcl>.
    Found 1-bit register for signal <auto_pre_r_lcl>.
    Found 1-bit register for signal <pre_bm_end_r>.
    Found 1-bit register for signal <pre_passing_open_bank_r>.
    Found 1-bit register for signal <ordered_r_lcl>.
    Found 2-bit register for signal <order_q_r>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<6>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<5>>.
    Found 1-bit register for signal <rb_hit_busies_r_lcl<4>>.
    Found 1-bit register for signal <q_has_rd_r>.
    Found 1-bit register for signal <q_has_priority_r>.
    Found 1-bit register for signal <wait_for_maint_r_lcl>.
    Found 2-bit register for signal <q_entry_r>.
    Found 2-bit subtractor for signal <temp[1]_GND_39_o_sub_6_OUT> created at line 278.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_39_o_sub_7_OUT> created at line 282.
    Found 2-bit subtractor for signal <rb_hit_busy_cnt[1]_GND_39_o_sub_19_OUT> created at line 306.
    Found 2-bit subtractor for signal <q_entry_r[1]_GND_39_o_sub_21_OUT> created at line 309.
    Found 2-bit subtractor for signal <idle_cnt[1]_GND_39_o_sub_24_OUT> created at line 311.
    Found 2-bit subtractor for signal <order_cnt[1]_GND_39_o_sub_37_OUT> created at line 484.
    Found 2-bit subtractor for signal <order_q_r[1]_GND_39_o_sub_41_OUT> created at line 486.
    Found 2-bit adder for signal <n0211> created at line 229.
    Found 2-bit adder for signal <idlers_below> created at line 229.
    Found 2-bit adder for signal <temp> created at line 274.
    Summary:
	inferred   9 Adder/Subtractor(s).
	inferred  18 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <mig_7series_v1_8_bank_queue_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_bank_common>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_bank_common.v".
        TCQ = 100
        BM_CNT_WIDTH = 2
        LOW_IDLE_CNT = 0
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nOP_WAIT = 0
        nRFC = 181
        nXSDLL = 512
        RANK_WIDTH = 1
        RANKS = 1
        CWL = 7
        tZQCS = 64
WARNING:Xst:647 - Input <end_rtp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <passing_open_bank> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <op_exit_req> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <start_pre_wait> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cmd<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'low_idle_cnt_r', unconnected in block 'mig_7series_v1_8_bank_common', is tied to its initial value (0).
    Found 1-bit register for signal <accept_r>.
    Found 1-bit register for signal <periodic_rd_cntr_r>.
    Found 1-bit register for signal <periodic_rd_ack_r_lcl>.
    Found 1-bit register for signal <was_wr>.
    Found 1-bit register for signal <was_priority>.
    Found 1-bit register for signal <maint_wip_r_lcl>.
    Found 4-bit register for signal <maint_controller.maint_hit_busies_r>.
    Found 1-bit register for signal <maint_controller.maint_rdy_r1>.
    Found 1-bit register for signal <maint_controller.maint_srx_r1>.
    Found 2-bit register for signal <generate_maint_cmds.send_cnt_r>.
    Found 1-bit register for signal <insert_maint_r_lcl>.
    Found 8-bit register for signal <rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r>.
    Found 1-bit register for signal <accept_internal_r>.
    Found 2-bit subtractor for signal <generate_maint_cmds.send_cnt_r[1]_GND_40_o_sub_70_OUT> created at line 387.
    Found 8-bit subtractor for signal <rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_GND_40_o_sub_81_OUT> created at line 446.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_6_OUT> created at line 179.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_8_OUT> created at line 179.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_10_OUT> created at line 179.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_14_OUT> created at line 188.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_16_OUT> created at line 188.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_18_OUT> created at line 188.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_23_OUT> created at line 201.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_25_OUT> created at line 201.
    Found 2-bit adder for signal <GND_40_o_GND_40_o_add_27_OUT> created at line 201.
    Found 2-bit adder for signal <n0230> created at line 372.
    Found 2-bit adder for signal <n0233> created at line 372.
    Found 2-bit adder for signal <n0236> created at line 372.
    Found 2-bit adder for signal <n0239> created at line 372.
    Found 2-bit adder for signal <n0242> created at line 372.
    Found 2-bit adder for signal <n0245> created at line 372.
    Found 2-bit adder for signal <generate_maint_cmds.present_count> created at line 372.
    Summary:
	inferred  18 Adder/Subtractor(s).
	inferred  24 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <mig_7series_v1_8_bank_common> synthesized.

Synthesizing Unit <mig_7series_v1_8_arb_mux>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_mux.v".
        TCQ = 100
        EVEN_CWL_2T_MODE = "OFF"
        ADDR_CMD_MODE = "1T"
        BANK_VECT_INDX = 11
        BANK_WIDTH = 3
        BURST_MODE = "8"
        CS_WIDTH = 1
        CL = 9
        CWL = 7
        DATA_BUF_ADDR_VECT_INDX = 19
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        CKE_ODT_AUX = "FALSE"
        EARLY_WR_DATA_ADDR = "OFF"
        ECC = "OFF"
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        nRAS = 22
        nRCD = 9
        nSLOTS = 1
        nWR = 10
        RANKS = 1
        RANK_VECT_INDX = 3
        RANK_WIDTH = 1
        ROW_VECT_INDX = 59
        ROW_WIDTH = 15
        RTT_NOM = "60"
        RTT_WR = "OFF"
        SLOT_0_CONFIG = 8'b00001111
        SLOT_1_CONFIG = 8'b00000000
    Summary:
	no macro.
Unit <mig_7series_v1_8_arb_mux> synthesized.

Synthesizing Unit <mig_7series_v1_8_arb_row_col>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v".
        TCQ = 100
        ADDR_CMD_MODE = "1T"
        CWL = 7
        EARLY_WR_DATA_ADDR = "OFF"
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nRAS = 22
        nRCD = 9
        nWR = 10
WARNING:Xst:647 - Input <col_rdy_wr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v" line 171: Output port <grant_ns> of the instance <row_arb0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v" line 205: Output port <grant_ns> of the instance <pre_4_1_1T_arb.pre_arb0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v" line 232: Output port <grant_ns> of the instance <config_arb0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_row_col.v" line 279: Output port <grant_ns> of the instance <col_arb0> is unconnected or connected to loadless signal.
WARNING:Xst:2935 - Signal 'send_cmd0_col', unconnected in block 'mig_7series_v1_8_arb_row_col', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'send_cmd1_row', unconnected in block 'mig_7series_v1_8_arb_row_col', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'send_cmd2_row', unconnected in block 'mig_7series_v1_8_arb_row_col', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'send_cmd2_col', unconnected in block 'mig_7series_v1_8_arb_row_col', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'send_cmd3_col', unconnected in block 'mig_7series_v1_8_arb_row_col', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'cs_en3', unconnected in block 'mig_7series_v1_8_arb_row_col', is tied to its initial value (0).
    Found 1-bit register for signal <pre_4_1_1T_arb.granted_pre_r>.
    Found 1-bit register for signal <rnk_config_strobe_r<0>>.
    Found 1-bit register for signal <rnk_config_strobe_r<1>>.
    Found 1-bit register for signal <rnk_config_strobe_r<2>>.
    Found 1-bit register for signal <rnk_config_valid_r_lcl>.
    Found 1-bit register for signal <sent_col_lcl>.
    Found 1-bit register for signal <sent_col_lcl_r>.
    Found 1-bit register for signal <insert_maint_r1_lcl>.
    Found 1-bit register for signal <sent_row_lcl>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <mig_7series_v1_8_arb_row_col> synthesized.

Synthesizing Unit <mig_7series_v1_8_round_robin_arb_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_round_robin_arb.v".
        TCQ = 100
        WIDTH = 4
    Found 4-bit register for signal <last_master_r>.
    Found 4-bit register for signal <grant_r>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <mig_7series_v1_8_round_robin_arb_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_arb_select>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_arb_select.v".
        TCQ = 100
        EVEN_CWL_2T_MODE = "OFF"
        ADDR_CMD_MODE = "1T"
        BANK_VECT_INDX = 11
        BANK_WIDTH = 3
        BURST_MODE = "8"
        CS_WIDTH = 1
        CL = 9
        CWL = 7
        DATA_BUF_ADDR_VECT_INDX = 19
        DATA_BUF_ADDR_WIDTH = 5
        DRAM_TYPE = "DDR3"
        EARLY_WR_DATA_ADDR = "OFF"
        ECC = "OFF"
        nBANK_MACHS = 4
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        CKE_ODT_AUX = "FALSE"
        nSLOTS = 1
        RANKS = 1
        RANK_VECT_INDX = 3
        RANK_WIDTH = 1
        ROW_VECT_INDX = 59
        ROW_WIDTH = 15
        RTT_NOM = "60"
        RTT_WR = "OFF"
        SLOT_0_CONFIG = 8'b00001111
        SLOT_1_CONFIG = 8'b00000000
WARNING:Xst:647 - Input <grant_col_wr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slot_1_present> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <init_calib_complete> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'col_cmd_r', unconnected in block 'mig_7series_v1_8_arb_select', is tied to its initial value (0000000000000000000000).
WARNING:Xst:2935 - Signal 'row_cmd_r', unconnected in block 'mig_7series_v1_8_arb_select', is tied to its initial value (0000000000000000000000).
WARNING:Xst:653 - Signal <col_mux.col_row_r> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <col_mux.col_periodic_rd_r>.
    Found 1-bit register for signal <col_mux.col_rmw_r>.
    Found 1-bit register for signal <col_mux.col_size_r>.
    Found 5-bit register for signal <col_mux.col_data_buf_addr_r>.
    Found 1-bit register for signal <col_rd_wr_r>.
    Found 1-bit register for signal <rnk_config_r>.
    Found 1-bit register for signal <cke_r>.
    Found 1-bit register for signal <mc_aux_out_r<0>>.
    Found 1-bit register for signal <mc_aux_out_r_1<0>>.
    Found 7-bit adder for signal <n0293[6:0]> created at line 291.
    Found 7-bit adder for signal <n0295[6:0]> created at line 295.
    Found 7-bit adder for signal <n0298[6:0]> created at line 299.
    Found 7-bit adder for signal <n0301[6:0]> created at line 307.
    Found 1-bit shifter logical left for signal <cs_one_hot[0]_ra0[0]_shift_left_70_OUT<0>> created at line 579
    Found 1-bit shifter logical left for signal <cs_one_hot[0]_ra1[0]_shift_left_71_OUT<0>> created at line 581
    Found 1-bit shifter logical left for signal <cs_one_hot[0]_ra2[0]_shift_left_72_OUT<0>> created at line 587
    Found 1-bit shifter logical left for signal <cs_one_hot[0]_ra3[0]_shift_left_73_OUT<0>> created at line 590
    Found 1-bit shifter logical left for signal <col_ra_one_hot> created at line 615
    WARNING:Xst:2404 -  FFs/Latches <mc_aux_out_r<1:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_arb_select>.
    WARNING:Xst:2404 -  FFs/Latches <mc_aux_out_r_1<1:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_arb_select>.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  13 D-type flip-flop(s).
	inferred  63 Multiplexer(s).
	inferred   5 Combinational logic shifter(s).
Unit <mig_7series_v1_8_arb_select> synthesized.

Synthesizing Unit <mig_7series_v1_8_col_mach>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/controller/mig_7series_v1_8_col_mach.v".
        TCQ = 100
        BANK_WIDTH = 3
        BURST_MODE = "8"
        COL_WIDTH = 10
        CS_WIDTH = 1
        DATA_BUF_ADDR_WIDTH = 5
        DATA_BUF_OFFSET_WIDTH = 1
        DELAY_WR_DATA_CNTRL = 1
        DQS_WIDTH = 4
        DRAM_TYPE = "DDR3"
        EARLY_WR_DATA_ADDR = "OFF"
        ECC = "OFF"
        MC_ERR_ADDR_WIDTH = 29
        nCK_PER_CLK = 4
        nPHY_WRLAT = 2
        RANK_WIDTH = 1
        ROW_WIDTH = 15
    Set property "syn_maxfan = 10" for signal <rd_data_en>.
    Set property "KEEP = TRUE" for signal <rd_data_en>.
    Set property "MAX_FANOUT = 10" for signal <rd_data_en>.
WARNING:Xst:647 - Input <col_ra> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <col_ba> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <col_row> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <col_a> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <col_size> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <col_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'offset_r', unconnected in block 'mig_7series_v1_8_col_mach', is tied to its initial value (00).
WARNING:Xst:2935 - Signal 'dq_busy_data', unconnected in block 'mig_7series_v1_8_col_mach', is tied to its initial value (0).
    Found 1-bit register for signal <col_rd_wr_r1>.
    Found 1-bit register for signal <col_rd_wr_r2>.
    Found 1-bit register for signal <sent_col_r1>.
    Found 1-bit register for signal <sent_col_r2>.
    Found 5-bit register for signal <delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r>.
    Found 5-bit register for signal <read_fifo.head_r>.
    Found 5-bit register for signal <read_fifo.tail_r>.
    Found 8-bit register for signal <read_fifo.fifo_out_data_r<7:0>>.
    Found 5-bit adder for signal <read_fifo.head_r[4]_GND_45_o_add_15_OUT> created at line 351.
    Found 5-bit adder for signal <read_fifo.tail_r[4]_GND_45_o_add_20_OUT> created at line 358.
    Found 5-bit comparator equal for signal <col_read_fifo_empty> created at line 362
    WARNING:Xst:2404 -  FFs/Latches <offset_r1<0><0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_col_mach>.
    WARNING:Xst:2404 -  FFs/Latches <offset_r2<0><0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_col_mach>.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <mig_7series_v1_8_col_mach> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_top>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v".
        TCQ = 100
        AL = "0"
        BANK_WIDTH = 3
        BURST_MODE = "8"
        BURST_TYPE = "SEQ"
        CA_MIRROR = "OFF"
        CK_WIDTH = 1
        CL = 9
        COL_WIDTH = 10
        CS_WIDTH = 1
        CKE_WIDTH = 1
        CWL = 7
        DM_WIDTH = 4
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_TYPE = "DDR3"
        DRAM_WIDTH = 8
        MASTER_PHY_CTL = 1
        LP_DDR_CK_WIDTH = 2
        PHYCTL_CMD_FIFO = "FALSE"
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        PHY_0_BITLANES = 48'b001111111110001111111110001111111110001011111111
        PHY_1_BITLANES = 48'b001111111111111111111111110000000000000000000000
        PHY_2_BITLANES = 48'b000000000000000000000000000000000000000000000000
        CK_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
        ADDR_MAP = 192'b000000000000000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011
        BANK_MAP = 36'b000100101010000100100101000100100100
        CAS_MAP = 12'b000100100010
        CKE_ODT_BYTE_MAP = 8'b00000000
        CKE_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
        ODT_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
        CKE_ODT_AUX = "FALSE"
        CS_MAP = 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000
        PARITY_MAP = 12'b000000000000
        RAS_MAP = 12'b000100100011
        WE_MAP = 12'b000100100001
        DQS_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
        DATA0_MAP = 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
        DATA1_MAP = 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
        DATA2_MAP = 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
        DATA3_MAP = 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
        DATA4_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA5_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA6_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA7_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA8_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA9_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA10_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA11_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA12_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA13_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA14_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA15_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA16_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA17_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        MASK0_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
        MASK1_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        PRE_REV3ES = "OFF"
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        ADDR_CMD_MODE = "1T"
        IODELAY_HP_MODE = "ON"
        BANK_TYPE = "HP_IO"
        DATA_IO_PRIM_TYPE = "HP_LP"
        DATA_IO_IDLE_PWRDWN = "ON"
        IODELAY_GRP = "IODELAY_MIG"
        IBUF_LPWR_MODE = "OFF"
        OUTPUT_DRV = "HIGH"
        REG_CTRL = "OFF"
        RTT_NOM = "60"
        RTT_WR = "OFF"
        tCK = 1666
        tRFC = 300000
        DDR2_DQSN_ENABLE = "YES"
        WRLVL = "ON"
        DEBUG_PORT = "ON"
        RANKS = 1
        ODT_WIDTH = 1
        ROW_WIDTH = 15
        SLOT_1_CONFIG = 8'b00000000
        CALIB_ROW_ADD = 16'b0000000000000000
        CALIB_COL_ADD = 12'b000000000000
        CALIB_BA_ADD = 3'b000
        SIM_BYPASS_INIT_CAL = "OFF"
        REFCLK_FREQ = 200.000000
        USE_CS_PORT = 1
        USE_DM_PORT = 1
        USE_ODT_PORT = 1
        RD_PATH_REG = 0
    Set property "KEEP = TRUE" for signal <if_empty>.
    Set property "MAX_FANOUT = 10" for signal <if_empty>.
    Set property "KEEP = TRUE" for signal <calib_in_common>.
    Set property "MAX_FANOUT = 10" for signal <calib_in_common>.
    Set property "KEEP = TRUE" for signal <phy_rddata_valid_w>.
    Set property "MAX_FANOUT = 3" for signal <phy_rddata_valid_w>.
    Set property "syn_maxfan = 3" for signal <phy_rddata_valid_w>.
WARNING:Xst:2898 - Port 'po_counter_load_val', unconnected in block instance 'u_ddr_mc_phy_wrapper', is tied to GND.
WARNING:Xst:647 - Input <mc_aux_out0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mc_aux_out1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mc_rank_cnt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" line 939: Output port <phy_data_full> of the instance <u_ddr_mc_phy_wrapper> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" line 939: Output port <pi_dqs_out_of_range> of the instance <u_ddr_mc_phy_wrapper> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" line 1112: Output port <calib_aux_out> of the instance <u_ddr_calib_top> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" line 1112: Output port <calib_rank_cnt> of the instance <u_ddr_calib_top> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" line 1112: Output port <dlyval_dq> of the instance <u_ddr_calib_top> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.v" line 1112: Output port <calib_writes> of the instance <u_ddr_calib_top> is unconnected or connected to loadless signal.
    WARNING:Xst:2404 -  FFs/Latches <parity<3:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_top>.
    Summary:
	inferred  18 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_phy_top> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_mc_phy_wrapper>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v".
        TCQ = 100
        tCK = 1666
        BANK_TYPE = "HP_IO"
        DATA_IO_PRIM_TYPE = "HP_LP"
        DATA_IO_IDLE_PWRDWN = "ON"
        IODELAY_GRP = "IODELAY_MIG"
        nCK_PER_CLK = 4
        nCS_PER_RANK = 1
        BANK_WIDTH = 3
        CKE_WIDTH = 1
        CS_WIDTH = 1
        CK_WIDTH = 1
        CWL = 7
        DDR2_DQSN_ENABLE = "YES"
        DM_WIDTH = 4
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_TYPE = "DDR3"
        RANKS = 1
        ODT_WIDTH = 1
        REG_CTRL = "OFF"
        ROW_WIDTH = 15
        USE_CS_PORT = 1
        USE_DM_PORT = 1
        USE_ODT_PORT = 1
        IBUF_LPWR_MODE = "OFF"
        LP_DDR_CK_WIDTH = 2
        PHYCTL_CMD_FIFO = "FALSE"
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        PHY_0_BITLANES = 48'b001111111110001111111110001111111110001011111111
        PHY_1_BITLANES = 48'b001111111111111111111111110000000000000000000000
        PHY_2_BITLANES = 48'b000000000000000000000000000000000000000000000000
        HIGHEST_BANK = 2
        HIGHEST_LANE = 8
        CK_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
        ADDR_MAP = 192'b000000000000000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100110000000100101001000100101000000100100111000100100110000100101011
        BANK_MAP = 36'b000100101010000100100101000100100100
        CAS_MAP = 12'b000100100010
        CKE_ODT_BYTE_MAP = 8'b00000000
        CKE_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
        ODT_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
        CKE_ODT_AUX = "FALSE"
        CS_MAP = 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000
        PARITY_MAP = 12'b000000000000
        RAS_MAP = 12'b000100100011
        WE_MAP = 12'b000100100001
        DQS_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
        DATA0_MAP = 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
        DATA1_MAP = 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
        DATA2_MAP = 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
        DATA3_MAP = 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
        DATA4_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA5_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA6_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA7_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA8_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA9_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA10_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA11_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA12_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA13_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA14_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA15_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA16_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        DATA17_MAP = 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        MASK0_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
        MASK1_MAP = 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
        SIM_CAL_OPTION = "NONE"
        MASTER_PHY_CTL = 1
    Set property "KEEP = TRUE" for signal <phy_ctl_wr_of>.
    Set property "MAX_FANOUT = 1" for signal <phy_ctl_wr_of>.
WARNING:Xst:2898 - Port 'auxout_clk', unconnected in block instance 'u_ddr_mc_phy', is tied to GND.
WARNING:Xst:2898 - Port 'idelayctrl_refclk', unconnected in block instance 'u_ddr_mc_phy', is tied to GND.
WARNING:Xst:2898 - Port 'cke_in', unconnected in block instance 'u_ddr_mc_phy', is tied to GND.
WARNING:Xst:2898 - Port 'input_sink', unconnected in block instance 'u_ddr_mc_phy', is tied to GND.
WARNING:Xst:647 - Input <mux_odt<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <parity_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelayctrl_refclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_init_data_sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_phaser_ref> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1299: Output port <d_out> of the instance <phy_ctl_pre_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1299: Output port <wr_en_out> of the instance <phy_ctl_pre_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1299: Output port <afull> of the instance <phy_ctl_pre_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <aux_out> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <if_a_empty> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <if_empty_or> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <if_empty_and> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <of_ctl_a_full> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <of_data_a_full> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <of_data_full> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <phy_ctl_a_full> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <phy_ctl_ready> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <rst_out> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <po_coarse_overflow> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <po_fine_overflow> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <pi_fine_overflow> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v" line 1414: Output port <pi_dqs_found> of the instance <u_ddr_mc_phy> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <mem_dqs_in<7:4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_dq_in<79:39>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_dq_in<30:29>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_dq_in<20:19>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_dq_in<10:8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<639:636>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<631:628>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<623:620>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<615:612>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<607:604>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<599:596>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<591:588>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<583:580>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<575:572>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<567:564>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<559:556>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<551:548>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<543:540>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<519:516>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<511:508>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<503:500>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<495:492>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<487:484>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<479:456>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<451:448>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<443:320>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<247:240>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<167:160>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<87:80>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_dout<71:64>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <phy_data_full> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <phy_ctl_wr_i1>.
    Found 32-bit register for signal <phy_ctl_wd_i2>.
    Found 1-bit register for signal <phy_ctl_wr_i2>.
    Found 6-bit register for signal <data_offset_1_i1>.
    Found 6-bit register for signal <data_offset_1_i2>.
    Found 6-bit register for signal <data_offset_2_i1>.
    Found 6-bit register for signal <data_offset_2_i2>.
    Found 32-bit register for signal <phy_ctl_wd_i1>.
    Summary:
	inferred  90 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_mc_phy_wrapper> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_of_pre_fifo_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v".
        TCQ = 25
        DEPTH = 8
        WIDTH = 44
    Set property "KEEP = TRUE" for signal <my_empty>.
    Set property "MAX_FANOUT = 3" for signal <my_empty>.
    Set property "KEEP = TRUE" for signal <my_full>.
    Set property "MAX_FANOUT = 3" for signal <my_full>.
    Set property "KEEP = TRUE" for signal <rd_ptr>.
    Set property "MAX_FANOUT = 10" for signal <rd_ptr>.
    Set property "KEEP = TRUE" for signal <wr_ptr>.
    Set property "MAX_FANOUT = 10" for signal <wr_ptr>.
    Set property "syn_ramstyle = registers" for signal <mem>.
INFO:Xst:3018 - HDL ADVISOR - 352 flip-flops were inferred for signal <mem> because the macro Ram extraction is invalidated. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Found 3-bit register for signal <my_empty>.
    Found 3-bit register for signal <wr_ptr>.
    Found 3-bit register for signal <my_full>.
    Found 4-bit register for signal <entry_cnt>.
    Found 3-bit register for signal <rd_ptr>.
    Found 44-bit register for signal <mem_ff_0>.
    Found 44-bit register for signal <mem_ff_1>.
    Found 44-bit register for signal <mem_ff_2>.
    Found 44-bit register for signal <mem_ff_3>.
    Found 44-bit register for signal <mem_ff_4>.
    Found 44-bit register for signal <mem_ff_5>.
    Found 44-bit register for signal <mem_ff_6>.
    Found 44-bit register for signal <mem_ff_7>.
    Found 4-bit subtractor for signal <entry_cnt[3]_GND_53_o_sub_33_OUT> created at line 182.
    Found 3-bit adder for signal <nxt_rd_ptr> created at line 129.
    Found 3-bit adder for signal <nxt_wr_ptr> created at line 152.
    Found 4-bit adder for signal <entry_cnt[3]_GND_53_o_add_31_OUT> created at line 180.
    Found 44-bit 8-to-1 multiplexer for signal <mem_out> created at line 116.
    Found 3-bit comparator equal for signal <nxt_rd_ptr[2]_wr_ptr[2]_equal_13_o> created at line 148
    Found 3-bit comparator equal for signal <nxt_wr_ptr[2]_rd_ptr[2]_equal_26_o> created at line 171
    Found 4-bit comparator lessequal for signal <n0059> created at line 185
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 368 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_mc_phy>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v".
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        RCLK_SELECT_BANK = 1
        RCLK_SELECT_LANE = "B"
        RCLK_SELECT_EDGE = 4'b1111
        GENERATE_DDR_CK_MAP = 16'b0011000101000100
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000001000000000000000000000000000
        USE_PRE_POST_FIFO = "TRUE"
        SYNTHESIS = "TRUE"
        PO_CTL_COARSE_BYPASS = "FALSE"
        PI_SEL_CLK_OFFSET = 6
        PHYCTL_CMD_FIFO = "FALSE"
        PHY_CLK_RATIO = 4
        PHY_FOUR_WINDOW_CLOCKS = 63
        PHY_EVENTS_DELAY = 18
        PHY_COUNT_EN = "FALSE"
        PHY_SYNC_MODE = "FALSE"
        PHY_DISABLE_SEQ_MATCH = "TRUE"
        MASTER_PHY_CTL = 1
        PHY_0_BITLANES = 48'b001111111110001111111110001111111110001011111111
        PHY_0_BITLANES_OUTONLY = 48'b001000000000001000000000001000000000001000000000
        PHY_0_LANE_REMAP = 16'b0011001000010000
        PHY_0_GENERATE_IDELAYCTRL = "FALSE"
        PHY_0_IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        NUM_DDR_CK = 1
        PHY_0_DATA_CTL = 4'b1111
        PHY_0_CMD_OFFSET = 8
        PHY_0_RD_CMD_OFFSET_0 = 10
        PHY_0_RD_CMD_OFFSET_1 = 10
        PHY_0_RD_CMD_OFFSET_2 = 10
        PHY_0_RD_CMD_OFFSET_3 = 10
        PHY_0_RD_DURATION_0 = 6
        PHY_0_RD_DURATION_1 = 6
        PHY_0_RD_DURATION_2 = 6
        PHY_0_RD_DURATION_3 = 6
        PHY_0_WR_CMD_OFFSET_0 = 8
        PHY_0_WR_CMD_OFFSET_1 = 8
        PHY_0_WR_CMD_OFFSET_2 = 8
        PHY_0_WR_CMD_OFFSET_3 = 8
        PHY_0_WR_DURATION_0 = 7
        PHY_0_WR_DURATION_1 = 7
        PHY_0_WR_DURATION_2 = 7
        PHY_0_WR_DURATION_3 = 7
        PHY_0_AO_WRLVL_EN = 0
        PHY_0_AO_TOGGLE = 4'b0001
        PHY_0_OF_ALMOST_FULL_VALUE = 1
        PHY_0_IF_ALMOST_EMPTY_VALUE = 1
        PHY_0_A_PI_FREQ_REF_DIV = "NONE"
        PHY_0_A_PI_CLKOUT_DIV = 2
        PHY_0_A_PO_CLKOUT_DIV = 2
        PHY_0_A_BURST_MODE = "TRUE"
        PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PHY_0_A_PO_OCLK_DELAY = 30
        PHY_0_B_PO_OCLK_DELAY = 30
        PHY_0_C_PO_OCLK_DELAY = 30
        PHY_0_D_PO_OCLK_DELAY = 30
        PHY_0_A_PO_OCLKDELAY_INV = "TRUE"
        PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_B_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_C_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_D_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_B_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_C_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_D_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_0_B_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_0_B_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_0_C_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_0_C_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_0_D_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_0_D_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_0_A_IDELAYE2_IDELAY_VALUE = 0
        PHY_0_B_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_0_B_IDELAYE2_IDELAY_VALUE = 0
        PHY_0_C_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_0_C_IDELAYE2_IDELAY_VALUE = 0
        PHY_0_D_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_0_D_IDELAYE2_IDELAY_VALUE = 0
        PHY_1_BITLANES = 48'b001111111111111111111111110000000000000000000000
        PHY_1_BITLANES_OUTONLY = 48'b000000000000000000000000000000000000000000000000
        PHY_1_LANE_REMAP = 16'b0011001000010000
        PHY_1_GENERATE_IDELAYCTRL = "FALSE"
        PHY_1_IODELAY_GRP = "IODELAY_MIG"
        PHY_1_DATA_CTL = 4'b0000
        PHY_1_CMD_OFFSET = 8
        PHY_1_RD_CMD_OFFSET_0 = 10
        PHY_1_RD_CMD_OFFSET_1 = 10
        PHY_1_RD_CMD_OFFSET_2 = 10
        PHY_1_RD_CMD_OFFSET_3 = 10
        PHY_1_RD_DURATION_0 = 6
        PHY_1_RD_DURATION_1 = 6
        PHY_1_RD_DURATION_2 = 6
        PHY_1_RD_DURATION_3 = 6
        PHY_1_WR_CMD_OFFSET_0 = 8
        PHY_1_WR_CMD_OFFSET_1 = 8
        PHY_1_WR_CMD_OFFSET_2 = 8
        PHY_1_WR_CMD_OFFSET_3 = 8
        PHY_1_WR_DURATION_0 = 7
        PHY_1_WR_DURATION_1 = 7
        PHY_1_WR_DURATION_2 = 7
        PHY_1_WR_DURATION_3 = 7
        PHY_1_AO_WRLVL_EN = 0
        PHY_1_AO_TOGGLE = 4'b0001
        PHY_1_OF_ALMOST_FULL_VALUE = 1
        PHY_1_IF_ALMOST_EMPTY_VALUE = 1
        PHY_1_A_PI_FREQ_REF_DIV = "NONE"
        PHY_1_A_PI_CLKOUT_DIV = 2
        PHY_1_A_PO_CLKOUT_DIV = 2
        PHY_1_A_BURST_MODE = "TRUE"
        PHY_1_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PHY_1_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PHY_1_A_PO_OCLK_DELAY = 30
        PHY_1_B_PO_OCLK_DELAY = 30
        PHY_1_C_PO_OCLK_DELAY = 30
        PHY_1_D_PO_OCLK_DELAY = 30
        PHY_1_A_PO_OCLKDELAY_INV = "TRUE"
        PHY_1_A_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_1_A_IDELAYE2_IDELAY_VALUE = 0
        PHY_1_B_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_1_B_IDELAYE2_IDELAY_VALUE = 0
        PHY_1_C_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_1_C_IDELAYE2_IDELAY_VALUE = 0
        PHY_1_D_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_1_D_IDELAYE2_IDELAY_VALUE = 0
        PHY_1_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_B_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_C_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_D_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_B_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_C_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_D_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_1_A_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_1_A_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_1_B_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_1_B_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_1_C_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_1_C_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_1_D_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_1_D_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_2_BITLANES = 48'b000000000000000000000000000000000000000000000000
        PHY_2_BITLANES_OUTONLY = 48'b000000000000000000000000000000000000000000000000
        PHY_2_LANE_REMAP = 16'b0011001000010000
        PHY_2_GENERATE_IDELAYCTRL = "FALSE"
        PHY_2_IODELAY_GRP = "IODELAY_MIG"
        PHY_2_DATA_CTL = 4'b0000
        PHY_2_CMD_OFFSET = 8
        PHY_2_RD_CMD_OFFSET_0 = 10
        PHY_2_RD_CMD_OFFSET_1 = 10
        PHY_2_RD_CMD_OFFSET_2 = 10
        PHY_2_RD_CMD_OFFSET_3 = 10
        PHY_2_RD_DURATION_0 = 6
        PHY_2_RD_DURATION_1 = 6
        PHY_2_RD_DURATION_2 = 6
        PHY_2_RD_DURATION_3 = 6
        PHY_2_WR_CMD_OFFSET_0 = 8
        PHY_2_WR_CMD_OFFSET_1 = 8
        PHY_2_WR_CMD_OFFSET_2 = 8
        PHY_2_WR_CMD_OFFSET_3 = 8
        PHY_2_WR_DURATION_0 = 7
        PHY_2_WR_DURATION_1 = 7
        PHY_2_WR_DURATION_2 = 7
        PHY_2_WR_DURATION_3 = 7
        PHY_2_AO_WRLVL_EN = 0
        PHY_2_AO_TOGGLE = 4'b0001
        PHY_2_OF_ALMOST_FULL_VALUE = 1
        PHY_2_IF_ALMOST_EMPTY_VALUE = 1
        PHY_2_A_PI_FREQ_REF_DIV = "NONE"
        PHY_2_A_PI_CLKOUT_DIV = 2
        PHY_2_A_PO_CLKOUT_DIV = 2
        PHY_2_A_BURST_MODE = "TRUE"
        PHY_2_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PHY_2_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PHY_2_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_B_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_C_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_D_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_B_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_C_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_D_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        PHY_2_A_PO_OCLK_DELAY = 30
        PHY_2_B_PO_OCLK_DELAY = 30
        PHY_2_C_PO_OCLK_DELAY = 30
        PHY_2_D_PO_OCLK_DELAY = 30
        PHY_2_A_PO_OCLKDELAY_INV = "TRUE"
        PHY_2_A_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_2_A_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_2_B_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_2_B_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_2_C_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_2_C_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_2_D_OSERDES_DATA_RATE = "UNDECLARED"
        PHY_2_D_OSERDES_DATA_WIDTH = "UNDECLARED"
        PHY_2_A_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_2_A_IDELAYE2_IDELAY_VALUE = 0
        PHY_2_B_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_2_B_IDELAYE2_IDELAY_VALUE = 0
        PHY_2_C_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_2_C_IDELAYE2_IDELAY_VALUE = 0
        PHY_2_D_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        PHY_2_D_IDELAYE2_IDELAY_VALUE = 0
        PHY_0_IS_LAST_BANK = "FALSE"
        PHY_1_IS_LAST_BANK = "FALSE"
        PHY_2_IS_LAST_BANK = "FALSE"
        TCK = 1666
        N_LANES = 32'b00000000000000000000000000000111
        HIGHEST_BANK = 2
        HIGHEST_LANE_B0 = 4
        HIGHEST_LANE_B1 = 4
        HIGHEST_LANE_B2 = 0
        HIGHEST_LANE_B3 = 0
        HIGHEST_LANE_B4 = 0
        HIGHEST_LANE = 8
        LP_DDR_CK_WIDTH = 2
        GENERATE_SIGNAL_SPLIT = "FALSE"
        CKE_ODT_AUX = "FALSE"
    Set property "IOB = FORCE" for signal <aux_out<7>>.
    Set property "IOB = FORCE" for signal <aux_out<6>>.
    Set property "IOB = FORCE" for signal <aux_out<5>>.
    Set property "IOB = FORCE" for signal <aux_out<4>>.
    Set property "IOB = FORCE" for signal <aux_out<3>>.
    Set property "IOB = FORCE" for signal <aux_out<2>>.
    Set property "IOB = FORCE" for signal <aux_out<1>>.
    Set property "IOB = FORCE" for signal <aux_out<0>>.
    Set property "syn_maxfan = 20" for signal <if_empty>.
    Set property "KEEP = TRUE" for signal <if_empty>.
    Set property "MAX_FANOUT = 20" for signal <if_empty>.
WARNING:Xst:647 - Input <aux_in_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aux_in_2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <data_offset_2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <calib_sel<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <po_fine_enable<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <po_coarse_enable<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <po_fine_inc<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <po_coarse_inc<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <po_sel_fine_oclk_delay<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cke_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1085: Output port <ddr_clk> of the instance <ddr_phy_4lanes_0.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1085: Output port <rclk> of the instance <ddr_phy_4lanes_0.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1085: Output port <phy_ctl_empty> of the instance <ddr_phy_4lanes_0.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1085: Output port <rst_out> of the instance <ddr_phy_4lanes_0.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1085: Output port <pi_dqs_found_all> of the instance <ddr_phy_4lanes_0.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1085: Output port <pi_dqs_found_any> of the instance <ddr_phy_4lanes_0.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1335: Output port <rclk> of the instance <ddr_phy_4lanes_1.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1335: Output port <pi_dqs_found_all> of the instance <ddr_phy_4lanes_1.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy.v" line 1335: Output port <pi_dqs_found_any> of the instance <ddr_phy_4lanes_1.u_ddr_phy_4lanes> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <pi_fine_overflow_w<2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <rst_auxout_rr>.
    Found 1-bit register for signal <rst_auxout>.
    Found 1-bit register for signal <rst_auxout_r>.
    Found 16-bit register for signal <mcGo_r>.
    Found 1-bit register for signal <aux_out<2>>.
    Found 1-bit register for signal <aux_out<0>>.
    Found 1-bit register for signal <aux_out<3>>.
    Found 1-bit register for signal <aux_out<1>>.
    Found 1-bit register for signal <aux_out<6>>.
    Found 1-bit register for signal <aux_out<4>>.
    Found 1-bit register for signal <aux_out<7>>.
    Found 1-bit register for signal <aux_out<5>>.
    Found 1-bit 3-to-1 multiplexer for signal <_n0202> created at line 391.
    Found 1-bit 3-to-1 multiplexer for signal <_n0209> created at line 392.
    Found 1-bit 4-to-1 multiplexer for signal <_n0216> created at line 402.
    Found 1-bit 3-to-1 multiplexer for signal <_n0223> created at line 412.
    Found 1-bit 4-to-1 multiplexer for signal <_n0230> created at line 405.
    Found 9-bit 3-to-1 multiplexer for signal <_n0237> created at line 393.
    Found 6-bit 3-to-1 multiplexer for signal <_n0244> created at line 403.
    Found 1-bit 4-to-1 multiplexer for signal <_n0251> created at line 407.
    Summary:
	inferred  27 D-type flip-flop(s).
	inferred  20 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_mc_phy> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_4lanes_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v".
        GENERATE_IDELAYCTRL = "FALSE"
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000000000
        NUM_DDR_CK = 1
        BYTE_LANES = 4'b1111
        DATA_CTL_N = 4'b1111
        BITLANES = 48'b001111111110001111111110001111111110001011111111
        BITLANES_OUTONLY = 48'b001000000000001000000000001000000000001000000000
        LANE_REMAP = 16'b0011001000010000
        LAST_BANK = "FALSE"
        USE_PRE_POST_FIFO = "TRUE"
        RCLK_SELECT_LANE = "B"
        TCK = 1666
        SYNTHESIS = "TRUE"
        PO_CTL_COARSE_BYPASS = "FALSE"
        PO_FINE_DELAY = 60
        PI_SEL_CLK_OFFSET = 6
        PC_CLK_RATIO = 4
        A_PI_FREQ_REF_DIV = "NONE"
        A_PI_CLKOUT_DIV = 2
        A_PI_BURST_MODE = "TRUE"
        A_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        A_PI_FINE_DELAY = 33
        A_PI_SYNC_IN_DIV_RST = "TRUE"
        B_PI_FREQ_REF_DIV = "NONE"
        B_PI_CLKOUT_DIV = 2
        B_PI_BURST_MODE = "TRUE"
        B_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        B_PI_FINE_DELAY = 33
        B_PI_SYNC_IN_DIV_RST = "TRUE"
        C_PI_FREQ_REF_DIV = "NONE"
        C_PI_CLKOUT_DIV = 2
        C_PI_BURST_MODE = "TRUE"
        C_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        C_PI_FINE_DELAY = 33
        C_PI_SYNC_IN_DIV_RST = "TRUE"
        D_PI_FREQ_REF_DIV = "NONE"
        D_PI_CLKOUT_DIV = 2
        D_PI_BURST_MODE = "TRUE"
        D_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        D_PI_FINE_DELAY = 33
        D_PI_SYNC_IN_DIV_RST = "TRUE"
        A_PO_CLKOUT_DIV = 2
        A_PO_FINE_DELAY = 60
        A_PO_COARSE_DELAY = 0
        A_PO_OCLK_DELAY = 30
        A_PO_OCLKDELAY_INV = "TRUE"
        A_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        A_PO_SYNC_IN_DIV_RST = "TRUE"
        B_PO_CLKOUT_DIV = 2
        B_PO_FINE_DELAY = 60
        B_PO_COARSE_DELAY = 0
        B_PO_OCLK_DELAY = 30
        B_PO_OCLKDELAY_INV = "TRUE"
        B_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        B_PO_SYNC_IN_DIV_RST = "TRUE"
        C_PO_CLKOUT_DIV = 2
        C_PO_FINE_DELAY = 60
        C_PO_COARSE_DELAY = 0
        C_PO_OCLK_DELAY = 30
        C_PO_OCLKDELAY_INV = "TRUE"
        C_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        C_PO_SYNC_IN_DIV_RST = "TRUE"
        D_PO_CLKOUT_DIV = 2
        D_PO_FINE_DELAY = 60
        D_PO_COARSE_DELAY = 0
        D_PO_OCLK_DELAY = 30
        D_PO_OCLKDELAY_INV = "TRUE"
        D_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        D_PO_SYNC_IN_DIV_RST = "TRUE"
        A_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        A_IDELAYE2_IDELAY_VALUE = 0
        B_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        B_IDELAYE2_IDELAY_VALUE = 0
        C_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        C_IDELAYE2_IDELAY_VALUE = 0
        D_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        D_IDELAYE2_IDELAY_VALUE = 0
        PC_BURST_MODE = "TRUE"
        PC_DATA_CTL_N = 4'b1111
        PC_CMD_OFFSET = 8
        PC_RD_CMD_OFFSET_0 = 10
        PC_RD_CMD_OFFSET_1 = 10
        PC_RD_CMD_OFFSET_2 = 10
        PC_RD_CMD_OFFSET_3 = 10
        PC_CO_DURATION = 1
        PC_DI_DURATION = 1
        PC_DO_DURATION = 1
        PC_RD_DURATION_0 = 6
        PC_RD_DURATION_1 = 6
        PC_RD_DURATION_2 = 6
        PC_RD_DURATION_3 = 6
        PC_WR_CMD_OFFSET_0 = 8
        PC_WR_CMD_OFFSET_1 = 8
        PC_WR_CMD_OFFSET_2 = 8
        PC_WR_CMD_OFFSET_3 = 8
        PC_WR_DURATION_0 = 7
        PC_WR_DURATION_1 = 7
        PC_WR_DURATION_2 = 7
        PC_WR_DURATION_3 = 7
        PC_AO_WRLVL_EN = 0
        PC_AO_TOGGLE = 4'b0001
        PC_FOUR_WINDOW_CLOCKS = 63
        PC_EVENTS_DELAY = 18
        PC_PHY_COUNT_EN = "FALSE"
        PC_SYNC_MODE = "FALSE"
        PC_DISABLE_SEQ_MATCH = "TRUE"
        PC_MULTI_REGION = "TRUE"
        A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        B_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        C_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        D_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_OUTPUT_DISABLE = "TRUE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        A_OS_DATA_RATE = "UNDECLARED"
        A_OS_DATA_WIDTH = "UNDECLARED"
        B_OS_DATA_RATE = "UNDECLARED"
        B_OS_DATA_WIDTH = "UNDECLARED"
        C_OS_DATA_RATE = "UNDECLARED"
        C_OS_DATA_WIDTH = "UNDECLARED"
        D_OS_DATA_RATE = "UNDECLARED"
        D_OS_DATA_WIDTH = "UNDECLARED"
        A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        B_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        C_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        D_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_SYNCHRONOUS_MODE = "FALSE"
        HIGHEST_LANE = 4
        N_CTL_LANES = 32'b00000000000000000000000000000000
        N_BYTE_LANES = 32'b00000000000000000000000000000100
        N_DATA_LANES = 32'b00000000000000000000000000000100
        AUXOUT_WIDTH = 4
        LP_DDR_CK_WIDTH = 2
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <A_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <A_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <A_po_fine_inc>.
    Set property "syn_maxfan = 3" for signal <B_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <B_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <B_po_fine_inc>.
    Set property "syn_maxfan = 3" for signal <C_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <C_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <C_po_fine_inc>.
    Set property "syn_maxfan = 3" for signal <D_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <D_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <D_po_fine_inc>.
WARNING:Xst:647 - Input <phy_ctl_wd<22:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mem_refclk_div4> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <input_sink> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <calib_zero_ctrl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 938: Output port <rclk> of the instance <ddr_byte_lane_A.ddr_byte_lane_A> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 938: Output port <if_a_full> of the instance <ddr_byte_lane_A.ddr_byte_lane_A> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 938: Output port <if_full> of the instance <ddr_byte_lane_A.ddr_byte_lane_A> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 938: Output port <of_a_empty> of the instance <ddr_byte_lane_A.ddr_byte_lane_A> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 938: Output port <of_empty> of the instance <ddr_byte_lane_A.ddr_byte_lane_A> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 938: Output port <pi_iserdes_rst> of the instance <ddr_byte_lane_A.ddr_byte_lane_A> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <if_a_full> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <if_full> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <of_a_empty> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <of_empty> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <pi_iserdes_rst> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <rclk> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <if_a_full> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <if_full> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <of_a_empty> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <of_empty> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <pi_iserdes_rst> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <rclk> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <if_a_full> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <if_full> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <of_a_empty> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <of_empty> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <pi_iserdes_rst> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
    Register <D_rst_primitives> equivalent to <A_rst_primitives> has been removed
    Register <C_rst_primitives> equivalent to <A_rst_primitives> has been removed
    Register <B_rst_primitives> equivalent to <A_rst_primitives> has been removed
    Found 1-bit register for signal <rst_out>.
    Found 1-bit register for signal <rst_primitives>.
    Found 1-bit register for signal <A_rst_primitives>.
    Found 31-bit register for signal <rclk_delay<30:0>>.
    Found 1-bit register for signal <mcGo>.
    Found 1-bit register for signal <po_coarse_overflow>.
    Found 1-bit register for signal <po_fine_overflow>.
    Found 9-bit register for signal <po_counter_read_val>.
    Found 1-bit register for signal <pi_fine_overflow>.
    Found 6-bit register for signal <pi_counter_read_val>.
    Found 1-bit register for signal <pi_phase_locked>.
    Found 1-bit register for signal <pi_dqs_found>.
    Found 1-bit register for signal <pi_dqs_out_of_range>.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_po_coarse_overflow_Mux_21_o> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_po_fine_overflow_Mux_22_o> created at line 1493.
    Found 9-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_po_counter_read_val[8]_wide_mux_23_OUT> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_fine_overflow_Mux_24_o> created at line 1493.
    Found 6-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_counter_read_val[5]_wide_mux_25_OUT> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_phase_locked_Mux_26_o> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_dqs_found_Mux_27_o> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_dqs_out_of_range_Mux_28_o> created at line 1493.
    Summary:
	inferred  56 D-type flip-flop(s).
	inferred 230 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_phy_4lanes_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_lane_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v".
        ABCD = "A"
        PO_DATA_CTL = "TRUE"
        BITLANES = 12'b001011111111
        BITLANES_OUTONLY = 12'b001000000000
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000000000
        RCLK_SELECT_LANE = "B"
        PC_CLK_RATIO = 4
        USE_PRE_POST_FIFO = "TRUE"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_ARRAY_MODE = "UNDECLARED"
        OF_OUTPUT_DISABLE = "FALSE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_ARRAY_MODE = "UNDECLARED"
        IF_SYNCHRONOUS_MODE = "FALSE"
        PI_BURST_MODE = "TRUE"
        PI_CLKOUT_DIV = 2
        PI_FREQ_REF_DIV = "NONE"
        PI_FINE_DELAY = 33
        PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PI_SEL_CLK_OFFSET = 6
        PI_SYNC_IN_DIV_RST = "TRUE"
        PO_CLKOUT_DIV = 2
        PO_FINE_DELAY = 60
        PO_COARSE_BYPASS = "FALSE"
        PO_COARSE_DELAY = 0
        PO_OCLK_DELAY = 30
        PO_OCLKDELAY_INV = "TRUE"
        PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PO_SYNC_IN_DIV_RST = "TRUE"
        OSERDES_DATA_RATE = "UNDECLARED"
        OSERDES_DATA_WIDTH = "UNDECLARED"
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        TCK = 1666
        SYNTHESIS = "TRUE"
        BUS_WIDTH = 12
        MSB_BURST_PEND_PO = 3
        MSB_BURST_PEND_PI = 7
        MSB_RANK_SEL_I = 15
        PHASER_CTL_BUS_WIDTH = 16
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <if_empty_r>.
    Set property "MAX_FANOUT = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <ififo_rd_en_in>.
    Set property "MAX_FANOUT = 10" for signal <ififo_rd_en_in>.
WARNING:Xst:647 - Input <phaser_ctl_bus<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_cmd_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dummy_i5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dummy_i6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <of_dqbus<47:40>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ofifo_rst>.
    Found 80-bit register for signal <rd_data_r>.
    Found 4-bit register for signal <if_empty_r>.
    Found 1-bit register for signal <ififo_rst>.
    Summary:
	inferred  86 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_byte_lane_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_if_post_fifo>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v".
        TCQ = 25
        DEPTH = 4
        WIDTH = 80
    Set property "syn_maxfan = 3" for signal <my_empty>.
    Set property "KEEP = TRUE" for signal <my_empty>.
    Set property "equivalent_register_removal = no" for signal <my_empty>.
    Set property "MAX_FANOUT = 3" for signal <my_empty>.
    Set property "KEEP = TRUE" for signal <rd_ptr>.
    Set property "MAX_FANOUT = 10" for signal <rd_ptr>.
    Set property "KEEP = TRUE" for signal <wr_ptr>.
    Set property "MAX_FANOUT = 10" for signal <wr_ptr>.
    Found 4x80-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 1-bit register for signal <my_full>.
    Found 2-bit register for signal <rd_ptr>.
    Found 2-bit register for signal <wr_ptr>.
    Found 4-bit register for signal <my_empty>.
    Found 2-bit adder for signal <rd_ptr[1]_GND_58_o_add_2_OUT> created at line 115.
    Found 2-bit adder for signal <wr_ptr[1]_GND_58_o_add_3_OUT> created at line 116.
    Found 2-bit comparator equal for signal <wr_ptr[1]_rd_ptr[1]_equal_5_o> created at line 122
    Found 2-bit comparator equal for signal <rd_ptr[1]_wr_ptr[1]_equal_9_o> created at line 137
    Summary:
	inferred   1 RAM(s).
	inferred   2 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_if_post_fifo> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_of_pre_fifo_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_of_pre_fifo.v".
        TCQ = 25
        DEPTH = 9
        WIDTH = 80
    Set property "KEEP = TRUE" for signal <my_empty>.
    Set property "MAX_FANOUT = 3" for signal <my_empty>.
    Set property "KEEP = TRUE" for signal <my_full>.
    Set property "MAX_FANOUT = 3" for signal <my_full>.
    Set property "KEEP = TRUE" for signal <rd_ptr>.
    Set property "MAX_FANOUT = 10" for signal <rd_ptr>.
    Set property "KEEP = TRUE" for signal <wr_ptr>.
    Set property "MAX_FANOUT = 10" for signal <wr_ptr>.
    Set property "syn_ramstyle = registers" for signal <mem>.
INFO:Xst:3018 - HDL ADVISOR - 720 flip-flops were inferred for signal <mem> because the macro Ram extraction is invalidated. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Found 3-bit register for signal <my_empty>.
    Found 4-bit register for signal <wr_ptr>.
    Found 3-bit register for signal <my_full>.
    Found 5-bit register for signal <entry_cnt>.
    Found 4-bit register for signal <rd_ptr>.
    Found 80-bit register for signal <mem_ff_0>.
    Found 80-bit register for signal <mem_ff_1>.
    Found 80-bit register for signal <mem_ff_2>.
    Found 80-bit register for signal <mem_ff_3>.
    Found 80-bit register for signal <mem_ff_4>.
    Found 80-bit register for signal <mem_ff_5>.
    Found 80-bit register for signal <mem_ff_6>.
    Found 80-bit register for signal <mem_ff_7>.
    Found 80-bit register for signal <mem_ff_8>.
    Found 5-bit subtractor for signal <entry_cnt[4]_GND_59_o_sub_35_OUT> created at line 182.
    Found 5-bit adder for signal <n0089> created at line 129.
    Found 5-bit adder for signal <n0091> created at line 152.
    Found 5-bit adder for signal <entry_cnt[4]_GND_59_o_add_33_OUT> created at line 180.
    Found 80-bit 9-to-1 multiplexer for signal <mem_out> created at line 116.
    Found 4-bit comparator equal for signal <nxt_rd_ptr[3]_wr_ptr[3]_equal_14_o> created at line 148
    Found 4-bit comparator equal for signal <nxt_wr_ptr[3]_rd_ptr[3]_equal_28_o> created at line 171
    Found 5-bit comparator lessequal for signal <n0059> created at line 185
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 739 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_of_pre_fifo_2> synthesized.

Synthesizing Unit <mod_5u_4u>.
    Related source file is "".
    Found 9-bit adder for signal <n0133> created at line 0.
    Found 9-bit adder for signal <GND_60_o_b[3]_add_1_OUT> created at line 0.
    Found 8-bit adder for signal <n0137> created at line 0.
    Found 8-bit adder for signal <GND_60_o_b[3]_add_3_OUT> created at line 0.
    Found 7-bit adder for signal <n0141> created at line 0.
    Found 7-bit adder for signal <GND_60_o_b[3]_add_5_OUT> created at line 0.
    Found 6-bit adder for signal <n0145> created at line 0.
    Found 6-bit adder for signal <GND_60_o_b[3]_add_7_OUT> created at line 0.
    Found 5-bit adder for signal <n0149> created at line 0.
    Found 5-bit adder for signal <a[4]_b[3]_add_9_OUT> created at line 0.
    Found 5-bit adder for signal <n0153> created at line 0.
    Found 5-bit adder for signal <a[4]_GND_60_o_add_11_OUT> created at line 0.
    Found 9-bit comparator lessequal for signal <BUS_0001> created at line 0
    Found 8-bit comparator lessequal for signal <BUS_0002> created at line 0
    Found 7-bit comparator lessequal for signal <BUS_0003> created at line 0
    Found 6-bit comparator lessequal for signal <BUS_0004> created at line 0
    Found 5-bit comparator lessequal for signal <BUS_0005> created at line 0
    Found 5-bit comparator lessequal for signal <BUS_0006> created at line 0
    Summary:
	inferred  12 Adder/Subtractor(s).
	inferred   6 Comparator(s).
	inferred  26 Multiplexer(s).
Unit <mod_5u_4u> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_group_io_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v".
        BITLANES = 12'b001011111111
        BITLANES_OUTONLY = 12'b001000000000
        PO_DATA_CTL = "TRUE"
        OSERDES_DATA_RATE = "DDR"
        OSERDES_DATA_WIDTH = 4
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BUS_WIDTH = 12
        SYNTHESIS = "TRUE"
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[0].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[1].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[2].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[3].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[4].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[5].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[6].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[7].iserdes_dq_.idelaye2>.
WARNING:Xst:647 - Input <oserdes_dqsts<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dq<35:32>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dq<47:40>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelayctrl_refclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <oserdes_dq_buf<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dq_buf<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqts_buf<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqts_buf<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <rst_r2>.
    Found 1-bit register for signal <rst_r3>.
    Found 1-bit register for signal <rst_r4>.
    Found 1-bit register for signal <idelay_ld_rst>.
    Found 1-bit register for signal <rst_r1>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_byte_group_io_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_lane_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v".
        ABCD = "B"
        PO_DATA_CTL = "TRUE"
        BITLANES = 12'b001111111110
        BITLANES_OUTONLY = 12'b001000000000
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000000000
        RCLK_SELECT_LANE = "B"
        PC_CLK_RATIO = 4
        USE_PRE_POST_FIFO = "TRUE"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_ARRAY_MODE = "UNDECLARED"
        OF_OUTPUT_DISABLE = "FALSE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_ARRAY_MODE = "UNDECLARED"
        IF_SYNCHRONOUS_MODE = "FALSE"
        PI_BURST_MODE = "TRUE"
        PI_CLKOUT_DIV = 2
        PI_FREQ_REF_DIV = "NONE"
        PI_FINE_DELAY = 33
        PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PI_SEL_CLK_OFFSET = 6
        PI_SYNC_IN_DIV_RST = "TRUE"
        PO_CLKOUT_DIV = 2
        PO_FINE_DELAY = 60
        PO_COARSE_BYPASS = "FALSE"
        PO_COARSE_DELAY = 0
        PO_OCLK_DELAY = 30
        PO_OCLKDELAY_INV = "TRUE"
        PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PO_SYNC_IN_DIV_RST = "TRUE"
        OSERDES_DATA_RATE = "UNDECLARED"
        OSERDES_DATA_WIDTH = "UNDECLARED"
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        TCK = 1666
        SYNTHESIS = "TRUE"
        BUS_WIDTH = 12
        MSB_BURST_PEND_PO = 3
        MSB_BURST_PEND_PI = 7
        MSB_RANK_SEL_I = 15
        PHASER_CTL_BUS_WIDTH = 16
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <if_empty_r>.
    Set property "MAX_FANOUT = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <ififo_rd_en_in>.
    Set property "MAX_FANOUT = 10" for signal <ififo_rd_en_in>.
WARNING:Xst:647 - Input <phaser_ctl_bus<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<4:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<9:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_cmd_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dummy_i5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dummy_i6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <of_dqbus<47:40>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ofifo_rst>.
    Found 80-bit register for signal <rd_data_r>.
    Found 4-bit register for signal <if_empty_r>.
    Found 1-bit register for signal <ififo_rst>.
    Summary:
	inferred  86 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_byte_lane_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_group_io_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v".
        BITLANES = 12'b001111111110
        BITLANES_OUTONLY = 12'b001000000000
        PO_DATA_CTL = "TRUE"
        OSERDES_DATA_RATE = "DDR"
        OSERDES_DATA_WIDTH = 4
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BUS_WIDTH = 12
        SYNTHESIS = "TRUE"
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[1].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[2].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[3].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[4].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[5].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[6].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[7].iserdes_dq_.idelaye2>.
    Set property "IODELAY_GROUP = IODELAY_MIG" for instance <input_[8].iserdes_dq_.idelaye2>.
WARNING:Xst:647 - Input <oserdes_dqsts<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dq<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dq<47:40>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelayctrl_refclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <oserdes_dq_buf<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dq_buf<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqts_buf<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqts_buf<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <rst_r2>.
    Found 1-bit register for signal <rst_r3>.
    Found 1-bit register for signal <rst_r4>.
    Found 1-bit register for signal <idelay_ld_rst>.
    Found 1-bit register for signal <rst_r1>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_byte_group_io_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_lane_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v".
        ABCD = "C"
        PO_DATA_CTL = "TRUE"
        BITLANES = 12'b001111111110
        BITLANES_OUTONLY = 12'b001000000000
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000000000
        RCLK_SELECT_LANE = "B"
        PC_CLK_RATIO = 4
        USE_PRE_POST_FIFO = "TRUE"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_ARRAY_MODE = "UNDECLARED"
        OF_OUTPUT_DISABLE = "FALSE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_ARRAY_MODE = "UNDECLARED"
        IF_SYNCHRONOUS_MODE = "FALSE"
        PI_BURST_MODE = "TRUE"
        PI_CLKOUT_DIV = 2
        PI_FREQ_REF_DIV = "NONE"
        PI_FINE_DELAY = 33
        PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PI_SEL_CLK_OFFSET = 6
        PI_SYNC_IN_DIV_RST = "TRUE"
        PO_CLKOUT_DIV = 2
        PO_FINE_DELAY = 60
        PO_COARSE_BYPASS = "FALSE"
        PO_COARSE_DELAY = 0
        PO_OCLK_DELAY = 30
        PO_OCLKDELAY_INV = "TRUE"
        PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PO_SYNC_IN_DIV_RST = "TRUE"
        OSERDES_DATA_RATE = "UNDECLARED"
        OSERDES_DATA_WIDTH = "UNDECLARED"
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        TCK = 1666
        SYNTHESIS = "TRUE"
        BUS_WIDTH = 12
        MSB_BURST_PEND_PO = 3
        MSB_BURST_PEND_PI = 7
        MSB_RANK_SEL_I = 15
        PHASER_CTL_BUS_WIDTH = 16
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <if_empty_r>.
    Set property "MAX_FANOUT = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <ififo_rd_en_in>.
    Set property "MAX_FANOUT = 10" for signal <ififo_rd_en_in>.
WARNING:Xst:647 - Input <phaser_ctl_bus<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<5:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<11:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_cmd_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dummy_i5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dummy_i6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <of_dqbus<47:40>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ofifo_rst>.
    Found 80-bit register for signal <rd_data_r>.
    Found 4-bit register for signal <if_empty_r>.
    Found 1-bit register for signal <ififo_rst>.
    Summary:
	inferred  86 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_byte_lane_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_lane_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v".
        ABCD = "D"
        PO_DATA_CTL = "TRUE"
        BITLANES = 12'b001111111110
        BITLANES_OUTONLY = 12'b001000000000
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000000000
        RCLK_SELECT_LANE = "B"
        PC_CLK_RATIO = 4
        USE_PRE_POST_FIFO = "TRUE"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_ARRAY_MODE = "UNDECLARED"
        OF_OUTPUT_DISABLE = "FALSE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_ARRAY_MODE = "UNDECLARED"
        IF_SYNCHRONOUS_MODE = "FALSE"
        PI_BURST_MODE = "TRUE"
        PI_CLKOUT_DIV = 2
        PI_FREQ_REF_DIV = "NONE"
        PI_FINE_DELAY = 33
        PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PI_SEL_CLK_OFFSET = 6
        PI_SYNC_IN_DIV_RST = "TRUE"
        PO_CLKOUT_DIV = 2
        PO_FINE_DELAY = 60
        PO_COARSE_BYPASS = "FALSE"
        PO_COARSE_DELAY = 0
        PO_OCLK_DELAY = 30
        PO_OCLKDELAY_INV = "TRUE"
        PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PO_SYNC_IN_DIV_RST = "TRUE"
        OSERDES_DATA_RATE = "UNDECLARED"
        OSERDES_DATA_WIDTH = "UNDECLARED"
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        TCK = 1666
        SYNTHESIS = "TRUE"
        BUS_WIDTH = 12
        MSB_BURST_PEND_PO = 3
        MSB_BURST_PEND_PI = 7
        MSB_RANK_SEL_I = 15
        PHASER_CTL_BUS_WIDTH = 16
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <if_empty_r>.
    Set property "MAX_FANOUT = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <ififo_rd_en_in>.
    Set property "MAX_FANOUT = 10" for signal <ififo_rd_en_in>.
WARNING:Xst:647 - Input <phaser_ctl_bus<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<6:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<13:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_cmd_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dummy_i5> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dummy_i6> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <of_dqbus<47:40>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ofifo_rst>.
    Found 80-bit register for signal <rd_data_r>.
    Found 4-bit register for signal <if_empty_r>.
    Found 1-bit register for signal <ififo_rst>.
    Summary:
	inferred  86 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_byte_lane_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_4lanes_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v".
        GENERATE_IDELAYCTRL = "FALSE"
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000001000
        NUM_DDR_CK = 1
        BYTE_LANES = 4'b1110
        DATA_CTL_N = 4'b0000
        BITLANES = 48'b001111111111111111111111110000000000000000000000
        BITLANES_OUTONLY = 48'b000000000000000000000000000000000000000000000000
        LANE_REMAP = 16'b0011001000010000
        LAST_BANK = "FALSE"
        USE_PRE_POST_FIFO = "TRUE"
        RCLK_SELECT_LANE = "B"
        TCK = 1666
        SYNTHESIS = "TRUE"
        PO_CTL_COARSE_BYPASS = "FALSE"
        PO_FINE_DELAY = 60
        PI_SEL_CLK_OFFSET = 6
        PC_CLK_RATIO = 4
        A_PI_FREQ_REF_DIV = "NONE"
        A_PI_CLKOUT_DIV = 2
        A_PI_BURST_MODE = "TRUE"
        A_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        A_PI_FINE_DELAY = 16
        A_PI_SYNC_IN_DIV_RST = "TRUE"
        B_PI_FREQ_REF_DIV = "NONE"
        B_PI_CLKOUT_DIV = 2
        B_PI_BURST_MODE = "TRUE"
        B_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF"
        B_PI_FINE_DELAY = 16
        B_PI_SYNC_IN_DIV_RST = "TRUE"
        C_PI_FREQ_REF_DIV = "NONE"
        C_PI_CLKOUT_DIV = 2
        C_PI_BURST_MODE = "TRUE"
        C_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        C_PI_FINE_DELAY = 16
        C_PI_SYNC_IN_DIV_RST = "TRUE"
        D_PI_FREQ_REF_DIV = "NONE"
        D_PI_CLKOUT_DIV = 2
        D_PI_BURST_MODE = "TRUE"
        D_PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        D_PI_FINE_DELAY = 16
        D_PI_SYNC_IN_DIV_RST = "TRUE"
        A_PO_CLKOUT_DIV = 4
        A_PO_FINE_DELAY = 60
        A_PO_COARSE_DELAY = 0
        A_PO_OCLK_DELAY = 30
        A_PO_OCLKDELAY_INV = "TRUE"
        A_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        A_PO_SYNC_IN_DIV_RST = "TRUE"
        B_PO_CLKOUT_DIV = 4
        B_PO_FINE_DELAY = 60
        B_PO_COARSE_DELAY = 0
        B_PO_OCLK_DELAY = 30
        B_PO_OCLKDELAY_INV = "TRUE"
        B_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        B_PO_SYNC_IN_DIV_RST = "TRUE"
        C_PO_CLKOUT_DIV = 4
        C_PO_FINE_DELAY = 60
        C_PO_COARSE_DELAY = 0
        C_PO_OCLK_DELAY = 30
        C_PO_OCLKDELAY_INV = "TRUE"
        C_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        C_PO_SYNC_IN_DIV_RST = "TRUE"
        D_PO_CLKOUT_DIV = 4
        D_PO_FINE_DELAY = 60
        D_PO_COARSE_DELAY = 0
        D_PO_OCLK_DELAY = 30
        D_PO_OCLKDELAY_INV = "TRUE"
        D_PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        D_PO_SYNC_IN_DIV_RST = "TRUE"
        A_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        A_IDELAYE2_IDELAY_VALUE = 0
        B_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        B_IDELAYE2_IDELAY_VALUE = 0
        C_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        C_IDELAYE2_IDELAY_VALUE = 0
        D_IDELAYE2_IDELAY_TYPE = "VARIABLE"
        D_IDELAYE2_IDELAY_VALUE = 0
        PC_BURST_MODE = "TRUE"
        PC_DATA_CTL_N = 4'b0000
        PC_CMD_OFFSET = 8
        PC_RD_CMD_OFFSET_0 = 10
        PC_RD_CMD_OFFSET_1 = 10
        PC_RD_CMD_OFFSET_2 = 10
        PC_RD_CMD_OFFSET_3 = 10
        PC_CO_DURATION = 1
        PC_DI_DURATION = 1
        PC_DO_DURATION = 1
        PC_RD_DURATION_0 = 6
        PC_RD_DURATION_1 = 6
        PC_RD_DURATION_2 = 6
        PC_RD_DURATION_3 = 6
        PC_WR_CMD_OFFSET_0 = 8
        PC_WR_CMD_OFFSET_1 = 8
        PC_WR_CMD_OFFSET_2 = 8
        PC_WR_CMD_OFFSET_3 = 8
        PC_WR_DURATION_0 = 7
        PC_WR_DURATION_1 = 7
        PC_WR_DURATION_2 = 7
        PC_WR_DURATION_3 = 7
        PC_AO_WRLVL_EN = 0
        PC_AO_TOGGLE = 4'b0001
        PC_FOUR_WINDOW_CLOCKS = 63
        PC_EVENTS_DELAY = 18
        PC_PHY_COUNT_EN = "FALSE"
        PC_SYNC_MODE = "FALSE"
        PC_DISABLE_SEQ_MATCH = "TRUE"
        PC_MULTI_REGION = "TRUE"
        A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        B_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        C_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        D_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_OUTPUT_DISABLE = "TRUE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        A_OS_DATA_RATE = "UNDECLARED"
        A_OS_DATA_WIDTH = "UNDECLARED"
        B_OS_DATA_RATE = "UNDECLARED"
        B_OS_DATA_WIDTH = "UNDECLARED"
        C_OS_DATA_RATE = "UNDECLARED"
        C_OS_DATA_WIDTH = "UNDECLARED"
        D_OS_DATA_RATE = "UNDECLARED"
        D_OS_DATA_WIDTH = "UNDECLARED"
        A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        B_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        C_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        D_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_SYNCHRONOUS_MODE = "FALSE"
        HIGHEST_LANE = 4
        N_CTL_LANES = 32'b00000000000000000000000000000011
        N_BYTE_LANES = 32'b00000000000000000000000000000011
        N_DATA_LANES = 32'b00000000000000000000000000000000
        AUXOUT_WIDTH = 4
        LP_DDR_CK_WIDTH = 2
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <A_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <A_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <A_po_fine_inc>.
    Set property "syn_maxfan = 3" for signal <B_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <B_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <B_po_fine_inc>.
    Set property "syn_maxfan = 3" for signal <C_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <C_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <C_po_fine_inc>.
    Set property "syn_maxfan = 3" for signal <D_po_fine_inc>.
    Set property "KEEP = TRUE" for signal <D_po_fine_inc>.
    Set property "MAX_FANOUT = 3" for signal <D_po_fine_inc>.
WARNING:Xst:647 - Input <phy_dout<79:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_ctl_wd<22:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mem_dq_in<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mem_dqs_in<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mem_refclk_div4> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <input_sink> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <phy_din> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <if_a_full> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <if_full> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <of_a_empty> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <of_empty> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <pre_fifo_a_full> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1070: Output port <pi_iserdes_rst> of the instance <ddr_byte_lane_B.ddr_byte_lane_B> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <phy_din> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <rclk> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <if_a_full> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <if_full> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <of_a_empty> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <of_empty> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <pre_fifo_a_full> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1201: Output port <pi_iserdes_rst> of the instance <ddr_byte_lane_C.ddr_byte_lane_C> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <phy_din> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <rclk> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <if_a_full> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <if_full> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <of_a_empty> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <of_empty> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <pre_fifo_a_full> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_4lanes.v" line 1333: Output port <pi_iserdes_rst> of the instance <ddr_byte_lane_D.ddr_byte_lane_D> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <mem_dq_out<11:0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_dq_ts<11:0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_dqs_out<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mem_dqs_ts<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <A_pi_dqs_out_of_range> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Register <D_rst_primitives> equivalent to <B_rst_primitives> has been removed
    Register <C_rst_primitives> equivalent to <B_rst_primitives> has been removed
    Found 1-bit register for signal <rst_out>.
    Found 1-bit register for signal <rst_primitives>.
    Found 1-bit register for signal <B_rst_primitives>.
    Found 31-bit register for signal <rclk_delay<30:0>>.
    Found 1-bit register for signal <mcGo>.
    Found 1-bit register for signal <po_coarse_overflow>.
    Found 1-bit register for signal <po_fine_overflow>.
    Found 9-bit register for signal <po_counter_read_val>.
    Found 1-bit register for signal <pi_fine_overflow>.
    Found 6-bit register for signal <pi_counter_read_val>.
    Found 1-bit register for signal <pi_phase_locked>.
    Found 1-bit register for signal <pi_dqs_found>.
    Found 1-bit register for signal <pi_dqs_out_of_range>.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_po_coarse_overflow_Mux_24_o> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_po_fine_overflow_Mux_25_o> created at line 1493.
    Found 9-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_po_counter_read_val[8]_wide_mux_26_OUT> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_fine_overflow_Mux_27_o> created at line 1493.
    Found 6-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_counter_read_val[5]_wide_mux_28_OUT> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_phase_locked_Mux_29_o> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_dqs_found_Mux_30_o> created at line 1493.
    Found 1-bit 4-to-1 multiplexer for signal <calib_sel[1]_D_pi_dqs_out_of_range_Mux_31_o> created at line 1493.
    Summary:
	inferred  56 D-type flip-flop(s).
	inferred 179 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_phy_4lanes_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_lane_5>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v".
        ABCD = "B"
        PO_DATA_CTL = "FALSE"
        BITLANES = 12'b110000000000
        BITLANES_OUTONLY = 12'b000000000000
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000001000
        RCLK_SELECT_LANE = "B"
        PC_CLK_RATIO = 4
        USE_PRE_POST_FIFO = "TRUE"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_ARRAY_MODE = "UNDECLARED"
        OF_OUTPUT_DISABLE = "FALSE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_ARRAY_MODE = "UNDECLARED"
        IF_SYNCHRONOUS_MODE = "FALSE"
        PI_BURST_MODE = "TRUE"
        PI_CLKOUT_DIV = 2
        PI_FREQ_REF_DIV = "NONE"
        PI_FINE_DELAY = 16
        PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF"
        PI_SEL_CLK_OFFSET = 6
        PI_SYNC_IN_DIV_RST = "TRUE"
        PO_CLKOUT_DIV = 4
        PO_FINE_DELAY = 60
        PO_COARSE_BYPASS = "FALSE"
        PO_COARSE_DELAY = 0
        PO_OCLK_DELAY = 30
        PO_OCLKDELAY_INV = "TRUE"
        PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PO_SYNC_IN_DIV_RST = "TRUE"
        OSERDES_DATA_RATE = "UNDECLARED"
        OSERDES_DATA_WIDTH = "UNDECLARED"
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        TCK = 1666
        SYNTHESIS = "TRUE"
        BUS_WIDTH = 12
        MSB_BURST_PEND_PO = 3
        MSB_BURST_PEND_PI = 7
        MSB_RANK_SEL_I = 15
        PHASER_CTL_BUS_WIDTH = 16
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <if_empty_r>.
    Set property "MAX_FANOUT = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <ififo_rd_en_in>.
    Set property "MAX_FANOUT = 10" for signal <ififo_rd_en_in>.
WARNING:Xst:647 - Input <phaser_ctl_bus<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<15:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <byte_rd_en_oth_lanes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <byte_rd_en_oth_banks> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_en_calib> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_load_val> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <if_empty_def> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_data_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <if_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_rst_dqs_find> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_fine_enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_fine_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_load_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_read_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" line 629: Output port <iserdes_dout> of the instance <ddr_byte_group_io> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" line 629: Output port <dqs_to_phaser> of the instance <ddr_byte_group_io> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <pi_counter_read_val> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <rclk> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <pi_iserdes_rst> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <pi_fine_overflow> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dqs_out_of_range> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <iserdes_clk> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <iserdes_clkdiv> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ofifo_rst>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_byte_lane_5> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_group_io_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v".
        BITLANES = 12'b110000000000
        BITLANES_OUTONLY = 12'b000000000000
        PO_DATA_CTL = "FALSE"
        OSERDES_DATA_RATE = "SDR"
        OSERDES_DATA_WIDTH = 4
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BUS_WIDTH = 12
        SYNTHESIS = "TRUE"
WARNING:Xst:647 - Input <mem_dq_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqs> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqsts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dq<39:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkdiv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_clk_delayed> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_ld> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelayctrl_refclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <iserdes_dout> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dq_buf<9:0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqts_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqs_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqsts_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_byte_group_io_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_lane_6>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v".
        ABCD = "C"
        PO_DATA_CTL = "FALSE"
        BITLANES = 12'b111111111111
        BITLANES_OUTONLY = 12'b000000000000
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000001000
        RCLK_SELECT_LANE = "B"
        PC_CLK_RATIO = 4
        USE_PRE_POST_FIFO = "TRUE"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_ARRAY_MODE = "UNDECLARED"
        OF_OUTPUT_DISABLE = "FALSE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_ARRAY_MODE = "UNDECLARED"
        IF_SYNCHRONOUS_MODE = "FALSE"
        PI_BURST_MODE = "TRUE"
        PI_CLKOUT_DIV = 2
        PI_FREQ_REF_DIV = "NONE"
        PI_FINE_DELAY = 16
        PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PI_SEL_CLK_OFFSET = 6
        PI_SYNC_IN_DIV_RST = "TRUE"
        PO_CLKOUT_DIV = 4
        PO_FINE_DELAY = 60
        PO_COARSE_BYPASS = "FALSE"
        PO_COARSE_DELAY = 0
        PO_OCLK_DELAY = 30
        PO_OCLKDELAY_INV = "TRUE"
        PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PO_SYNC_IN_DIV_RST = "TRUE"
        OSERDES_DATA_RATE = "UNDECLARED"
        OSERDES_DATA_WIDTH = "UNDECLARED"
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        TCK = 1666
        SYNTHESIS = "TRUE"
        BUS_WIDTH = 12
        MSB_BURST_PEND_PO = 3
        MSB_BURST_PEND_PI = 7
        MSB_RANK_SEL_I = 15
        PHASER_CTL_BUS_WIDTH = 16
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <if_empty_r>.
    Set property "MAX_FANOUT = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <ififo_rd_en_in>.
    Set property "MAX_FANOUT = 10" for signal <ififo_rd_en_in>.
WARNING:Xst:647 - Input <phaser_ctl_bus<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<15:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <byte_rd_en_oth_lanes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <byte_rd_en_oth_banks> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_en_calib> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_load_val> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <if_empty_def> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_data_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <if_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_rst_dqs_find> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_fine_enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_fine_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_load_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_read_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" line 629: Output port <iserdes_dout> of the instance <ddr_byte_group_io> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" line 629: Output port <dqs_to_phaser> of the instance <ddr_byte_group_io> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <pi_counter_read_val> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <rclk> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <pi_iserdes_rst> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <pi_fine_overflow> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dqs_out_of_range> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <iserdes_clk> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <iserdes_clkdiv> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ofifo_rst>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_byte_lane_6> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_group_io_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v".
        BITLANES = 12'b111111111111
        BITLANES_OUTONLY = 12'b000000000000
        PO_DATA_CTL = "FALSE"
        OSERDES_DATA_RATE = "SDR"
        OSERDES_DATA_WIDTH = 4
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BUS_WIDTH = 12
        SYNTHESIS = "TRUE"
WARNING:Xst:647 - Input <mem_dq_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqs> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqsts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkdiv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_clk_delayed> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_ld> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelayctrl_refclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <iserdes_dout> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqts_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqs_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqsts_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_byte_group_io_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_lane_7>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v".
        ABCD = "D"
        PO_DATA_CTL = "FALSE"
        BITLANES = 12'b001111111111
        BITLANES_OUTONLY = 12'b000000000000
        BYTELANES_DDR_CK = 72'b000000000000000000000000000000000000000000000000000000000000000000001000
        RCLK_SELECT_LANE = "B"
        PC_CLK_RATIO = 4
        USE_PRE_POST_FIFO = "TRUE"
        OF_ALMOST_EMPTY_VALUE = 1
        OF_ALMOST_FULL_VALUE = 1
        OF_ARRAY_MODE = "UNDECLARED"
        OF_OUTPUT_DISABLE = "FALSE"
        OF_SYNCHRONOUS_MODE = "FALSE"
        IF_ALMOST_EMPTY_VALUE = 1
        IF_ALMOST_FULL_VALUE = 1
        IF_ARRAY_MODE = "UNDECLARED"
        IF_SYNCHRONOUS_MODE = "FALSE"
        PI_BURST_MODE = "TRUE"
        PI_CLKOUT_DIV = 2
        PI_FREQ_REF_DIV = "NONE"
        PI_FINE_DELAY = 16
        PI_OUTPUT_CLK_SRC = "DELAYED_REF"
        PI_SEL_CLK_OFFSET = 6
        PI_SYNC_IN_DIV_RST = "TRUE"
        PO_CLKOUT_DIV = 4
        PO_FINE_DELAY = 60
        PO_COARSE_BYPASS = "FALSE"
        PO_COARSE_DELAY = 0
        PO_OCLK_DELAY = 30
        PO_OCLKDELAY_INV = "TRUE"
        PO_OUTPUT_CLK_SRC = "DELAYED_REF"
        PO_SYNC_IN_DIV_RST = "TRUE"
        OSERDES_DATA_RATE = "UNDECLARED"
        OSERDES_DATA_WIDTH = "UNDECLARED"
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BANK_TYPE = "HP_IO"
        TCK = 1666
        SYNTHESIS = "TRUE"
        BUS_WIDTH = 12
        MSB_BURST_PEND_PO = 3
        MSB_BURST_PEND_PI = 7
        MSB_RANK_SEL_I = 15
        PHASER_CTL_BUS_WIDTH = 16
        CKE_ODT_AUX = "FALSE"
    Set property "syn_maxfan = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <if_empty_r>.
    Set property "MAX_FANOUT = 3" for signal <if_empty_r>.
    Set property "KEEP = TRUE" for signal <ififo_rd_en_in>.
    Set property "MAX_FANOUT = 10" for signal <ififo_rd_en_in>.
WARNING:Xst:647 - Input <phaser_ctl_bus<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phaser_ctl_bus<15:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <byte_rd_en_oth_lanes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <byte_rd_en_oth_banks> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_en_calib> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_load_val> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <if_empty_def> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_data_wr_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_rd_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <if_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_rst_dqs_find> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_fine_enable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_fine_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_load_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_counter_read_en> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" line 629: Output port <iserdes_dout> of the instance <ddr_byte_group_io> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v" line 629: Output port <dqs_to_phaser> of the instance <ddr_byte_group_io> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <pi_counter_read_val> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <rclk> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <pi_iserdes_rst> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <pi_fine_overflow> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dqs_out_of_range> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <iserdes_clk> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <iserdes_clkdiv> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ofifo_rst>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_byte_lane_7> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_byte_group_io_5>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_group_io.v".
        BITLANES = 12'b001111111111
        BITLANES_OUTONLY = 12'b000000000000
        PO_DATA_CTL = "FALSE"
        OSERDES_DATA_RATE = "SDR"
        OSERDES_DATA_WIDTH = 4
        IDELAYE2_IDELAY_TYPE = "VARIABLE"
        IDELAYE2_IDELAY_VALUE = 0
        IODELAY_GRP = "IODELAY_MIG"
        BUS_WIDTH = 12
        SYNTHESIS = "TRUE"
WARNING:Xst:647 - Input <mem_dq_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqs> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqsts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dq<47:40>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_dqts> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_clkdiv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <phy_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iserdes_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oserdes_clk_delayed> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_inc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelay_ld> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <idelayctrl_refclk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <iserdes_dout> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dq_buf<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqts_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqs_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <oserdes_dqsts_buf> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_byte_group_io_5> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_calib_top>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v".
        TCQ = 100
        nCK_PER_CLK = 4
        tCK = 1666
        CLK_PERIOD = 6664
        N_CTL_LANES = 32'b00000000000000000000000000000011
        DRAM_TYPE = "DDR3"
        PRBS_WIDTH = 8
        HIGHEST_LANE = 8
        HIGHEST_BANK = 2
        BANK_TYPE = "HP_IO"
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        DQS_BYTE_MAP = 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
        CTL_BYTE_LANE = 8'b00111001
        CTL_BANK = 3'b001
        SLOT_1_CONFIG = 8'b00000000
        BANK_WIDTH = 3
        CA_MIRROR = "OFF"
        COL_WIDTH = 10
        nCS_PER_RANK = 1
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_WIDTH = 8
        ROW_WIDTH = 15
        RANKS = 1
        CS_WIDTH = 1
        CKE_WIDTH = 1
        DDR2_DQSN_ENABLE = "YES"
        PER_BIT_DESKEW = "OFF"
        NUM_DQSFOUND_CAL = 1020
        CALIB_ROW_ADD = 16'b0000000000000000
        CALIB_COL_ADD = 12'b000000000000
        CALIB_BA_ADD = 3'b000
        AL = "0"
        TEST_AL = "0"
        ADDR_CMD_MODE = "1T"
        BURST_MODE = "8"
        BURST_TYPE = "SEQ"
        nCL = 9
        nCWL = 7
        tRFC = 300000
        OUTPUT_DRV = "HIGH"
        REG_CTRL = "OFF"
        RTT_NOM = "60"
        RTT_WR = "OFF"
        USE_ODT_PORT = 1
        WRLVL = "ON"
        PRE_REV3ES = "OFF"
        SIM_INIT_OPTION = "NONE"
        SIM_CAL_OPTION = "NONE"
        CKE_ODT_AUX = "FALSE"
        DEBUG_PORT = "ON"
    Set property "syn_maxfan = 10" for signal <calib_sel>.
    Set property "KEEP = TRUE" for signal <calib_sel>.
    Set property "MAX_FANOUT = 10" for signal <calib_sel>.
    Set property "syn_maxfan = 10" for signal <calib_zero_inputs>.
    Set property "KEEP = TRUE" for signal <calib_zero_inputs>.
    Set property "MAX_FANOUT = 10" for signal <calib_zero_inputs>.
    Set property "syn_maxfan = 3" for signal <po_sel_stg2stg3<2>>.
    Set property "KEEP = TRUE" for signal <po_sel_stg2stg3<2>>.
    Set property "MAX_FANOUT = 3" for signal <po_sel_stg2stg3<2>>.
    Set property "syn_maxfan = 3" for signal <po_sel_stg2stg3<1>>.
    Set property "KEEP = TRUE" for signal <po_sel_stg2stg3<1>>.
    Set property "MAX_FANOUT = 3" for signal <po_sel_stg2stg3<1>>.
    Set property "syn_maxfan = 3" for signal <po_sel_stg2stg3<0>>.
    Set property "KEEP = TRUE" for signal <po_sel_stg2stg3<0>>.
    Set property "MAX_FANOUT = 3" for signal <po_sel_stg2stg3<0>>.
    Set property "syn_maxfan = 3" for signal <po_stg2_c_incdec<2>>.
    Set property "KEEP = TRUE" for signal <po_stg2_c_incdec<2>>.
    Set property "MAX_FANOUT = 3" for signal <po_stg2_c_incdec<2>>.
    Set property "syn_maxfan = 3" for signal <po_stg2_c_incdec<1>>.
    Set property "KEEP = TRUE" for signal <po_stg2_c_incdec<1>>.
    Set property "MAX_FANOUT = 3" for signal <po_stg2_c_incdec<1>>.
    Set property "syn_maxfan = 3" for signal <po_stg2_c_incdec<0>>.
    Set property "KEEP = TRUE" for signal <po_stg2_c_incdec<0>>.
    Set property "MAX_FANOUT = 3" for signal <po_stg2_c_incdec<0>>.
    Set property "syn_maxfan = 3" for signal <po_en_stg2_c<2>>.
    Set property "KEEP = TRUE" for signal <po_en_stg2_c<2>>.
    Set property "MAX_FANOUT = 3" for signal <po_en_stg2_c<2>>.
    Set property "syn_maxfan = 3" for signal <po_en_stg2_c<1>>.
    Set property "KEEP = TRUE" for signal <po_en_stg2_c<1>>.
    Set property "MAX_FANOUT = 3" for signal <po_en_stg2_c<1>>.
    Set property "syn_maxfan = 3" for signal <po_en_stg2_c<0>>.
    Set property "KEEP = TRUE" for signal <po_en_stg2_c<0>>.
    Set property "MAX_FANOUT = 3" for signal <po_en_stg2_c<0>>.
    Set property "syn_maxfan = 3" for signal <po_stg2_f_incdec<2>>.
    Set property "KEEP = TRUE" for signal <po_stg2_f_incdec<2>>.
    Set property "MAX_FANOUT = 3" for signal <po_stg2_f_incdec<2>>.
    Set property "syn_maxfan = 3" for signal <po_stg2_f_incdec<1>>.
    Set property "KEEP = TRUE" for signal <po_stg2_f_incdec<1>>.
    Set property "MAX_FANOUT = 3" for signal <po_stg2_f_incdec<1>>.
    Set property "syn_maxfan = 3" for signal <po_stg2_f_incdec<0>>.
    Set property "KEEP = TRUE" for signal <po_stg2_f_incdec<0>>.
    Set property "MAX_FANOUT = 3" for signal <po_stg2_f_incdec<0>>.
    Set property "syn_maxfan = 3" for signal <po_en_stg2_f<2>>.
    Set property "KEEP = TRUE" for signal <po_en_stg2_f<2>>.
    Set property "MAX_FANOUT = 3" for signal <po_en_stg2_f<2>>.
    Set property "syn_maxfan = 3" for signal <po_en_stg2_f<1>>.
    Set property "KEEP = TRUE" for signal <po_en_stg2_f<1>>.
    Set property "MAX_FANOUT = 3" for signal <po_en_stg2_f<1>>.
    Set property "syn_maxfan = 3" for signal <po_en_stg2_f<0>>.
    Set property "KEEP = TRUE" for signal <po_en_stg2_f<0>>.
    Set property "MAX_FANOUT = 3" for signal <po_en_stg2_f<0>>.
    Set property "syn_maxfan = 10" for signal <calib_in_common>.
    Set property "KEEP = TRUE" for signal <calib_in_common>.
    Set property "MAX_FANOUT = 10" for signal <calib_in_common>.
    Set property "syn_maxfan = 10" for signal <init_calib_complete>.
    Set property "KEEP = TRUE" for signal <init_calib_complete>.
    Set property "MAX_FANOUT = 10" for signal <init_calib_complete>.
    Set property "KEEP = TRUE" for signal <idelay_inc_r2>.
    Set property "MAX_FANOUT = 30" for signal <idelay_inc_r2>.
WARNING:Xst:647 - Input <pi_phaselocked> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_found_dqs> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pi_dqs_found_all> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1270: Output port <no_rst_tg_mc> of the instance <u_ddr_phy_init> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1270: Output port <init_wrcal_done> of the instance <u_ddr_phy_init> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1388: Output port <po_dec_dly_cnt> of the instance <u_ddr_phy_wrcal> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1388: Output port <po_dly_load> of the instance <u_ddr_phy_wrcal> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1450: Output port <dbg_dqs_count> of the instance <mb_wrlvl_inst.u_ddr_phy_wrlvl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1450: Output port <dbg_wl_state> of the instance <mb_wrlvl_inst.u_ddr_phy_wrlvl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1450: Output port <phy_ctl_rdy_dly> of the instance <mb_wrlvl_inst.u_ddr_phy_wrlvl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1643: Output port <dqsfound_retry_done> of the instance <dqsfind_calib_right.u_ddr_phy_dqs_found_cal> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1761: Output port <rdlvl_stg1_err> of the instance <u_ddr_phy_rdlvl> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_calib_top.v" line 1761: Output port <rdlvl_assrt_common> of the instance <u_ddr_phy_rdlvl> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <init_calib_complete>.
    Found 1-bit register for signal <phy_if_reset>.
    Found 1-bit register for signal <dbg_pi_f_inc_r>.
    Found 1-bit register for signal <dbg_pi_f_en_r>.
    Found 1-bit register for signal <dbg_sel_pi_incdec_r>.
    Found 1-bit register for signal <dbg_po_f_inc_r>.
    Found 1-bit register for signal <dbg_po_f_stg23_sel_r>.
    Found 1-bit register for signal <dbg_po_f_en_r>.
    Found 1-bit register for signal <dbg_sel_po_incdec_r>.
    Found 1-bit register for signal <tempmon_pi_f_inc_r>.
    Found 1-bit register for signal <tempmon_pi_f_en_r>.
    Found 1-bit register for signal <ck_addr_cmd_delay_done_r1>.
    Found 1-bit register for signal <ck_addr_cmd_delay_done_r2>.
    Found 1-bit register for signal <ck_addr_cmd_delay_done_r3>.
    Found 1-bit register for signal <ck_addr_cmd_delay_done_r4>.
    Found 1-bit register for signal <ck_addr_cmd_delay_done_r5>.
    Found 1-bit register for signal <ck_addr_cmd_delay_done_r6>.
    Found 3-bit register for signal <byte_sel_cnt>.
    Found 3-bit register for signal <ctl_lane_sel>.
    Found 1-bit register for signal <calib_in_common>.
    Found 6-bit register for signal <calib_sel>.
    Found 2-bit register for signal <calib_zero_inputs>.
    Found 2-bit register for signal <calib_zero_ctrl>.
    Found 1-bit register for signal <rdlvl_stg1_done_r1>.
    Found 1-bit register for signal <prbs_rdlvl_done_r1>.
    Found 1-bit register for signal <reset_if_r1>.
    Found 1-bit register for signal <reset_if_r2>.
    Found 1-bit register for signal <reset_if_r3>.
    Found 1-bit register for signal <reset_if_r4>.
    Found 1-bit register for signal <reset_if_r5>.
    Found 1-bit register for signal <reset_if_r6>.
    Found 1-bit register for signal <reset_if_r7>.
    Found 1-bit register for signal <reset_if_r8>.
    Found 1-bit register for signal <reset_if_r9>.
    Found 1-bit register for signal <reset_if>.
    Found 1-bit register for signal <idelay_ce_r1>.
    Found 1-bit register for signal <idelay_ce_r2>.
    Found 1-bit register for signal <idelay_inc_r1>.
    Found 1-bit register for signal <idelay_inc_r2>.
    Found 7-bit adder for signal <n0384> created at line 989.
    Found 14-bit shifter logical right for signal <n0354> created at line 938
    Found 286-bit shifter logical right for signal <n0356> created at line 988
    Found 285-bit shifter logical right for signal <n0358> created at line 989
    Found 3-bit comparator lessequal for signal <n0172> created at line 993
    WARNING:Xst:2404 -  FFs/Latches <rst_tg_mc_r<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_calib_top>.
    WARNING:Xst:2404 -  FFs/Latches <po_f_dly_inc<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_calib_top>.
    WARNING:Xst:2404 -  FFs/Latches <po_f_dly_dec<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_calib_top>.
    WARNING:Xst:2404 -  FFs/Latches <po_dly_done_r2<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_calib_top>.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  50 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  59 Multiplexer(s).
	inferred   3 Combinational logic shifter(s).
Unit <mig_7series_v1_8_ddr_calib_top> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_prbs_gen>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_prbs_gen.v".
        TCQ = 100
        PRBS_WIDTH = 64
    Found 7-bit register for signal <sample_cnt_r>.
    Found 1-bit register for signal <reseed_prbs_r>.
    Found 64-bit register for signal <lfsr_q>.
    Found 1-bit register for signal <phy_if_empty_r>.
    Found 7-bit adder for signal <sample_cnt_r[6]_GND_99_o_add_2_OUT> created at line 144.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  73 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_prbs_gen> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_init>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_init.v".
        TCQ = 100
        nCK_PER_CLK = 4
        CLK_PERIOD = 6664
        USE_ODT_PORT = 1
        PRBS_WIDTH = 8
        BANK_WIDTH = 3
        CA_MIRROR = "OFF"
        COL_WIDTH = 10
        nCS_PER_RANK = 1
        DQ_WIDTH = 32
        DQS_WIDTH = 4
        DQS_CNT_WIDTH = 2
        ROW_WIDTH = 15
        CS_WIDTH = 1
        RANKS = 1
        CKE_WIDTH = 1
        DRAM_TYPE = "DDR3"
        REG_CTRL = "OFF"
        ADDR_CMD_MODE = "1T"
        CALIB_ROW_ADD = 16'b0000000000000000
        CALIB_COL_ADD = 12'b000000000000
        CALIB_BA_ADD = 3'b000
        AL = "0"
        BURST_MODE = "8"
        BURST_TYPE = "SEQ"
        nCL = 9
        nCWL = 7
        tRFC = 300000
        OUTPUT_DRV = "HIGH"
        RTT_NOM = "60"
        RTT_WR = "OFF"
        WRLVL = "ON"
        DDR2_DQSN_ENABLE = "YES"
        nSLOTS = 1
        SIM_INIT_OPTION = "NONE"
        SIM_CAL_OPTION = "NONE"
        CKE_ODT_AUX = "FALSE"
        PRE_REV3ES = "OFF"
        TEST_AL = "0"
    Set property "MAX_FANOUT = 10" for signal <init_calib_complete>.
    Set property "ASYNC_REG = TRUE" for signal <pi_phase_locked_all_r1>.
    Set property "ASYNC_REG = TRUE" for signal <pi_phase_locked_all_r2>.
    Set property "ASYNC_REG = TRUE" for signal <pi_phase_locked_all_r3>.
    Set property "ASYNC_REG = TRUE" for signal <pi_phase_locked_all_r4>.
WARNING:Xst:647 - Input <slot_0_present> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slot_1_present> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wrlvl_byte_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <calib_aux_out> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dbg_phy_init<255:6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Register <phy_address<59>> equivalent to <phy_address<14>> has been removed
    Register <phy_address<44>> equivalent to <phy_address<14>> has been removed
    Register <phy_address<29>> equivalent to <phy_address<14>> has been removed
    Register <phy_address<58>> equivalent to <phy_address<13>> has been removed
    Register <phy_address<43>> equivalent to <phy_address<13>> has been removed
    Register <phy_address<28>> equivalent to <phy_address<13>> has been removed
    Register <phy_address<57>> equivalent to <phy_address<12>> has been removed
    Register <phy_address<42>> equivalent to <phy_address<12>> has been removed
    Register <phy_address<27>> equivalent to <phy_address<12>> has been removed
    Register <phy_address<56>> equivalent to <phy_address<11>> has been removed
    Register <phy_address<41>> equivalent to <phy_address<11>> has been removed
    Register <phy_address<26>> equivalent to <phy_address<11>> has been removed
    Register <calib_cmd_wren> equivalent to <calib_ctl_wren> has been removed
    Register <phy_address<54>> equivalent to <phy_address<9>> has been removed
    Register <phy_address<39>> equivalent to <phy_address<9>> has been removed
    Register <phy_address<24>> equivalent to <phy_address<9>> has been removed
    Register <phy_bank<11>> equivalent to <phy_bank<2>> has been removed
    Register <phy_bank<8>> equivalent to <phy_bank<2>> has been removed
    Register <phy_bank<5>> equivalent to <phy_bank<2>> has been removed
    Register <phy_bank<10>> equivalent to <phy_bank<1>> has been removed
    Register <phy_bank<7>> equivalent to <phy_bank<1>> has been removed
    Register <phy_bank<4>> equivalent to <phy_bank<1>> has been removed
    Register <phy_bank<9>> equivalent to <phy_bank<0>> has been removed
    Register <phy_bank<6>> equivalent to <phy_bank<0>> has been removed
    Register <phy_bank<3>> equivalent to <phy_bank<0>> has been removed
    Register <phy_address<46>> equivalent to <phy_address<1>> has been removed
    Register <phy_address<31>> equivalent to <phy_address<1>> has been removed
    Register <phy_address<16>> equivalent to <phy_address<1>> has been removed
    Register <phy_address<45>> equivalent to <phy_address<0>> has been removed
    Register <phy_address<30>> equivalent to <phy_address<0>> has been removed
    Register <phy_address<15>> equivalent to <phy_address<0>> has been removed
    Register <phy_address<53>> equivalent to <phy_address<8>> has been removed
    Register <phy_address<38>> equivalent to <phy_address<8>> has been removed
    Register <phy_address<23>> equivalent to <phy_address<8>> has been removed
    Register <phy_address<52>> equivalent to <phy_address<7>> has been removed
    Register <phy_address<37>> equivalent to <phy_address<7>> has been removed
    Register <phy_address<22>> equivalent to <phy_address<7>> has been removed
    Register <phy_address<51>> equivalent to <phy_address<6>> has been removed
    Register <phy_address<36>> equivalent to <phy_address<6>> has been removed
    Register <phy_address<21>> equivalent to <phy_address<6>> has been removed
    Register <phy_address<50>> equivalent to <phy_address<5>> has been removed
    Register <phy_address<35>> equivalent to <phy_address<5>> has been removed
    Register <phy_address<20>> equivalent to <phy_address<5>> has been removed
    Register <phy_address<49>> equivalent to <phy_address<4>> has been removed
    Register <phy_address<34>> equivalent to <phy_address<4>> has been removed
    Register <phy_address<19>> equivalent to <phy_address<4>> has been removed
    Register <phy_address<48>> equivalent to <phy_address<3>> has been removed
    Register <phy_address<33>> equivalent to <phy_address<3>> has been removed
    Register <phy_address<18>> equivalent to <phy_address<3>> has been removed
    Register <phy_address<47>> equivalent to <phy_address<2>> has been removed
    Register <phy_address<32>> equivalent to <phy_address<2>> has been removed
    Register <phy_address<17>> equivalent to <phy_address<2>> has been removed
    Register <phy_address<55>> equivalent to <phy_address<10>> has been removed
    Register <phy_address<40>> equivalent to <phy_address<10>> has been removed
    Register <phy_address<25>> equivalent to <phy_address<10>> has been removed
    Found 1-bit register for signal <phy_reset_n>.
    Found 1-bit register for signal <prbs_rdlvl_done_r1>.
    Found 1-bit register for signal <wrcal_resume_r>.
    Found 1-bit register for signal <mpr_end_if_reset>.
    Found 1-bit register for signal <calib_writes>.
    Found 1-bit register for signal <wrcal_rd_wait>.
    Found 1-bit register for signal <init_complete_r>.
    Found 1-bit register for signal <init_complete_r1>.
    Found 1-bit register for signal <init_complete_r2>.
    Found 1-bit register for signal <init_calib_complete>.
    Found 1-bit register for signal <pi_phaselock_start>.
    Found 1-bit register for signal <rdlvl_last_byte_done_r>.
    Found 1-bit register for signal <prbs_last_byte_done_r>.
    Found 15-bit register for signal <rdlvl_start_dly0_r<14:0>>.
    Found 15-bit register for signal <wrcal_start_dly_r>.
    Found 15-bit register for signal <oclkdelay_start_dly_r>.
    Found 16-bit register for signal <prech_done_dly_r>.
    Found 1-bit register for signal <prech_done>.
    Found 1-bit register for signal <mpr_rdlvl_start>.
    Found 1-bit register for signal <phy_if_empty_r>.
    Found 1-bit register for signal <prbs_gen_clk_en>.
    Found 1-bit register for signal <rdlvl_stg1_start>.
    Found 1-bit register for signal <rdlvl_stg1_start_int>.
    Found 1-bit register for signal <rdlvl_start_pre>.
    Found 1-bit register for signal <prbs_rdlvl_start>.
    Found 1-bit register for signal <pi_dqs_found_start>.
    Found 1-bit register for signal <wrcal_start>.
    Found 1-bit register for signal <oclkdelay_calib_start>.
    Found 1-bit register for signal <pi_dqs_found_done_r1>.
    Found 1-bit register for signal <wrlvl_final_if_rst>.
    Found 1-bit register for signal <wrlvl_odt_ctl>.
    Found 5-bit register for signal <enable_wrlvl_cnt>.
    Found 1-bit register for signal <wrlvl_odt>.
    Found 1-bit register for signal <wrlvl_active>.
    Found 1-bit register for signal <wr_level_dqs_asrt>.
    Found 2-bit register for signal <dqs_asrt_cnt>.
    Found 1-bit register for signal <wr_lvl_start>.
    Found 1-bit register for signal <wl_sm_start>.
    Found 1-bit register for signal <wrlvl_active_r1>.
    Found 1-bit register for signal <wr_level_dqs_asrt_r1>.
    Found 1-bit register for signal <wrlvl_done_r>.
    Found 1-bit register for signal <wrlvl_done_r1>.
    Found 1-bit register for signal <wrlvl_rank_done_r1>.
    Found 1-bit register for signal <wrlvl_rank_done_r2>.
    Found 1-bit register for signal <wrlvl_rank_done_r3>.
    Found 1-bit register for signal <wrlvl_rank_done_r4>.
    Found 1-bit register for signal <wrlvl_rank_done_r5>.
    Found 1-bit register for signal <wrlvl_rank_done_r6>.
    Found 1-bit register for signal <wrlvl_rank_done_r7>.
    Found 1-bit register for signal <prech_req_r>.
    Found 1-bit register for signal <prech_req_posedge_r>.
    Found 1-bit register for signal <prech_pending_r>.
    Found 7-bit register for signal <cnt_cmd_r>.
    Found 1-bit register for signal <cnt_cmd_done_r>.
    Found 4-bit register for signal <cnt_wait>.
    Found 1-bit register for signal <cnt_wrcal_rd>.
    Found 1-bit register for signal <temp_lmr_done>.
    Found 1-bit register for signal <temp_wrcal_done_r>.
    Found 14-bit register for signal <tg_timer>.
    Found 1-bit register for signal <tg_timer_done>.
    Found 1-bit register for signal <no_rst_tg_mc>.
    Found 1-bit register for signal <detect_pi_found_dqs>.
    Found 10-bit register for signal <cnt_pwron_ce_r>.
    Found 1-bit register for signal <pwron_ce_r>.
    Found 9-bit register for signal <cnt_pwron_r>.
    Found 1-bit register for signal <cnt_pwron_reset_done_r>.
    Found 1-bit register for signal <cnt_pwron_cke_done_r>.
    Found 8-bit register for signal <cnt_txpr_r>.
    Found 1-bit register for signal <cnt_txpr_done_r>.
    Found 8-bit register for signal <cnt_dllk_zqinit_r>.
    Found 1-bit register for signal <cnt_dllk_zqinit_done_r>.
    Found 2-bit register for signal <cnt_init_mr_r>.
    Found 1-bit register for signal <cnt_init_mr_done_r>.
    Found 1-bit register for signal <ddr2_pre_flag_r>.
    Found 1-bit register for signal <ddr2_refresh_flag_r>.
    Found 2-bit register for signal <cnt_init_af_r>.
    Found 1-bit register for signal <cnt_init_af_done_r>.
    Found 3-bit register for signal <reg_ctrl_cnt_r>.
    Found 1-bit register for signal <stg1_wr_done>.
    Found 4-bit register for signal <num_refresh>.
    Found 6-bit register for signal <init_state_r>.
    Found 6-bit register for signal <init_state_r1>.
    Found 1-bit register for signal <mem_init_done_r>.
    Found 1-bit register for signal <write_calib>.
    Found 1-bit register for signal <read_calib>.
    Found 1-bit register for signal <pi_calib_done_r>.
    Found 1-bit register for signal <pi_calib_rank_done_r>.
    Found 14-bit register for signal <pi_phaselock_timer>.
    Found 1-bit register for signal <ddr3_lm_done_r>.
    Found 1-bit register for signal <pi_phase_locked_all_r1>.
    Found 1-bit register for signal <pi_phase_locked_all_r2>.
    Found 1-bit register for signal <pi_phase_locked_all_r3>.
    Found 1-bit register for signal <pi_phase_locked_all_r4>.
    Found 1-bit register for signal <pi_calib_done_r1>.
    Found 4-bit register for signal <phy_int_cs_n>.
    Found 1-bit register for signal <burst_addr_r>.
    Found 9-bit register for signal <stg1_wr_rd_cnt>.
    Found 4-bit register for signal <oclk_wr_cnt>.
    Found 4-bit register for signal <wrcal_wr_cnt>.
    Found 3-bit register for signal <num_reads>.
    Found 8-bit register for signal <wrcal_reads>.
    Found 1-bit register for signal <calib_wrdata_en>.
    Found 1-bit register for signal <extend_cal_pat>.
    Found 1-bit register for signal <first_rdlvl_pat_r>.
    Found 1-bit register for signal <first_wrcal_pat_r>.
    Found 256-bit register for signal <phy_wrdata>.
    Found 1-bit register for signal <phy_ras_n<1>>.
    Found 1-bit register for signal <phy_cas_n<1>>.
    Found 1-bit register for signal <phy_we_n<1>>.
    Found 3-bit register for signal <calib_cmd>.
    Found 6-bit register for signal <calib_data_offset_0>.
    Found 6-bit register for signal <calib_data_offset_1>.
    Found 6-bit register for signal <calib_data_offset_2>.
    Found 1-bit register for signal <calib_ctl_wren>.
    Found 2-bit register for signal <calib_seq>.
    Found 1-bit register for signal <mr2_r<0><1>>.
    Found 1-bit register for signal <mr2_r<0><0>>.
    Found 1-bit register for signal <mr1_r<0><2>>.
    Found 1-bit register for signal <mr1_r<0><1>>.
    Found 1-bit register for signal <mr1_r<0><0>>.
    Found 8-bit register for signal <n1040>.
    Found 12-bit register for signal <n1041>.
    Found 4-bit register for signal <phy_tmp_odt_r>.
    Found 4-bit register for signal <calib_cke>.
    Found 2-bit register for signal <calib_odt>.
    Found 1-bit register for signal <phy_address<14>>.
    Found 1-bit register for signal <phy_address<13>>.
    Found 1-bit register for signal <phy_address<12>>.
    Found 1-bit register for signal <phy_address<11>>.
    Found 1-bit register for signal <phy_address<10>>.
    Found 1-bit register for signal <phy_address<9>>.
    Found 1-bit register for signal <phy_address<8>>.
    Found 1-bit register for signal <phy_address<7>>.
    Found 1-bit register for signal <phy_address<6>>.
    Found 1-bit register for signal <phy_address<5>>.
    Found 1-bit register for signal <phy_address<4>>.
    Found 1-bit register for signal <phy_address<3>>.
    Found 1-bit register for signal <phy_address<2>>.
    Found 1-bit register for signal <phy_address<1>>.
    Found 1-bit register for signal <phy_address<0>>.
    Found 1-bit register for signal <phy_bank<2>>.
    Found 1-bit register for signal <phy_bank<1>>.
    Found 1-bit register for signal <phy_bank<0>>.
    Found 1-bit register for signal <rdlvl_stg1_done_r1>.
INFO:Xst:1799 - State 011000 is never reached in FSM <init_state_r>.
INFO:Xst:1799 - State 011100 is never reached in FSM <init_state_r>.
INFO:Xst:1799 - State 011011 is never reached in FSM <init_state_r>.
INFO:Xst:1799 - State 011110 is never reached in FSM <init_state_r>.
INFO:Xst:1799 - State 010111 is never reached in FSM <init_state_r>.
    Found finite state machine <FSM_1> for signal <init_state_r>.
    -----------------------------------------------------------------------
    | States             | 50                                             |
    | Transitions        | 211                                            |
    | Inputs             | 59                                             |
    | Outputs            | 48                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit adder for signal <dqs_asrt_cnt[1]_GND_100_o_add_88_OUT> created at line 1173.
    Found 7-bit adder for signal <cnt_cmd_r[6]_cnt_cmd_r[6]_mux_102_OUT> created at line 1283.
    Found 4-bit adder for signal <cnt_wait[3]_cnt_wait[3]_mux_133_OUT> created at line 1310.
    Found 10-bit adder for signal <cnt_pwron_ce_r[9]_GND_100_o_add_160_OUT> created at line 1393.
    Found 9-bit adder for signal <cnt_pwron_r[8]_GND_100_o_add_165_OUT> created at line 1402.
    Found 8-bit adder for signal <cnt_txpr_r[7]_GND_100_o_add_174_OUT> created at line 1455.
    Found 8-bit adder for signal <cnt_dllk_zqinit_r[7]_cnt_dllk_zqinit_r[7]_mux_187_OUT> created at line 1486.
    Found 2-bit adder for signal <cnt_init_mr_r[1]_GND_100_o_add_194_OUT> created at line 1507.
    Found 2-bit adder for signal <cnt_init_af_r[1]_GND_100_o_add_210_OUT> created at line 1558.
    Found 3-bit adder for signal <reg_ctrl_cnt_r[2]_GND_100_o_add_218_OUT> created at line 1571.
    Found 4-bit adder for signal <num_refresh[3]_GND_100_o_add_232_OUT> created at line 1607.
    Found 14-bit adder for signal <pi_phaselock_timer[13]_GND_100_o_add_344_OUT> created at line 2253.
    Found 2-bit adder for signal <calib_seq[1]_GND_100_o_add_533_OUT> created at line 3315.
    Found 10-bit adder for signal <phy_address[9]_GND_100_o_add_625_OUT> created at line 4433.
    Found 5-bit subtractor for signal <GND_100_o_GND_100_o_sub_75_OUT<4:0>> created at line 1122.
    Found 9-bit subtractor for signal <GND_100_o_GND_100_o_sub_400_OUT<8:0>> created at line 2652.
    Found 4-bit subtractor for signal <GND_100_o_GND_100_o_sub_409_OUT<3:0>> created at line 2663.
    Found 4-bit subtractor for signal <GND_100_o_GND_100_o_sub_417_OUT<3:0>> created at line 2674.
    Found 3-bit subtractor for signal <GND_100_o_GND_100_o_sub_424_OUT<2:0>> created at line 2685.
    Found 8-bit subtractor for signal <GND_100_o_GND_100_o_sub_433_OUT<7:0>> created at line 2708.
    Found 3x2-bit multiplier for signal <n1193> created at line 3285.
    Found 6-bit shifter logical right for signal <rd_data_offset_ranks_0[5]_PWR_96_o_shift_right_504_OUT> created at line 3285
    Found 6-bit shifter logical right for signal <rd_data_offset_ranks_1[5]_PWR_96_o_shift_right_506_OUT> created at line 3286
    Found 6-bit shifter logical right for signal <rd_data_offset_ranks_2[5]_PWR_96_o_shift_right_508_OUT> created at line 3287
    Found 4x3-bit Read Only RAM for signal <cnt_init_mr_r[1]_GND_100_o_wide_mux_602_OUT>
    Found 15-bit 4-to-1 multiplexer for signal <cnt_init_mr_r[1]_load_mr0[14]_wide_mux_603_OUT> created at line 4315.
    Found 2-bit comparator greater for signal <n0392> created at line 1754
    WARNING:Xst:2404 -  FFs/Latches <init_wrcal_done<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <tg_timer_go<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <chip_cnt_r<14:13>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <new_burst_r<0:0>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_ras_n<3><0:0>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_ras_n<2><3:3>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_cas_n<3><2:2>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_cas_n<2><3:3>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_we_n<3><2:2>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_we_n<2><3:3>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_ras_n<0><2:2>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_cas_n<0><0:0>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_we_n<0><0:0>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <calib_cas_slot<1:1>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <calib_cas_slot<1:1>> (without init value) have a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>.
    WARNING:Xst:2404 -  FFs/Latches <phy_data_full_r<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Multiplier(s).
	inferred  20 Adder/Subtractor(s).
	inferred 607 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred 113 Multiplexer(s).
	inferred   3 Combinational logic shifter(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_init> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_wrcal>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrcal.v".
        TCQ = 100
        nCK_PER_CLK = 4
        CLK_PERIOD = 6664
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_WIDTH = 8
        SIM_CAL_OPTION = "NONE"
        PRE_REV3ES = "OFF"
        PO_TAP_DLY = 1
    Set property "syn_maxfan = 10" for signal <wrcal_dqs_cnt_r>.
    Set property "KEEP = TRUE" for signal <wrcal_dqs_cnt_r>.
    Set property "MAX_FANOUT = 10" for signal <wrcal_dqs_cnt_r>.
    Set property "syn_maxfan = 3" for signal <dqs_po_stg2_c_incdec>.
    Set property "KEEP = TRUE" for signal <dqs_po_stg2_c_incdec>.
    Set property "MAX_FANOUT = 3" for signal <dqs_po_stg2_c_incdec>.
WARNING:Xst:653 - Signal <dbg_phy_wrcal<99:73>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dbg_phy_wrcal<53:50>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dbg_phy_wrcal<16:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dbg_phy_wrcal<12:9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Register <early2_match_rise2_r<4>> equivalent to <pat_match_rise2_r<4>> has been removed
    Register <early1_match_rise2_r<4>> equivalent to <pat_match_rise2_r<4>> has been removed
    Register <early2_match_rise2_r<3>> equivalent to <early1_match_rise2_r<3>> has been removed
    Register <early2_match_fall3_r<1>> equivalent to <early1_match_fall3_r<1>> has been removed
    Register <early1_match_rise3_r<6>> equivalent to <pat_match_rise3_r<6>> has been removed
    Register <early2_match_rise2_r<7>> equivalent to <early1_match_rise2_r<7>> has been removed
    Register <early2_match_fall3_r<6>> equivalent to <pat_match_fall3_r<6>> has been removed
    Register <early2_match_rise1_r<6>> equivalent to <pat_match_rise1_r<6>> has been removed
    Register <early2_match_fall2_r<6>> equivalent to <pat_match_fall2_r<6>> has been removed
    Register <early2_match_rise0_r<0>> equivalent to <pat_match_rise0_r<0>> has been removed
    Register <early2_match_fall1_r<0>> equivalent to <early1_match_fall1_r<0>> has been removed
    Register <early1_match_rise2_r<5>> equivalent to <pat_match_rise2_r<5>> has been removed
    Register <early1_match_rise0_r<3>> equivalent to <pat_match_rise0_r<3>> has been removed
    Register <early2_match_rise3_r<5>> equivalent to <early1_match_rise3_r<5>> has been removed
    Register <early2_match_rise0_r<2>> equivalent to <pat_match_rise0_r<2>> has been removed
    Register <early1_match_rise3_r<4>> equivalent to <pat_match_rise3_r<4>> has been removed
    Register <early1_match_fall2_r<1>> equivalent to <pat_match_fall2_r<1>> has been removed
    Register <early1_match_rise0_r<1>> equivalent to <pat_match_rise0_r<1>> has been removed
    Register <early2_match_rise0_r<6>> equivalent to <pat_match_rise0_r<6>> has been removed
    Register <early1_match_rise0_r<5>> equivalent to <pat_match_rise0_r<5>> has been removed
    Register <early2_match_rise1_r<1>> equivalent to <early1_match_rise1_r<1>> has been removed
    Register <early2_match_rise3_r<7>> equivalent to <pat_match_rise3_r<7>> has been removed
    Register <early1_match_rise3_r<7>> equivalent to <pat_match_rise3_r<7>> has been removed
    Register <early2_match_rise0_r<4>> equivalent to <pat_match_rise0_r<4>> has been removed
    Register <early2_match_fall0_r<4>> equivalent to <pat_match_fall0_r<4>> has been removed
    Register <early2_match_fall3_r<5>> equivalent to <early1_match_fall3_r<5>> has been removed
    Register <early1_match_fall2_r<0>> equivalent to <pat_match_fall2_r<0>> has been removed
    Register <early2_match_fall1_r<7>> equivalent to <pat_match_fall1_r<7>> has been removed
    Register <early1_match_rise0_r<7>> equivalent to <pat_match_rise0_r<7>> has been removed
    Register <early2_match_fall0_r<0>> equivalent to <pat_match_fall0_r<0>> has been removed
    Register <early2_match_rise2_r<0>> equivalent to <pat_match_rise2_r<0>> has been removed
    Register <early1_match_rise2_r<0>> equivalent to <pat_match_rise2_r<0>> has been removed
    Register <early1_match_fall2_r<4>> equivalent to <pat_match_fall2_r<4>> has been removed
    Register <early1_match_fall0_r<5>> equivalent to <pat_match_fall0_r<5>> has been removed
    Register <early2_match_fall3_r<2>> equivalent to <pat_match_fall3_r<2>> has been removed
    Register <early1_match_fall0_r<7>> equivalent to <pat_match_fall0_r<7>> has been removed
    Register <early2_match_fall1_r<4>> equivalent to <early1_match_fall1_r<4>> has been removed
    Register <early2_match_fall2_r<7>> equivalent to <early1_match_fall2_r<7>> has been removed
    Register <early2_match_fall0_r<2>> equivalent to <pat_match_fall0_r<2>> has been removed
    Register <early2_match_fall1_r<3>> equivalent to <pat_match_fall1_r<3>> has been removed
    Register <early2_match_fall1_r<2>> equivalent to <pat_match_fall1_r<2>> has been removed
    Register <early2_match_fall1_r<1>> equivalent to <early1_match_fall1_r<1>> has been removed
    Register <early1_match_fall0_r<1>> equivalent to <pat_match_fall0_r<1>> has been removed
    Register <early2_match_fall1_r<5>> equivalent to <early1_match_fall1_r<5>> has been removed
    Register <early1_match_fall2_r<5>> equivalent to <pat_match_fall2_r<5>> has been removed
    Register <early2_match_rise2_r<2>> equivalent to <early1_match_rise2_r<2>> has been removed
    Register <early2_match_fall3_r<3>> equivalent to <pat_match_fall3_r<3>> has been removed
    Register <early1_match_fall3_r<3>> equivalent to <pat_match_fall3_r<3>> has been removed
    Register <early1_match_rise3_r<2>> equivalent to <pat_match_rise3_r<2>> has been removed
    Register <early2_match_rise1_r<2>> equivalent to <pat_match_rise1_r<2>> has been removed
    Register <early2_match_fall3_r<7>> equivalent to <pat_match_fall3_r<7>> has been removed
    Register <early1_match_fall3_r<7>> equivalent to <pat_match_fall3_r<7>> has been removed
    Register <early2_match_fall1_r<6>> equivalent to <pat_match_fall1_r<6>> has been removed
    Register <early2_match_fall2_r<2>> equivalent to <pat_match_fall2_r<2>> has been removed
    Register <early2_match_rise1_r<0>> equivalent to <early1_match_rise1_r<0>> has been removed
    Register <po_stg2_wrcal_cnt> equivalent to <rd_mux_sel_r> has been removed
    Register <early2_match_rise1_r<4>> equivalent to <early1_match_rise1_r<4>> has been removed
    Register <early1_match_rise3_r<0>> equivalent to <pat_match_rise3_r<0>> has been removed
    Register <early2_match_rise1_r<3>> equivalent to <pat_match_rise1_r<3>> has been removed
    Register <early2_match_fall2_r<3>> equivalent to <early1_match_fall2_r<3>> has been removed
    Register <early2_match_rise1_r<7>> equivalent to <pat_match_rise1_r<7>> has been removed
    Register <early2_match_rise3_r<3>> equivalent to <pat_match_rise3_r<3>> has been removed
    Register <early1_match_rise3_r<3>> equivalent to <pat_match_rise3_r<3>> has been removed
    Register <early2_match_rise2_r<6>> equivalent to <early1_match_rise2_r<6>> has been removed
    Register <early2_match_rise3_r<1>> equivalent to <early1_match_rise3_r<1>> has been removed
    Register <early1_match_fall0_r<3>> equivalent to <pat_match_fall0_r<3>> has been removed
    Register <early2_match_fall3_r<0>> equivalent to <pat_match_fall3_r<0>> has been removed
    Register <early1_match_rise2_r<1>> equivalent to <pat_match_rise2_r<1>> has been removed
    Register <early2_match_rise1_r<5>> equivalent to <early1_match_rise1_r<5>> has been removed
    Register <early2_match_fall3_r<4>> equivalent to <pat_match_fall3_r<4>> has been removed
    Register <early2_match_fall0_r<6>> equivalent to <pat_match_fall0_r<6>> has been removed
    Register <pat_data_match_valid_r> equivalent to <rd_active_r4> has been removed
    Found 1-bit register for signal <wrlvl_byte_done_r>.
    Found 12-bit register for signal <po_coarse_tap_cnt>.
    Found 24-bit register for signal <po_fine_tap_cnt>.
    Found 4-bit register for signal <no_po_fine_taps_left>.
    Found 3-bit register for signal <rd_mux_sel_r>.
    Found 1-bit register for signal <mux_rd_rise0_r<0>>.
    Found 1-bit register for signal <mux_rd_fall0_r<0>>.
    Found 1-bit register for signal <mux_rd_rise1_r<0>>.
    Found 1-bit register for signal <mux_rd_fall1_r<0>>.
    Found 1-bit register for signal <mux_rd_rise2_r<0>>.
    Found 1-bit register for signal <mux_rd_fall2_r<0>>.
    Found 1-bit register for signal <mux_rd_rise3_r<0>>.
    Found 1-bit register for signal <mux_rd_fall3_r<0>>.
    Found 1-bit register for signal <mux_rd_rise0_r<1>>.
    Found 1-bit register for signal <mux_rd_fall0_r<1>>.
    Found 1-bit register for signal <mux_rd_rise1_r<1>>.
    Found 1-bit register for signal <mux_rd_fall1_r<1>>.
    Found 1-bit register for signal <mux_rd_rise2_r<1>>.
    Found 1-bit register for signal <mux_rd_fall2_r<1>>.
    Found 1-bit register for signal <mux_rd_rise3_r<1>>.
    Found 1-bit register for signal <mux_rd_fall3_r<1>>.
    Found 1-bit register for signal <mux_rd_rise0_r<2>>.
    Found 1-bit register for signal <mux_rd_fall0_r<2>>.
    Found 1-bit register for signal <mux_rd_rise1_r<2>>.
    Found 1-bit register for signal <mux_rd_fall1_r<2>>.
    Found 1-bit register for signal <mux_rd_rise2_r<2>>.
    Found 1-bit register for signal <mux_rd_fall2_r<2>>.
    Found 1-bit register for signal <mux_rd_rise3_r<2>>.
    Found 1-bit register for signal <mux_rd_fall3_r<2>>.
    Found 1-bit register for signal <mux_rd_rise0_r<3>>.
    Found 1-bit register for signal <mux_rd_fall0_r<3>>.
    Found 1-bit register for signal <mux_rd_rise1_r<3>>.
    Found 1-bit register for signal <mux_rd_fall1_r<3>>.
    Found 1-bit register for signal <mux_rd_rise2_r<3>>.
    Found 1-bit register for signal <mux_rd_fall2_r<3>>.
    Found 1-bit register for signal <mux_rd_rise3_r<3>>.
    Found 1-bit register for signal <mux_rd_fall3_r<3>>.
    Found 1-bit register for signal <mux_rd_rise0_r<4>>.
    Found 1-bit register for signal <mux_rd_fall0_r<4>>.
    Found 1-bit register for signal <mux_rd_rise1_r<4>>.
    Found 1-bit register for signal <mux_rd_fall1_r<4>>.
    Found 1-bit register for signal <mux_rd_rise2_r<4>>.
    Found 1-bit register for signal <mux_rd_fall2_r<4>>.
    Found 1-bit register for signal <mux_rd_rise3_r<4>>.
    Found 1-bit register for signal <mux_rd_fall3_r<4>>.
    Found 1-bit register for signal <mux_rd_rise0_r<5>>.
    Found 1-bit register for signal <mux_rd_fall0_r<5>>.
    Found 1-bit register for signal <mux_rd_rise1_r<5>>.
    Found 1-bit register for signal <mux_rd_fall1_r<5>>.
    Found 1-bit register for signal <mux_rd_rise2_r<5>>.
    Found 1-bit register for signal <mux_rd_fall2_r<5>>.
    Found 1-bit register for signal <mux_rd_rise3_r<5>>.
    Found 1-bit register for signal <mux_rd_fall3_r<5>>.
    Found 1-bit register for signal <mux_rd_rise0_r<6>>.
    Found 1-bit register for signal <mux_rd_fall0_r<6>>.
    Found 1-bit register for signal <mux_rd_rise1_r<6>>.
    Found 1-bit register for signal <mux_rd_fall1_r<6>>.
    Found 1-bit register for signal <mux_rd_rise2_r<6>>.
    Found 1-bit register for signal <mux_rd_fall2_r<6>>.
    Found 1-bit register for signal <mux_rd_rise3_r<6>>.
    Found 1-bit register for signal <mux_rd_fall3_r<6>>.
    Found 1-bit register for signal <mux_rd_rise0_r<7>>.
    Found 1-bit register for signal <mux_rd_fall0_r<7>>.
    Found 1-bit register for signal <mux_rd_rise1_r<7>>.
    Found 1-bit register for signal <mux_rd_fall1_r<7>>.
    Found 1-bit register for signal <mux_rd_rise2_r<7>>.
    Found 1-bit register for signal <mux_rd_fall2_r<7>>.
    Found 1-bit register for signal <mux_rd_rise3_r<7>>.
    Found 1-bit register for signal <mux_rd_fall3_r<7>>.
    Found 1-bit register for signal <wrcal_prech_req>.
    Found 1-bit register for signal <sr_rise0_r<0>>.
    Found 1-bit register for signal <sr_fall0_r<0>>.
    Found 1-bit register for signal <sr_rise1_r<0>>.
    Found 1-bit register for signal <sr_fall1_r<0>>.
    Found 1-bit register for signal <sr_rise2_r<0>>.
    Found 1-bit register for signal <sr_fall2_r<0>>.
    Found 1-bit register for signal <sr_rise3_r<0>>.
    Found 1-bit register for signal <sr_fall3_r<0>>.
    Found 1-bit register for signal <sr_rise0_r<1>>.
    Found 1-bit register for signal <sr_fall0_r<1>>.
    Found 1-bit register for signal <sr_rise1_r<1>>.
    Found 1-bit register for signal <sr_fall1_r<1>>.
    Found 1-bit register for signal <sr_rise2_r<1>>.
    Found 1-bit register for signal <sr_fall2_r<1>>.
    Found 1-bit register for signal <sr_rise3_r<1>>.
    Found 1-bit register for signal <sr_fall3_r<1>>.
    Found 1-bit register for signal <sr_rise0_r<2>>.
    Found 1-bit register for signal <sr_fall0_r<2>>.
    Found 1-bit register for signal <sr_rise1_r<2>>.
    Found 1-bit register for signal <sr_fall1_r<2>>.
    Found 1-bit register for signal <sr_rise2_r<2>>.
    Found 1-bit register for signal <sr_fall2_r<2>>.
    Found 1-bit register for signal <sr_rise3_r<2>>.
    Found 1-bit register for signal <sr_fall3_r<2>>.
    Found 1-bit register for signal <sr_rise0_r<3>>.
    Found 1-bit register for signal <sr_fall0_r<3>>.
    Found 1-bit register for signal <sr_rise1_r<3>>.
    Found 1-bit register for signal <sr_fall1_r<3>>.
    Found 1-bit register for signal <sr_rise2_r<3>>.
    Found 1-bit register for signal <sr_fall2_r<3>>.
    Found 1-bit register for signal <sr_rise3_r<3>>.
    Found 1-bit register for signal <sr_fall3_r<3>>.
    Found 1-bit register for signal <sr_rise0_r<4>>.
    Found 1-bit register for signal <sr_fall0_r<4>>.
    Found 1-bit register for signal <sr_rise1_r<4>>.
    Found 1-bit register for signal <sr_fall1_r<4>>.
    Found 1-bit register for signal <sr_rise2_r<4>>.
    Found 1-bit register for signal <sr_fall2_r<4>>.
    Found 1-bit register for signal <sr_rise3_r<4>>.
    Found 1-bit register for signal <sr_fall3_r<4>>.
    Found 1-bit register for signal <sr_rise0_r<5>>.
    Found 1-bit register for signal <sr_fall0_r<5>>.
    Found 1-bit register for signal <sr_rise1_r<5>>.
    Found 1-bit register for signal <sr_fall1_r<5>>.
    Found 1-bit register for signal <sr_rise2_r<5>>.
    Found 1-bit register for signal <sr_fall2_r<5>>.
    Found 1-bit register for signal <sr_rise3_r<5>>.
    Found 1-bit register for signal <sr_fall3_r<5>>.
    Found 1-bit register for signal <sr_rise0_r<6>>.
    Found 1-bit register for signal <sr_fall0_r<6>>.
    Found 1-bit register for signal <sr_rise1_r<6>>.
    Found 1-bit register for signal <sr_fall1_r<6>>.
    Found 1-bit register for signal <sr_rise2_r<6>>.
    Found 1-bit register for signal <sr_fall2_r<6>>.
    Found 1-bit register for signal <sr_rise3_r<6>>.
    Found 1-bit register for signal <sr_fall3_r<6>>.
    Found 1-bit register for signal <sr_rise0_r<7>>.
    Found 1-bit register for signal <sr_fall0_r<7>>.
    Found 1-bit register for signal <sr_rise1_r<7>>.
    Found 1-bit register for signal <sr_fall1_r<7>>.
    Found 1-bit register for signal <sr_rise2_r<7>>.
    Found 1-bit register for signal <sr_fall2_r<7>>.
    Found 1-bit register for signal <sr_rise3_r<7>>.
    Found 1-bit register for signal <sr_fall3_r<7>>.
    Found 1-bit register for signal <rd_active_r>.
    Found 1-bit register for signal <rd_active_r1>.
    Found 1-bit register for signal <rd_active_r2>.
    Found 1-bit register for signal <rd_active_r3>.
    Found 1-bit register for signal <rd_active_r4>.
    Found 1-bit register for signal <pat_match_rise0_r<0>>.
    Found 1-bit register for signal <pat_match_fall0_r<0>>.
    Found 1-bit register for signal <pat_match_rise1_r<0>>.
    Found 1-bit register for signal <pat_match_fall1_r<0>>.
    Found 1-bit register for signal <pat_match_rise2_r<0>>.
    Found 1-bit register for signal <pat_match_fall2_r<0>>.
    Found 1-bit register for signal <pat_match_rise3_r<0>>.
    Found 1-bit register for signal <pat_match_fall3_r<0>>.
    Found 1-bit register for signal <early1_match_rise0_r<0>>.
    Found 1-bit register for signal <early1_match_fall0_r<0>>.
    Found 1-bit register for signal <early1_match_rise1_r<0>>.
    Found 1-bit register for signal <early1_match_fall1_r<0>>.
    Found 1-bit register for signal <early1_match_fall3_r<0>>.
    Found 1-bit register for signal <early2_match_fall2_r<0>>.
    Found 1-bit register for signal <early2_match_rise3_r<0>>.
    Found 1-bit register for signal <pat_match_rise0_r<1>>.
    Found 1-bit register for signal <pat_match_fall0_r<1>>.
    Found 1-bit register for signal <pat_match_rise1_r<1>>.
    Found 1-bit register for signal <pat_match_fall1_r<1>>.
    Found 1-bit register for signal <pat_match_rise2_r<1>>.
    Found 1-bit register for signal <pat_match_fall2_r<1>>.
    Found 1-bit register for signal <pat_match_rise3_r<1>>.
    Found 1-bit register for signal <pat_match_fall3_r<1>>.
    Found 1-bit register for signal <early1_match_rise1_r<1>>.
    Found 1-bit register for signal <early1_match_fall1_r<1>>.
    Found 1-bit register for signal <early1_match_rise3_r<1>>.
    Found 1-bit register for signal <early1_match_fall3_r<1>>.
    Found 1-bit register for signal <early2_match_rise0_r<1>>.
    Found 1-bit register for signal <early2_match_fall0_r<1>>.
    Found 1-bit register for signal <early2_match_rise2_r<1>>.
    Found 1-bit register for signal <early2_match_fall2_r<1>>.
    Found 1-bit register for signal <pat_match_rise0_r<2>>.
    Found 1-bit register for signal <pat_match_fall0_r<2>>.
    Found 1-bit register for signal <pat_match_rise1_r<2>>.
    Found 1-bit register for signal <pat_match_fall1_r<2>>.
    Found 1-bit register for signal <pat_match_rise2_r<2>>.
    Found 1-bit register for signal <pat_match_fall2_r<2>>.
    Found 1-bit register for signal <pat_match_rise3_r<2>>.
    Found 1-bit register for signal <pat_match_fall3_r<2>>.
    Found 1-bit register for signal <early1_match_rise0_r<2>>.
    Found 1-bit register for signal <early1_match_fall0_r<2>>.
    Found 1-bit register for signal <early1_match_rise1_r<2>>.
    Found 1-bit register for signal <early1_match_fall1_r<2>>.
    Found 1-bit register for signal <early1_match_rise2_r<2>>.
    Found 1-bit register for signal <early1_match_fall2_r<2>>.
    Found 1-bit register for signal <early1_match_fall3_r<2>>.
    Found 1-bit register for signal <early2_match_rise3_r<2>>.
    Found 1-bit register for signal <pat_match_rise0_r<3>>.
    Found 1-bit register for signal <pat_match_fall0_r<3>>.
    Found 1-bit register for signal <pat_match_rise1_r<3>>.
    Found 1-bit register for signal <pat_match_fall1_r<3>>.
    Found 1-bit register for signal <pat_match_rise2_r<3>>.
    Found 1-bit register for signal <pat_match_fall2_r<3>>.
    Found 1-bit register for signal <pat_match_rise3_r<3>>.
    Found 1-bit register for signal <pat_match_fall3_r<3>>.
    Found 1-bit register for signal <early1_match_rise1_r<3>>.
    Found 1-bit register for signal <early1_match_fall1_r<3>>.
    Found 1-bit register for signal <early1_match_rise2_r<3>>.
    Found 1-bit register for signal <early1_match_fall2_r<3>>.
    Found 1-bit register for signal <early2_match_rise0_r<3>>.
    Found 1-bit register for signal <early2_match_fall0_r<3>>.
    Found 1-bit register for signal <pat_match_rise0_r<4>>.
    Found 1-bit register for signal <pat_match_fall0_r<4>>.
    Found 1-bit register for signal <pat_match_rise1_r<4>>.
    Found 1-bit register for signal <pat_match_fall1_r<4>>.
    Found 1-bit register for signal <pat_match_rise2_r<4>>.
    Found 1-bit register for signal <pat_match_fall2_r<4>>.
    Found 1-bit register for signal <pat_match_rise3_r<4>>.
    Found 1-bit register for signal <pat_match_fall3_r<4>>.
    Found 1-bit register for signal <early1_match_rise0_r<4>>.
    Found 1-bit register for signal <early1_match_fall0_r<4>>.
    Found 1-bit register for signal <early1_match_rise1_r<4>>.
    Found 1-bit register for signal <early1_match_fall1_r<4>>.
    Found 1-bit register for signal <early1_match_fall3_r<4>>.
    Found 1-bit register for signal <early2_match_fall2_r<4>>.
    Found 1-bit register for signal <early2_match_rise3_r<4>>.
    Found 1-bit register for signal <pat_match_rise0_r<5>>.
    Found 1-bit register for signal <pat_match_fall0_r<5>>.
    Found 1-bit register for signal <pat_match_rise1_r<5>>.
    Found 1-bit register for signal <pat_match_fall1_r<5>>.
    Found 1-bit register for signal <pat_match_rise2_r<5>>.
    Found 1-bit register for signal <pat_match_fall2_r<5>>.
    Found 1-bit register for signal <pat_match_rise3_r<5>>.
    Found 1-bit register for signal <pat_match_fall3_r<5>>.
    Found 1-bit register for signal <early1_match_rise1_r<5>>.
    Found 1-bit register for signal <early1_match_fall1_r<5>>.
    Found 1-bit register for signal <early1_match_rise3_r<5>>.
    Found 1-bit register for signal <early1_match_fall3_r<5>>.
    Found 1-bit register for signal <early2_match_rise0_r<5>>.
    Found 1-bit register for signal <early2_match_fall0_r<5>>.
    Found 1-bit register for signal <early2_match_rise2_r<5>>.
    Found 1-bit register for signal <early2_match_fall2_r<5>>.
    Found 1-bit register for signal <pat_match_rise0_r<6>>.
    Found 1-bit register for signal <pat_match_fall0_r<6>>.
    Found 1-bit register for signal <pat_match_rise1_r<6>>.
    Found 1-bit register for signal <pat_match_fall1_r<6>>.
    Found 1-bit register for signal <pat_match_rise2_r<6>>.
    Found 1-bit register for signal <pat_match_fall2_r<6>>.
    Found 1-bit register for signal <pat_match_rise3_r<6>>.
    Found 1-bit register for signal <pat_match_fall3_r<6>>.
    Found 1-bit register for signal <early1_match_rise0_r<6>>.
    Found 1-bit register for signal <early1_match_fall0_r<6>>.
    Found 1-bit register for signal <early1_match_rise1_r<6>>.
    Found 1-bit register for signal <early1_match_fall1_r<6>>.
    Found 1-bit register for signal <early1_match_rise2_r<6>>.
    Found 1-bit register for signal <early1_match_fall2_r<6>>.
    Found 1-bit register for signal <early1_match_fall3_r<6>>.
    Found 1-bit register for signal <early2_match_rise3_r<6>>.
    Found 1-bit register for signal <pat_match_rise0_r<7>>.
    Found 1-bit register for signal <pat_match_fall0_r<7>>.
    Found 1-bit register for signal <pat_match_rise1_r<7>>.
    Found 1-bit register for signal <pat_match_fall1_r<7>>.
    Found 1-bit register for signal <pat_match_rise2_r<7>>.
    Found 1-bit register for signal <pat_match_fall2_r<7>>.
    Found 1-bit register for signal <pat_match_rise3_r<7>>.
    Found 1-bit register for signal <pat_match_fall3_r<7>>.
    Found 1-bit register for signal <early1_match_rise1_r<7>>.
    Found 1-bit register for signal <early1_match_fall1_r<7>>.
    Found 1-bit register for signal <early1_match_rise2_r<7>>.
    Found 1-bit register for signal <early1_match_fall2_r<7>>.
    Found 1-bit register for signal <early2_match_rise0_r<7>>.
    Found 1-bit register for signal <early2_match_fall0_r<7>>.
    Found 1-bit register for signal <pat_match_rise0_and_r>.
    Found 1-bit register for signal <pat_match_fall0_and_r>.
    Found 1-bit register for signal <pat_match_rise1_and_r>.
    Found 1-bit register for signal <pat_match_fall1_and_r>.
    Found 1-bit register for signal <pat_match_rise2_and_r>.
    Found 1-bit register for signal <pat_match_fall2_and_r>.
    Found 1-bit register for signal <pat_match_rise3_and_r>.
    Found 1-bit register for signal <pat_match_fall3_and_r>.
    Found 1-bit register for signal <pat_data_match_r>.
    Found 1-bit register for signal <early1_match_rise0_and_r>.
    Found 1-bit register for signal <early1_match_fall0_and_r>.
    Found 1-bit register for signal <early1_match_rise1_and_r>.
    Found 1-bit register for signal <early1_match_fall1_and_r>.
    Found 1-bit register for signal <early1_match_rise2_and_r>.
    Found 1-bit register for signal <early1_match_fall2_and_r>.
    Found 1-bit register for signal <early1_match_rise3_and_r>.
    Found 1-bit register for signal <early1_match_fall3_and_r>.
    Found 1-bit register for signal <early1_data_match_r>.
    Found 1-bit register for signal <early2_match_rise0_and_r>.
    Found 1-bit register for signal <early2_match_fall0_and_r>.
    Found 1-bit register for signal <early2_match_rise1_and_r>.
    Found 1-bit register for signal <early2_match_fall1_and_r>.
    Found 1-bit register for signal <early2_match_rise2_and_r>.
    Found 1-bit register for signal <early2_match_fall2_and_r>.
    Found 1-bit register for signal <early2_match_rise3_and_r>.
    Found 1-bit register for signal <early2_match_fall3_and_r>.
    Found 1-bit register for signal <early2_data_match_r>.
    Found 1-bit register for signal <wrcal_pat_resume_r1>.
    Found 1-bit register for signal <wrcal_pat_resume_r2>.
    Found 1-bit register for signal <wrcal_pat_resume_r3>.
    Found 1-bit register for signal <dqs_po_stg2_c_incdec_r>.
    Found 1-bit register for signal <dqs_po_en_stg2_c_r>.
    Found 1-bit register for signal <dqs_wcal_po_stg2_f_incdec_r>.
    Found 1-bit register for signal <dqs_wcal_po_en_stg2_f_r>.
    Found 1-bit register for signal <dqs_po_stg2_c_incdec>.
    Found 1-bit register for signal <dqs_po_en_stg2_c>.
    Found 1-bit register for signal <dqs_wcal_po_stg2_f_incdec>.
    Found 1-bit register for signal <dqs_wcal_po_en_stg2_f>.
    Found 4-bit register for signal <tap_inc_wait_cnt>.
    Found 5-bit register for signal <not_empty_wait_cnt>.
    Found 1-bit register for signal <dec_taps>.
    Found 3-bit register for signal <cal2_rd_cnt>.
    Found 3-bit register for signal <wrcal_dqs_cnt_r>.
    Found 1-bit register for signal <cal2_done_r>.
    Found 1-bit register for signal <cal2_prech_req_r>.
    Found 5-bit register for signal <cal2_state_r>.
    Found 1-bit register for signal <cal2_corse_cnt<11>>.
    Found 1-bit register for signal <cal2_corse_cnt<10>>.
    Found 1-bit register for signal <cal2_corse_cnt<9>>.
    Found 1-bit register for signal <cal2_corse_cnt<8>>.
    Found 1-bit register for signal <cal2_corse_cnt<7>>.
    Found 1-bit register for signal <cal2_corse_cnt<6>>.
    Found 1-bit register for signal <cal2_corse_cnt<5>>.
    Found 1-bit register for signal <cal2_corse_cnt<4>>.
    Found 1-bit register for signal <cal2_corse_cnt<3>>.
    Found 1-bit register for signal <cal2_corse_cnt<2>>.
    Found 1-bit register for signal <cal2_corse_cnt<1>>.
    Found 1-bit register for signal <cal2_corse_cnt<0>>.
    Found 24-bit register for signal <n1142[23:0]>.
    Found 3-bit register for signal <dec_cnt>.
    Found 6-bit register for signal <fine_dec_cnt>.
    Found 1-bit register for signal <wrcal_pat_err>.
    Found 1-bit register for signal <wrcal_pat_resume_r>.
    Found 1-bit register for signal <dqsfound_again>.
    Found 1-bit register for signal <cal2_read_req>.
    Found 1-bit register for signal <wrcal_act_req>.
    Found 5-bit register for signal <cal2_po_dly_cnt>.
    Found 1-bit register for signal <cal2_po_dly_req>.
    Found 1-bit register for signal <cal2_po_dly_load>.
    Found 6-bit register for signal <po_dec_cnt>.
    Found 1-bit register for signal <po_dec_done>.
    Found 17-bit register for signal <cal2_pass_fail>.
    Found 5-bit register for signal <stable_pass_cnt>.
    Found 1-bit register for signal <restart_stable_cnt>.
    Found 5-bit register for signal <pass_start_index>.
    Found 5-bit register for signal <stable_pass_cnt1>.
    Found 1-bit register for signal <restart_stable_cnt1>.
    Found 5-bit register for signal <pass_start_index1>.
    Found 1-bit register for signal <cal2_if_reset>.
    Found 1-bit register for signal <temp_wrcal_done>.
    Found 1-bit register for signal <wrlvl_byte_redo>.
    Found 1-bit register for signal <early1_data>.
    Found 1-bit register for signal <early2_data>.
    Found 1-bit register for signal <idelay_ld>.
    Found 1-bit register for signal <idelay_ld_done>.
    Found 6-bit register for signal <fine_inc_cnt>.
    Found 1-bit register for signal <cal2_done_r1>.
    Found 1-bit register for signal <wrcal_done>.
INFO:Xst:1799 - State 00100 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 00011 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 00101 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 00110 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 01011 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 01100 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 01101 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10000 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 01110 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 01111 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10111 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10010 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10100 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10110 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10011 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10101 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 10001 is never reached in FSM <cal2_state_r>.
INFO:Xst:1799 - State 11000 is never reached in FSM <cal2_state_r>.
    Found finite state machine <FSM_2> for signal <cal2_state_r>.
    -----------------------------------------------------------------------
    | States             | 26                                             |
    | Transitions        | 23                                             |
    | Inputs             | 30                                             |
    | Outputs            | 19                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000                                          |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <cal2_corse_cnt[2]_wl_po_coarse_cnt_w[0][2]_add_27_OUT> created at line 478.
    Found 6-bit adder for signal <cal2_fine_cnt[0][5]_wl_po_fine_cnt_w[0][5]_add_28_OUT> created at line 480.
    Found 3-bit adder for signal <cal2_corse_cnt[5]_wl_po_coarse_cnt_w[1][2]_add_29_OUT> created at line 478.
    Found 6-bit adder for signal <cal2_fine_cnt[1][5]_wl_po_fine_cnt_w[1][5]_add_30_OUT> created at line 480.
    Found 3-bit adder for signal <cal2_corse_cnt[8]_wl_po_coarse_cnt_w[2][2]_add_31_OUT> created at line 478.
    Found 6-bit adder for signal <cal2_fine_cnt[2][5]_wl_po_fine_cnt_w[2][5]_add_32_OUT> created at line 480.
    Found 3-bit adder for signal <cal2_corse_cnt[11]_wl_po_coarse_cnt_w[3][2]_add_33_OUT> created at line 478.
    Found 6-bit adder for signal <cal2_fine_cnt[3][5]_wl_po_fine_cnt_w[3][5]_add_34_OUT> created at line 480.
    Found 6-bit adder for signal <n1179> created at line 512.
    Found 6-bit adder for signal <n1180> created at line 512.
    Found 6-bit adder for signal <n1181> created at line 512.
    Found 6-bit adder for signal <n1182> created at line 512.
    Found 6-bit adder for signal <n1183> created at line 512.
    Found 6-bit adder for signal <n1184> created at line 512.
    Found 6-bit adder for signal <n1185> created at line 512.
    Found 4-bit adder for signal <tap_inc_wait_cnt[3]_GND_102_o_add_456_OUT> created at line 1271.
    Found 5-bit adder for signal <not_empty_wait_cnt[4]_GND_102_o_add_462_OUT> created at line 1280.
    Found 4-bit adder for signal <n1413> created at line 1490.
    Found 5-bit adder for signal <stable_pass_cnt[4]_GND_102_o_add_558_OUT> created at line 1586.
    Found 5-bit adder for signal <stable_pass_cnt1[4]_GND_102_o_add_563_OUT> created at line 1591.
    Found 3-bit adder for signal <wrcal_dqs_cnt_r[2]_GND_102_o_add_591_OUT> created at line 1638.
    Found 5-bit adder for signal <cal2_po_dly_cnt[4]_GND_102_o_add_622_OUT> created at line 1691.
    Found 6-bit adder for signal <n1566[5:0]> created at line 1720.
    Found 6-bit adder for signal <n1569[5:0]> created at line 1723.
    Found 3-bit subtractor for signal <GND_102_o_GND_102_o_sub_479_OUT<2:0>> created at line 1307.
    Found 6-bit subtractor for signal <GND_102_o_GND_102_o_sub_543_OUT<5:0>> created at line 1515.
    Found 6-bit subtractor for signal <GND_102_o_GND_102_o_sub_635_OUT<5:0>> created at line 1719.
    Found 6-bit subtractor for signal <GND_102_o_GND_102_o_sub_637_OUT<5:0>> created at line 1722.
    Found 3-bit subtractor for signal <GND_102_o_GND_102_o_sub_664_OUT<2:0>> created at line 1785.
    Found 6-bit subtractor for signal <GND_102_o_GND_102_o_sub_676_OUT<5:0>> created at line 1799.
    Found 3-bit subtractor for signal <GND_102_o_GND_102_o_sub_681_OUT<2:0>> created at line 1807.
    Found 2x3-bit multiplier for signal <n1321> created at line 1777.
    Found 21-bit shifter logical right for signal <n1322> created at line 1777
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise0[31]_Mux_49_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall0[31]_Mux_50_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise1[31]_Mux_51_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall1[31]_Mux_52_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise2[31]_Mux_53_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall2[31]_Mux_54_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise3[31]_Mux_55_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall3[31]_Mux_56_o> created at line 526.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_59_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_61_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_63_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_65_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_67_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_69_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_71_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_73_o> created at line 526.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_76_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_78_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_80_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_82_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_84_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_86_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_88_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_90_o> created at line 526.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_93_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_95_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_97_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_99_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_101_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_103_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_105_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_107_o> created at line 526.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_110_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_112_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_114_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_116_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_118_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_120_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_122_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_124_o> created at line 526.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_127_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_129_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_131_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_133_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_135_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_137_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_139_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_141_o> created at line 526.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_144_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_146_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_148_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_150_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_152_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_154_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_156_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_158_o> created at line 526.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_161_o> created at line 512.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_163_o> created at line 514.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_165_o> created at line 516.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_167_o> created at line 518.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_169_o> created at line 520.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_171_o> created at line 522.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_173_o> created at line 524.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_175_o> created at line 526.
    Found 3-bit 4-to-1 multiplexer for signal <wrcal_dqs_cnt_r[1]_wl_po_coarse_cnt_w[3][2]_wide_mux_520_OUT> created at line 1500.
    Found 6-bit 4-to-1 multiplexer for signal <wrcal_dqs_cnt_r[1]_cal2_fine_cnt[3][5]_wide_mux_665_OUT> created at line 1791.
    Found 5-bit comparator greater for signal <stable_pass_cnt[4]_GND_102_o_LessThan_554_o> created at line 1569
    Found 5-bit comparator greater for signal <stable_pass_cnt1[4]_GND_102_o_LessThan_556_o> created at line 1576
    Found 5-bit comparator greater for signal <cal2_po_dly_cnt[4]_PWR_99_o_LessThan_574_o> created at line 1598
    Found 5-bit comparator greater for signal <stable_pass_cnt1[4]_stable_pass_cnt[4]_LessThan_633_o> created at line 1718
    Found 3-bit comparator lessequal for signal <n0980> created at line 1792
    Found 3-bit comparator greater for signal <GND_102_o_wrcal_dqs_cnt_r[2]_LessThan_680_o> created at line 1805
    Summary:
	inferred   1 Multiplier(s).
	inferred  29 Adder/Subtractor(s).
	inferred 471 D-type flip-flop(s).
	inferred   6 Comparator(s).
	inferred 170 Multiplexer(s).
	inferred   1 Combinational logic shifter(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_wrcal> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_wrlvl>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v".
        TCQ = 100
        DQS_CNT_WIDTH = 2
        DQ_WIDTH = 32
        DQS_WIDTH = 4
        DRAM_WIDTH = 8
        RANKS = 1
        nCK_PER_CLK = 4
        CLK_PERIOD = 6664
        SIM_CAL_OPTION = "NONE"
    Set property "syn_maxfan = 2" for signal <dqs_po_dec_done>.
    Set property "KEEP = TRUE" for signal <dqs_po_dec_done>.
    Set property "MAX_FANOUT = 2" for signal <dqs_po_dec_done>.
    Set property "syn_maxfan = 2" for signal <wr_level_done>.
    Set property "KEEP = TRUE" for signal <wr_level_done>.
    Set property "MAX_FANOUT = 2" for signal <wr_level_done>.
WARNING:Xst:647 - Input <oclkdelay_calib_cnt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dbg_phy_wrlvl<255:156>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Register <dqs_wl_po_en_stg2_c> equivalent to <dqs_wl_po_stg2_c_incdec> has been removed
    Found 1-bit register for signal <phy_ctl_ready_r2>.
    Found 1-bit register for signal <phy_ctl_ready_r3>.
    Found 1-bit register for signal <phy_ctl_ready_r4>.
    Found 1-bit register for signal <phy_ctl_ready_r5>.
    Found 1-bit register for signal <phy_ctl_ready_r6>.
    Found 1-bit register for signal <wrlvl_byte_redo_r>.
    Found 1-bit register for signal <wrlvl_final_r>.
    Found 1-bit register for signal <wr_level_done>.
    Found 1-bit register for signal <wrlvl_tap_done_r>.
    Found 4-bit register for signal <wait_cnt>.
    Found 9-bit register for signal <po_rdval_cnt>.
    Found 1-bit register for signal <po_cnt_dec>.
    Found 1-bit register for signal <po_dec_done>.
    Found 1-bit register for signal <dqs_po_dec_done>.
    Found 1-bit register for signal <wr_level_done_r1>.
    Found 1-bit register for signal <wr_level_done_r2>.
    Found 1-bit register for signal <wr_level_done_r3>.
    Found 1-bit register for signal <wr_level_done_r4>.
    Found 1-bit register for signal <wr_level_done_r5>.
    Found 12-bit register for signal <wl_po_coarse_cnt>.
    Found 24-bit register for signal <wl_po_fine_cnt>.
    Found 1-bit register for signal <done_dqs_dec>.
    Found 1-bit register for signal <wrlvl_byte_done>.
    Found 24-bit register for signal <wl_dqs_tap_count_r<0>>.
    Found 12-bit register for signal <n0874[11:0]>.
    Found 12-bit register for signal <n0875[11:0]>.
    Found 24-bit register for signal <n0879[23:0]>.
    Found 24-bit register for signal <n0880[23:0]>.
    Found 1-bit register for signal <final_val<5>>.
    Found 1-bit register for signal <final_val<4>>.
    Found 1-bit register for signal <final_val<3>>.
    Found 1-bit register for signal <final_val<2>>.
    Found 1-bit register for signal <final_val<1>>.
    Found 1-bit register for signal <final_val<0>>.
    Found 1-bit register for signal <final_val<11>>.
    Found 1-bit register for signal <final_val<10>>.
    Found 1-bit register for signal <final_val<9>>.
    Found 1-bit register for signal <final_val<8>>.
    Found 1-bit register for signal <final_val<7>>.
    Found 1-bit register for signal <final_val<6>>.
    Found 1-bit register for signal <final_val<17>>.
    Found 1-bit register for signal <final_val<16>>.
    Found 1-bit register for signal <final_val<15>>.
    Found 1-bit register for signal <final_val<14>>.
    Found 1-bit register for signal <final_val<13>>.
    Found 1-bit register for signal <final_val<12>>.
    Found 1-bit register for signal <final_val<23>>.
    Found 1-bit register for signal <final_val<22>>.
    Found 1-bit register for signal <final_val<21>>.
    Found 1-bit register for signal <final_val<20>>.
    Found 1-bit register for signal <final_val<19>>.
    Found 1-bit register for signal <final_val<18>>.
    Found 1-bit register for signal <dqs_po_stg2_f_incdec>.
    Found 1-bit register for signal <dqs_po_en_stg2_f>.
    Found 1-bit register for signal <dqs_wl_po_stg2_c_incdec>.
    Found 1-bit register for signal <rd_data_rise_wl_r<0>>.
    Found 1-bit register for signal <rd_data_rise_wl_r<1>>.
    Found 1-bit register for signal <rd_data_rise_wl_r<2>>.
    Found 1-bit register for signal <rd_data_rise_wl_r<3>>.
    Found 4-bit register for signal <rd_data_previous_r>.
    Found 3-bit register for signal <stable_cnt>.
    Found 1-bit register for signal <past_negedge>.
    Found 1-bit register for signal <flag_ck_negedge>.
    Found 1-bit register for signal <flag_init>.
    Found 4-bit register for signal <rd_data_edge_detect_r>.
    Found 1-bit register for signal <wr_level_start_r>.
    Found 4-bit register for signal <incdec_wait_cnt>.
    Found 1-bit register for signal <wrlvl_err>.
    Found 1-bit register for signal <wr_level_done_r>.
    Found 1-bit register for signal <wrlvl_rank_done_r>.
    Found 3-bit register for signal <dqs_count_r>.
    Found 1-bit register for signal <dq_cnt_inc>.
    Found 2-bit register for signal <rank_cnt_r>.
    Found 5-bit register for signal <wl_state_r>.
    Found 5-bit register for signal <wl_state_r1>.
    Found 1-bit register for signal <inhibit_edge_detect_r>.
    Found 1-bit register for signal <wl_edge_detect_valid_r>.
    Found 6-bit register for signal <wl_tap_count_r>.
    Found 6-bit register for signal <fine_dec_cnt>.
    Found 24-bit register for signal <n0868[23:0]>.
    Found 12-bit register for signal <n0869[11:0]>.
    Found 12-bit register for signal <n0870[11:0]>.
    Found 12-bit register for signal <n0872[11:0]>.
    Found 1-bit register for signal <dual_rnk_dec>.
    Found 3-bit register for signal <wrlvl_redo_corse_inc>.
    Found 1-bit register for signal <phy_ctl_ready_r1>.
    Found finite state machine <FSM_3> for signal <wl_state_r>.
    -----------------------------------------------------------------------
    | States             | 27                                             |
    | Transitions        | 74                                             |
    | Inputs             | 30                                             |
    | Outputs            | 27                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000                                          |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit subtractor for signal <n0948> created at line 573.
    Found 8-bit subtractor for signal <n0950> created at line 579.
    Found 8-bit subtractor for signal <n0954> created at line 573.
    Found 8-bit subtractor for signal <n0956> created at line 579.
    Found 8-bit subtractor for signal <n0960> created at line 573.
    Found 8-bit subtractor for signal <n0962> created at line 579.
    Found 8-bit subtractor for signal <n0966> created at line 573.
    Found 8-bit subtractor for signal <n0968> created at line 579.
    Found 7-bit subtractor for signal <GND_104_o_GND_104_o_sub_460_OUT> created at line 938.
    Found 4-bit subtractor for signal <GND_104_o_GND_104_o_sub_499_OUT> created at line 1003.
    Found 4-bit subtractor for signal <GND_104_o_GND_104_o_sub_541_OUT> created at line 1038.
    Found 5-bit adder for signal <dqs_count_w[2]_dqs_count_w[3]_add_56_OUT> created at line 429.
    Found 31-bit adder for signal <n0949> created at line 572.
    Found 31-bit adder for signal <n0951> created at line 578.
    Found 31-bit adder for signal <n0955> created at line 572.
    Found 31-bit adder for signal <n0957> created at line 578.
    Found 31-bit adder for signal <n0961> created at line 572.
    Found 31-bit adder for signal <n0963> created at line 578.
    Found 31-bit adder for signal <n0967> created at line 572.
    Found 31-bit adder for signal <n0969> created at line 578.
    Found 3-bit adder for signal <stable_cnt[2]_GND_104_o_add_336_OUT> created at line 688.
    Found 4-bit adder for signal <incdec_wait_cnt[3]_GND_104_o_add_391_OUT> created at line 765.
    Found 6-bit adder for signal <wl_tap_count_r[5]_GND_104_o_add_467_OUT> created at line 941.
    Found 3-bit adder for signal <dqs_count_r[2]_GND_104_o_add_474_OUT> created at line 959.
    Found 4-bit adder for signal <n1264> created at line 989.
    Found 4-bit adder for signal <n1281> created at line 1032.
    Found 2-bit adder for signal <rank_cnt_r[1]_GND_104_o_add_607_OUT> created at line 1194.
    Found 4-bit subtractor for signal <GND_104_o_GND_104_o_sub_25_OUT<3:0>> created at line 335.
    Found 9-bit subtractor for signal <GND_104_o_GND_104_o_sub_31_OUT<8:0>> created at line 345.
    Found 6-bit subtractor for signal <GND_104_o_GND_104_o_sub_481_OUT<5:0>> created at line 968.
    Found 3-bit subtractor for signal <GND_104_o_GND_104_o_sub_528_OUT<2:0>> created at line 1034.
    Found 3x3-bit multiplier for signal <n0930> created at line 542.
    Found 42-bit shifter logical right for signal <n0931> created at line 542
    Found 1-bit 4-to-1 multiplexer for signal <dqs_count_r[1]_rd_data_previous_r[3]_Mux_332_o> created at line 686.
    Found 1-bit 4-to-1 multiplexer for signal <dqs_count_r[1]_rd_data_rise_wl_r[3]_Mux_333_o> created at line 686.
    Found 6-bit 4-to-1 multiplexer for signal <wrcal_cnt[1]_smallest[3][5]_wide_mux_403_OUT> created at line 814.
    Found 3-bit 4-to-1 multiplexer for signal <wrcal_cnt[1]_final_coarse_tap[3][2]_wide_mux_396_OUT> created at line 819.
    Found 3-bit 4-to-1 multiplexer for signal <dqs_count_w[1]_final_coarse_tap[3][2]_wide_mux_421_OUT> created at line 843.
    Found 6-bit 4-to-1 multiplexer for signal <dqs_count_w[1]_fine_inc[3][5]_wide_mux_471_OUT> created at line 953.
    Found 3-bit 4-to-1 multiplexer for signal <dqs_count_w[1]_corse_cnt[3][2]_wide_mux_488_OUT> created at line 989.
    Found 3-bit 4-to-1 multiplexer for signal <dqs_count_r[1]_corse_dec[3][2]_wide_mux_505_OUT> created at line 1012.
    Found 3-bit 4-to-1 multiplexer for signal <dqs_count_w[1]_corse_inc[3][2]_wide_mux_539_OUT> created at line 1038.
    Found 1-bit 4-to-1 multiplexer for signal <dqs_count_r[1]_PWR_104_o_equal_367_o> created at line 1096.
    Found 4-bit comparator greater for signal <GND_104_o_wait_cnt[3]_LessThan_24_o> created at line 334
    Found 9-bit comparator greater for signal <GND_104_o_po_rdval_cnt[8]_LessThan_30_o> created at line 343
    Found 2-bit comparator lessequal for signal <n0102> created at line 429
    Found 3-bit comparator lessequal for signal <n0177> created at line 431
    Found 6-bit comparator greater for signal <smallest[0][5]_largest[0][5]_LessThan_207_o> created at line 569
    Found 6-bit comparator greater for signal <largest[0][5]_smallest[0][5]_LessThan_215_o> created at line 575
    Found 6-bit comparator not equal for signal <smallest[0][5]_largest[0][5]_equal_223_o> created at line 581
    Found 6-bit comparator greater for signal <smallest[1][5]_largest[1][5]_LessThan_229_o> created at line 569
    Found 6-bit comparator greater for signal <largest[1][5]_smallest[1][5]_LessThan_237_o> created at line 575
    Found 6-bit comparator not equal for signal <smallest[1][5]_largest[1][5]_equal_245_o> created at line 581
    Found 6-bit comparator greater for signal <smallest[2][5]_largest[2][5]_LessThan_251_o> created at line 569
    Found 6-bit comparator greater for signal <largest[2][5]_smallest[2][5]_LessThan_259_o> created at line 575
    Found 6-bit comparator not equal for signal <smallest[2][5]_largest[2][5]_equal_267_o> created at line 581
    Found 6-bit comparator greater for signal <smallest[3][5]_largest[3][5]_LessThan_273_o> created at line 569
    Found 6-bit comparator greater for signal <largest[3][5]_smallest[3][5]_LessThan_281_o> created at line 575
    Found 6-bit comparator not equal for signal <smallest[3][5]_largest[3][5]_equal_289_o> created at line 581
    Found 1-bit comparator equal for signal <n0490> created at line 680
    Found 6-bit comparator greater for signal <GND_104_o_wl_tap_count_r[5]_LessThan_329_o> created at line 683
    Found 3-bit comparator greater for signal <stable_cnt[2]_PWR_104_o_LessThan_336_o> created at line 687
    Found 3-bit comparator greater for signal <GND_104_o_stable_cnt[2]_LessThan_354_o> created at line 711
    Found 6-bit comparator greater for signal <wl_tap_count_r[5]_GND_104_o_LessThan_365_o> created at line 730
    Found 3-bit comparator lessequal for signal <n0574> created at line 813
    Found 3-bit comparator greater for signal <wrcal_cnt[1]_PWR_104_o_LessThan_406_o> created at line 816
    Found 3-bit comparator greater for signal <wrcal_cnt[1]_GND_104_o_LessThan_410_o> created at line 819
    Found 5-bit comparator lessequal for signal <n0637> created at line 938
    Found 6-bit comparator greater for signal <GND_104_o_fine_dec_cnt[5]_LessThan_485_o> created at line 979
    Found 4-bit comparator greater for signal <n0668> created at line 989
    Found 6-bit comparator greater for signal <PWR_104_o_wl_tap_count_r[5]_LessThan_581_o> created at line 1108
    Found 6-bit comparator greater for signal <wl_tap_count_r[5]_PWR_104_o_LessThan_586_o> created at line 1117
    Found 3-bit comparator greater for signal <dqs_count_r[1]_PWR_104_o_LessThan_588_o> created at line 1119
    WARNING:Xst:2404 -  FFs/Latches <add_smallest<3><1:24>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrlvl>.
    WARNING:Xst:2404 -  FFs/Latches <add_largest<3><23:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrlvl>.
    Summary:
	inferred   1 Multiplier(s).
	inferred  31 Adder/Subtractor(s).
	inferred 307 D-type flip-flop(s).
	inferred  30 Comparator(s).
	inferred 191 Multiplexer(s).
	inferred   1 Combinational logic shifter(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_wrlvl> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay.v".
        TCQ = 100
        tCK = 1666
        DQS_CNT_WIDTH = 2
        N_CTL_LANES = 32'b00000000000000000000000000000011
        SIM_CAL_OPTION = "NONE"
    Set property "KEEP = TRUE" for signal <delay_done_r4>.
    Set property "MAX_FANOUT = 10" for signal <delay_done_r4>.
    Register <po_en_stg2_c> equivalent to <po_stg2_c_incdec> has been removed
    Found 1-bit register for signal <po_cnt_inc>.
    Found 1-bit register for signal <po_cnt_dec>.
    Found 1-bit register for signal <po_en_stg2_f>.
    Found 1-bit register for signal <po_stg2_c_incdec>.
    Found 6-bit register for signal <delay_cnt_r>.
    Found 6-bit register for signal <delaydec_cnt_r>.
    Found 3-bit register for signal <ctl_lane_cnt>.
    Found 1-bit register for signal <delay_dec_done>.
    Found 1-bit register for signal <delay_done_r1>.
    Found 1-bit register for signal <delay_done_r2>.
    Found 1-bit register for signal <delay_done_r3>.
    Found 1-bit register for signal <delay_done_r4>.
    Found 4-bit register for signal <wait_cnt_r>.
    Found 3-bit adder for signal <ctl_lane_cnt[2]_GND_106_o_add_41_OUT> created at line 211.
    Found 4-bit subtractor for signal <GND_106_o_GND_106_o_sub_3_OUT<3:0>> created at line 133.
    Found 6-bit subtractor for signal <GND_106_o_GND_106_o_sub_22_OUT<5:0>> created at line 191.
    Found 6-bit subtractor for signal <GND_106_o_GND_106_o_sub_32_OUT<5:0>> created at line 200.
    Found 4-bit comparator greater for signal <GND_106_o_wait_cnt_r[3]_LessThan_2_o> created at line 132
    Found 6-bit comparator greater for signal <GND_106_o_delaydec_cnt_r[5]_LessThan_8_o> created at line 137
    Found 6-bit comparator greater for signal <GND_106_o_delay_cnt_r[5]_LessThan_10_o> created at line 139
    WARNING:Xst:2404 -  FFs/Latches <po_stg2_f_incdec<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay>.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  28 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_oclkdelay_cal>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v".
        TCQ = 100
        tCK = 1666
        nCK_PER_CLK = 4
        DRAM_TYPE = "DDR3"
        DRAM_WIDTH = 8
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DQ_WIDTH = 32
        SIM_CAL_OPTION = "NONE"
        OCAL_EN = "ON"
    Set property "syn_maxfan = 10" for signal <ocal_done_r>.
    Set property "KEEP = TRUE" for signal <ocal_done_r>.
    Set property "MAX_FANOUT = 10" for signal <ocal_done_r>.
WARNING:Xst:653 - Signal <dbg_phy_oclkdelay_cal<255:225>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dbg_phy_oclkdelay_cal<53:24>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Register <pat_data_match_valid_r> equivalent to <rd_active_r3> has been removed
    Found 4-bit register for signal <count>.
    Found 1-bit register for signal <po_stg3_dec>.
    Found 1-bit register for signal <po_en_stg3>.
    Found 6-bit register for signal <delay_cnt_r>.
    Found 1-bit register for signal <delay_done>.
    Found 1-bit register for signal <delay_done_r1>.
    Found 1-bit register for signal <delay_done_r2>.
    Found 1-bit register for signal <delay_done_r3>.
    Found 1-bit register for signal <delay_done_r4>.
    Found 3-bit register for signal <mux_sel_r>.
    Found 1-bit register for signal <oclkdelay_calib_start_r>.
    Found 1-bit register for signal <rd_active_r>.
    Found 1-bit register for signal <rd_active_r1>.
    Found 1-bit register for signal <rd_active_r2>.
    Found 1-bit register for signal <rd_active_r3>.
    Found 1-bit register for signal <rd_active_r4>.
    Found 1-bit register for signal <stg3_dec_r>.
    Found 1-bit register for signal <sel_rd_rise0_r<0>>.
    Found 1-bit register for signal <sel_rd_fall0_r<0>>.
    Found 1-bit register for signal <sel_rd_rise1_r<0>>.
    Found 1-bit register for signal <sel_rd_fall1_r<0>>.
    Found 1-bit register for signal <sel_rd_rise2_r<0>>.
    Found 1-bit register for signal <sel_rd_fall2_r<0>>.
    Found 1-bit register for signal <sel_rd_rise3_r<0>>.
    Found 1-bit register for signal <sel_rd_fall3_r<0>>.
    Found 1-bit register for signal <sel_rd_rise0_r<1>>.
    Found 1-bit register for signal <sel_rd_fall0_r<1>>.
    Found 1-bit register for signal <sel_rd_rise1_r<1>>.
    Found 1-bit register for signal <sel_rd_fall1_r<1>>.
    Found 1-bit register for signal <sel_rd_rise2_r<1>>.
    Found 1-bit register for signal <sel_rd_fall2_r<1>>.
    Found 1-bit register for signal <sel_rd_rise3_r<1>>.
    Found 1-bit register for signal <sel_rd_fall3_r<1>>.
    Found 1-bit register for signal <sel_rd_rise0_r<2>>.
    Found 1-bit register for signal <sel_rd_fall0_r<2>>.
    Found 1-bit register for signal <sel_rd_rise1_r<2>>.
    Found 1-bit register for signal <sel_rd_fall1_r<2>>.
    Found 1-bit register for signal <sel_rd_rise2_r<2>>.
    Found 1-bit register for signal <sel_rd_fall2_r<2>>.
    Found 1-bit register for signal <sel_rd_rise3_r<2>>.
    Found 1-bit register for signal <sel_rd_fall3_r<2>>.
    Found 1-bit register for signal <sel_rd_rise0_r<3>>.
    Found 1-bit register for signal <sel_rd_fall0_r<3>>.
    Found 1-bit register for signal <sel_rd_rise1_r<3>>.
    Found 1-bit register for signal <sel_rd_fall1_r<3>>.
    Found 1-bit register for signal <sel_rd_rise2_r<3>>.
    Found 1-bit register for signal <sel_rd_fall2_r<3>>.
    Found 1-bit register for signal <sel_rd_rise3_r<3>>.
    Found 1-bit register for signal <sel_rd_fall3_r<3>>.
    Found 1-bit register for signal <sel_rd_rise0_r<4>>.
    Found 1-bit register for signal <sel_rd_fall0_r<4>>.
    Found 1-bit register for signal <sel_rd_rise1_r<4>>.
    Found 1-bit register for signal <sel_rd_fall1_r<4>>.
    Found 1-bit register for signal <sel_rd_rise2_r<4>>.
    Found 1-bit register for signal <sel_rd_fall2_r<4>>.
    Found 1-bit register for signal <sel_rd_rise3_r<4>>.
    Found 1-bit register for signal <sel_rd_fall3_r<4>>.
    Found 1-bit register for signal <sel_rd_rise0_r<5>>.
    Found 1-bit register for signal <sel_rd_fall0_r<5>>.
    Found 1-bit register for signal <sel_rd_rise1_r<5>>.
    Found 1-bit register for signal <sel_rd_fall1_r<5>>.
    Found 1-bit register for signal <sel_rd_rise2_r<5>>.
    Found 1-bit register for signal <sel_rd_fall2_r<5>>.
    Found 1-bit register for signal <sel_rd_rise3_r<5>>.
    Found 1-bit register for signal <sel_rd_fall3_r<5>>.
    Found 1-bit register for signal <sel_rd_rise0_r<6>>.
    Found 1-bit register for signal <sel_rd_fall0_r<6>>.
    Found 1-bit register for signal <sel_rd_rise1_r<6>>.
    Found 1-bit register for signal <sel_rd_fall1_r<6>>.
    Found 1-bit register for signal <sel_rd_rise2_r<6>>.
    Found 1-bit register for signal <sel_rd_fall2_r<6>>.
    Found 1-bit register for signal <sel_rd_rise3_r<6>>.
    Found 1-bit register for signal <sel_rd_fall3_r<6>>.
    Found 1-bit register for signal <sel_rd_rise0_r<7>>.
    Found 1-bit register for signal <sel_rd_fall0_r<7>>.
    Found 1-bit register for signal <sel_rd_rise1_r<7>>.
    Found 1-bit register for signal <sel_rd_fall1_r<7>>.
    Found 1-bit register for signal <sel_rd_rise2_r<7>>.
    Found 1-bit register for signal <sel_rd_fall2_r<7>>.
    Found 1-bit register for signal <sel_rd_rise3_r<7>>.
    Found 1-bit register for signal <sel_rd_fall3_r<7>>.
    Found 8-bit register for signal <prev_rd_rise0_r>.
    Found 8-bit register for signal <prev_rd_fall0_r>.
    Found 8-bit register for signal <prev_rd_rise1_r>.
    Found 8-bit register for signal <prev_rd_fall1_r>.
    Found 8-bit register for signal <prev_rd_rise2_r>.
    Found 8-bit register for signal <prev_rd_fall2_r>.
    Found 8-bit register for signal <prev_rd_rise3_r>.
    Found 8-bit register for signal <prev_rd_fall3_r>.
    Found 1-bit register for signal <pat_match_rise1_r<0>>.
    Found 1-bit register for signal <pat_match_fall1_r<0>>.
    Found 1-bit register for signal <pat_match_rise2_r<0>>.
    Found 1-bit register for signal <pat_match_fall2_r<0>>.
    Found 1-bit register for signal <pat_match_rise3_r<0>>.
    Found 1-bit register for signal <pat_match_fall3_r<0>>.
    Found 1-bit register for signal <pat_match_rise1_r<1>>.
    Found 1-bit register for signal <pat_match_fall1_r<1>>.
    Found 1-bit register for signal <pat_match_rise2_r<1>>.
    Found 1-bit register for signal <pat_match_fall2_r<1>>.
    Found 1-bit register for signal <pat_match_rise3_r<1>>.
    Found 1-bit register for signal <pat_match_fall3_r<1>>.
    Found 1-bit register for signal <pat_match_rise1_r<2>>.
    Found 1-bit register for signal <pat_match_fall1_r<2>>.
    Found 1-bit register for signal <pat_match_rise2_r<2>>.
    Found 1-bit register for signal <pat_match_fall2_r<2>>.
    Found 1-bit register for signal <pat_match_rise3_r<2>>.
    Found 1-bit register for signal <pat_match_fall3_r<2>>.
    Found 1-bit register for signal <pat_match_rise1_r<3>>.
    Found 1-bit register for signal <pat_match_fall1_r<3>>.
    Found 1-bit register for signal <pat_match_rise2_r<3>>.
    Found 1-bit register for signal <pat_match_fall2_r<3>>.
    Found 1-bit register for signal <pat_match_rise3_r<3>>.
    Found 1-bit register for signal <pat_match_fall3_r<3>>.
    Found 1-bit register for signal <pat_match_rise1_r<4>>.
    Found 1-bit register for signal <pat_match_fall1_r<4>>.
    Found 1-bit register for signal <pat_match_rise2_r<4>>.
    Found 1-bit register for signal <pat_match_fall2_r<4>>.
    Found 1-bit register for signal <pat_match_rise3_r<4>>.
    Found 1-bit register for signal <pat_match_fall3_r<4>>.
    Found 1-bit register for signal <pat_match_rise1_r<5>>.
    Found 1-bit register for signal <pat_match_fall1_r<5>>.
    Found 1-bit register for signal <pat_match_rise2_r<5>>.
    Found 1-bit register for signal <pat_match_fall2_r<5>>.
    Found 1-bit register for signal <pat_match_rise3_r<5>>.
    Found 1-bit register for signal <pat_match_fall3_r<5>>.
    Found 1-bit register for signal <pat_match_rise1_r<6>>.
    Found 1-bit register for signal <pat_match_fall1_r<6>>.
    Found 1-bit register for signal <pat_match_rise2_r<6>>.
    Found 1-bit register for signal <pat_match_fall2_r<6>>.
    Found 1-bit register for signal <pat_match_rise3_r<6>>.
    Found 1-bit register for signal <pat_match_fall3_r<6>>.
    Found 1-bit register for signal <pat_match_rise1_r<7>>.
    Found 1-bit register for signal <pat_match_fall1_r<7>>.
    Found 1-bit register for signal <pat_match_rise2_r<7>>.
    Found 1-bit register for signal <pat_match_fall2_r<7>>.
    Found 1-bit register for signal <pat_match_rise3_r<7>>.
    Found 1-bit register for signal <pat_match_fall3_r<7>>.
    Found 1-bit register for signal <pat_match_rise1_and_r>.
    Found 1-bit register for signal <pat_match_fall1_and_r>.
    Found 1-bit register for signal <pat_match_rise2_and_r>.
    Found 1-bit register for signal <pat_match_fall2_and_r>.
    Found 1-bit register for signal <pat_match_rise3_and_r>.
    Found 1-bit register for signal <pat_match_fall3_and_r>.
    Found 1-bit register for signal <pat_data_match_r>.
    Found 4-bit register for signal <stable_stg3_cnt>.
    Found 1-bit register for signal <stable_eye_r>.
    Found 1-bit register for signal <wait_cnt_en_r>.
    Found 4-bit register for signal <wait_cnt_r>.
    Found 1-bit register for signal <cnt_next_state>.
    Found 24-bit register for signal <n0905[23:0]>.
    Found 1-bit register for signal <prech_done_r>.
    Found 1-bit register for signal <stg3_tap_cnt_eq_oclkdelay_init_val>.
    Found 1-bit register for signal <stg3_tap_cnt_gt_20>.
    Found 1-bit register for signal <stg3_tap_cnt_eq_63>.
    Found 1-bit register for signal <stg3_tap_cnt_less_oclkdelay_init_val>.
    Found 1-bit register for signal <stg3_limit>.
    Found 5-bit register for signal <ocal_state_r>.
    Found 3-bit register for signal <cnt_dqs_r>.
    Found 6-bit register for signal <stg3_tap_cnt>.
    Found 6-bit register for signal <stg3_incdec_limit>.
    Found 1-bit register for signal <stg3_dec2inc>.
    Found 6-bit register for signal <stg2_tap_cnt>.
    Found 2-bit register for signal <stg2_inc2_cnt>.
    Found 2-bit register for signal <stg2_dec2_cnt>.
    Found 6-bit register for signal <stg2_dec_cnt>.
    Found 1-bit register for signal <stg3_dec>.
    Found 1-bit register for signal <wrlvl_final>.
    Found 1-bit register for signal <oclk_calib_resume>.
    Found 1-bit register for signal <oclk_prech_req>.
    Found 6-bit register for signal <ocal_final_cnt_r>.
    Found 6-bit register for signal <ocal_inc_cnt>.
    Found 6-bit register for signal <ocal_dec_cnt>.
    Found 1-bit register for signal <ocal_stg3_inc_en>.
    Found 1-bit register for signal <ocal_edge1_found>.
    Found 1-bit register for signal <ocal_edge2_found>.
    Found 6-bit register for signal <ocal_right_edge>.
    Found 6-bit register for signal <ocal_edge1_taps>.
    Found 6-bit register for signal <ocal_edge2_taps>.
    Found 1-bit register for signal <ocal_byte_done>.
    Found 1-bit register for signal <ocal_if_rst>.
    Found 1-bit register for signal <ocal_done_r>.
    Found 1-bit register for signal <po_stg23_sel>.
    Found 1-bit register for signal <po_en_stg23>.
    Found 1-bit register for signal <po_stg23_incdec>.
    Found finite state machine <FSM_4> for signal <ocal_state_r>.
    -----------------------------------------------------------------------
    | States             | 21                                             |
    | Transitions        | 66                                             |
    | Inputs             | 31                                             |
    | Outputs            | 32                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000                                          |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 7-bit subtractor for signal <GND_107_o_GND_107_o_sub_353_OUT> created at line 658.
    Found 7-bit subtractor for signal <GND_107_o_GND_107_o_sub_376_OUT> created at line 704.
    Found 6-bit subtractor for signal <oclkdelay_init_val[5]_stg3_tap_cnt[5]_sub_424_OUT> created at line 838.
    Found 6-bit subtractor for signal <stg2_tap_cnt[5]_wl_po_fine_cnt[23]_sub_460_OUT> created at line 938.
    Found 7-bit subtractor for signal <n1039> created at line 1021.
    Found 7-bit subtractor for signal <GND_107_o_GND_107_o_sub_508_OUT> created at line 1022.
    Found 7-bit subtractor for signal <n1038[6:0]> created at line 1026.
    Found 7-bit subtractor for signal <n1045> created at line 1032.
    Found 6-bit subtractor for signal <n1048> created at line 1041.
    Found 6-bit adder for signal <n0912> created at line 421.
    Found 6-bit adder for signal <n0913> created at line 421.
    Found 6-bit adder for signal <n0914> created at line 421.
    Found 6-bit adder for signal <n0915> created at line 421.
    Found 6-bit adder for signal <n0916> created at line 421.
    Found 6-bit adder for signal <n0917> created at line 421.
    Found 6-bit adder for signal <n0918> created at line 421.
    Found 4-bit adder for signal <stable_stg3_cnt[3]_GND_107_o_add_308_OUT> created at line 586.
    Found 4-bit adder for signal <wait_cnt_r[3]_GND_107_o_add_327_OUT> created at line 616.
    Found 7-bit adder for signal <_n1316> created at line 656.
    Found 5-bit adder for signal <cnt_dqs_w[2]_cnt_dqs_w[3]_add_384_OUT> created at line 757.
    Found 6-bit adder for signal <stg3_incdec_limit[5]_GND_107_o_add_462_OUT> created at line 954.
    Found 6-bit adder for signal <stg2_tap_cnt[5]_GND_107_o_add_476_OUT> created at line 962.
    Found 32-bit adder for signal <n1216> created at line 1021.
    Found 32-bit adder for signal <n1042> created at line 1021.
    Found 31-bit adder for signal <n1043> created at line 1026.
    Found 31-bit adder for signal <n1046> created at line 1032.
    Found 6-bit adder for signal <n1174> created at line 1036.
    Found 6-bit adder for signal <stg3_tap_cnt[5]_GND_107_o_add_520_OUT> created at line 1059.
    Found 3-bit adder for signal <cnt_dqs_r[2]_GND_107_o_add_532_OUT> created at line 1114.
    Found 6-bit adder for signal <n1230[5:0]> created at line 1117.
    Found 8-bit adder for signal <n1061> created at line 1117.
    Found 4-bit subtractor for signal <GND_107_o_GND_107_o_sub_49_OUT<3:0>> created at line 325.
    Found 6-bit subtractor for signal <GND_107_o_GND_107_o_sub_59_OUT<5:0>> created at line 357.
    Found 6-bit subtractor for signal <GND_107_o_GND_107_o_sub_434_OUT<5:0>> created at line 861.
    Found 6-bit subtractor for signal <GND_107_o_GND_107_o_sub_438_OUT<5:0>> created at line 868.
    Found 2-bit subtractor for signal <GND_107_o_GND_107_o_sub_479_OUT<1:0>> created at line 964.
    Found 6-bit subtractor for signal <GND_107_o_GND_107_o_sub_484_OUT<5:0>> created at line 977.
    Found 6-bit subtractor for signal <GND_107_o_GND_107_o_sub_486_OUT<5:0>> created at line 979.
    Found 2-bit subtractor for signal <GND_107_o_GND_107_o_sub_488_OUT<1:0>> created at line 982.
    Found 6-bit subtractor for signal <GND_107_o_GND_107_o_sub_523_OUT<5:0>> created at line 1061.
    Found 42-bit shifter logical right for signal <n0944> created at line 757
    Found 42-bit shifter logical right for signal <n1062> created at line 1117
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_rise0[31]_Mux_77_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_fall0[31]_Mux_78_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_rise1[31]_Mux_79_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_fall1[31]_Mux_80_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_rise2[31]_Mux_81_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_fall2[31]_Mux_82_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_rise3[31]_Mux_83_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[1]_rd_data_fall3[31]_Mux_84_o> created at line 435.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise0[31]_Mux_87_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall0[31]_Mux_89_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise1[31]_Mux_91_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall1[31]_Mux_93_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise2[31]_Mux_95_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall2[31]_Mux_97_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise3[31]_Mux_99_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall3[31]_Mux_101_o> created at line 435.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise0[31]_Mux_104_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall0[31]_Mux_106_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise1[31]_Mux_108_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall1[31]_Mux_110_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise2[31]_Mux_112_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall2[31]_Mux_114_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise3[31]_Mux_116_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall3[31]_Mux_118_o> created at line 435.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise0[31]_Mux_121_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall0[31]_Mux_123_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise1[31]_Mux_125_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall1[31]_Mux_127_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise2[31]_Mux_129_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall2[31]_Mux_131_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise3[31]_Mux_133_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall3[31]_Mux_135_o> created at line 435.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise0[31]_Mux_138_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall0[31]_Mux_140_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise1[31]_Mux_142_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall1[31]_Mux_144_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise2[31]_Mux_146_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall2[31]_Mux_148_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise3[31]_Mux_150_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall3[31]_Mux_152_o> created at line 435.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise0[31]_Mux_155_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall0[31]_Mux_157_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise1[31]_Mux_159_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall1[31]_Mux_161_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise2[31]_Mux_163_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall2[31]_Mux_165_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise3[31]_Mux_167_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall3[31]_Mux_169_o> created at line 435.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise0[31]_Mux_172_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall0[31]_Mux_174_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise1[31]_Mux_176_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall1[31]_Mux_178_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise2[31]_Mux_180_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall2[31]_Mux_182_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise3[31]_Mux_184_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall3[31]_Mux_186_o> created at line 435.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise0[31]_Mux_189_o> created at line 421.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall0[31]_Mux_191_o> created at line 423.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise1[31]_Mux_193_o> created at line 425.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall1[31]_Mux_195_o> created at line 427.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise2[31]_Mux_197_o> created at line 429.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall2[31]_Mux_199_o> created at line 431.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_rise3[31]_Mux_201_o> created at line 433.
    Found 1-bit 32-to-1 multiplexer for signal <mux_sel_r[2]_rd_data_fall3[31]_Mux_203_o> created at line 435.
    Found 4-bit comparator greater for signal <GND_107_o_count[3]_LessThan_48_o> created at line 324
    Found 6-bit comparator greater for signal <GND_107_o_delay_cnt_r[5]_LessThan_58_o> created at line 356
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[0]_prev_rd_rise1_r[0]_equal_225_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[0]_prev_rd_fall1_r[0]_equal_226_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[0]_prev_rd_rise2_r[0]_equal_227_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[0]_prev_rd_fall2_r[0]_equal_228_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[0]_prev_rd_rise3_r[0]_equal_229_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[0]_prev_rd_fall3_r[0]_equal_230_o> created at line 498
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[1]_prev_rd_rise1_r[1]_equal_234_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[1]_prev_rd_fall1_r[1]_equal_235_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[1]_prev_rd_rise2_r[1]_equal_236_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[1]_prev_rd_fall2_r[1]_equal_237_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[1]_prev_rd_rise3_r[1]_equal_238_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[1]_prev_rd_fall3_r[1]_equal_239_o> created at line 498
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[2]_prev_rd_rise1_r[2]_equal_243_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[2]_prev_rd_fall1_r[2]_equal_244_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[2]_prev_rd_rise2_r[2]_equal_245_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[2]_prev_rd_fall2_r[2]_equal_246_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[2]_prev_rd_rise3_r[2]_equal_247_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[2]_prev_rd_fall3_r[2]_equal_248_o> created at line 498
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[3]_prev_rd_rise1_r[3]_equal_252_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[3]_prev_rd_fall1_r[3]_equal_253_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[3]_prev_rd_rise2_r[3]_equal_254_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[3]_prev_rd_fall2_r[3]_equal_255_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[3]_prev_rd_rise3_r[3]_equal_256_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[3]_prev_rd_fall3_r[3]_equal_257_o> created at line 498
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[4]_prev_rd_rise1_r[4]_equal_261_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[4]_prev_rd_fall1_r[4]_equal_262_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[4]_prev_rd_rise2_r[4]_equal_263_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[4]_prev_rd_fall2_r[4]_equal_264_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[4]_prev_rd_rise3_r[4]_equal_265_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[4]_prev_rd_fall3_r[4]_equal_266_o> created at line 498
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[5]_prev_rd_rise1_r[5]_equal_270_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[5]_prev_rd_fall1_r[5]_equal_271_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[5]_prev_rd_rise2_r[5]_equal_272_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[5]_prev_rd_fall2_r[5]_equal_273_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[5]_prev_rd_rise3_r[5]_equal_274_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[5]_prev_rd_fall3_r[5]_equal_275_o> created at line 498
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[6]_prev_rd_rise1_r[6]_equal_279_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[6]_prev_rd_fall1_r[6]_equal_280_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[6]_prev_rd_rise2_r[6]_equal_281_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[6]_prev_rd_fall2_r[6]_equal_282_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[6]_prev_rd_rise3_r[6]_equal_283_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[6]_prev_rd_fall3_r[6]_equal_284_o> created at line 498
    Found 1-bit comparator equal for signal <sel_rd_rise1_r[7]_prev_rd_rise1_r[7]_equal_288_o> created at line 473
    Found 1-bit comparator equal for signal <sel_rd_fall1_r[7]_prev_rd_fall1_r[7]_equal_289_o> created at line 478
    Found 1-bit comparator equal for signal <sel_rd_rise2_r[7]_prev_rd_rise2_r[7]_equal_290_o> created at line 483
    Found 1-bit comparator equal for signal <sel_rd_fall2_r[7]_prev_rd_fall2_r[7]_equal_291_o> created at line 488
    Found 1-bit comparator equal for signal <sel_rd_rise3_r[7]_prev_rd_rise3_r[7]_equal_292_o> created at line 493
    Found 1-bit comparator equal for signal <sel_rd_fall3_r[7]_prev_rd_fall3_r[7]_equal_293_o> created at line 498
    Found 4-bit comparator greater for signal <stable_stg3_cnt[3]_PWR_106_o_LessThan_308_o> created at line 585
    Found 3-bit comparator lessequal for signal <n0467> created at line 632
    Found 32-bit comparator equal for signal <GND_107_o_GND_107_o_equal_354_o> created at line 658
    Found 6-bit comparator lessequal for signal <n0502> created at line 668
    Found 6-bit comparator lessequal for signal <n0504> created at line 670
    Found 6-bit comparator lessequal for signal <n0510> created at line 690
    Found 6-bit comparator lessequal for signal <n0516> created at line 702
    Found 32-bit comparator lessequal for signal <n0519> created at line 704
    Found 6-bit comparator greater for signal <stg2_tap_cnt[5]_PWR_106_o_LessThan_461_o> created at line 941
    Found 6-bit comparator greater for signal <GND_107_o_stg2_tap_cnt[5]_LessThan_462_o> created at line 946
    Found 32-bit comparator greater for signal <GND_107_o_GND_107_o_LessThan_504_o> created at line 1019
    Found 6-bit comparator greater for signal <GND_107_o_ocal_edge1_taps[5]_LessThan_505_o> created at line 1019
    Found 6-bit comparator greater for signal <GND_107_o_ocal_inc_cnt[5]_LessThan_527_o> created at line 1072
    Found 7-bit comparator equal for signal <GND_107_o_GND_107_o_equal_351_o> created at line 656
    WARNING:Xst:2404 -  FFs/Latches <po_stg3_incdec<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_oclkdelay_cal>.
    Summary:
	inferred  37 Adder/Subtractor(s).
	inferred 332 D-type flip-flop(s).
	inferred  64 Comparator(s).
	inferred 107 Multiplexer(s).
	inferred   2 Combinational logic shifter(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_oclkdelay_cal> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_dqs_found_cal>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_dqs_found_cal.v".
        TCQ = 100
        nCK_PER_CLK = 4
        nCL = 9
        AL = "0"
        nCWL = 7
        DRAM_TYPE = "DDR3"
        RANKS = 1
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_WIDTH = 8
        REG_CTRL = "OFF"
        SIM_CAL_OPTION = "NONE"
        NUM_DQSFOUND_CAL = 1020
        N_CTL_LANES = 32'b00000000000000000000000000000011
        HIGHEST_LANE = 8
        HIGHEST_BANK = 2
        BYTE_LANES_B0 = 4'b1111
        BYTE_LANES_B1 = 4'b1110
        BYTE_LANES_B2 = 4'b0000
        BYTE_LANES_B3 = 4'b0000
        BYTE_LANES_B4 = 4'b0000
        DATA_CTL_B0 = 4'b1111
        DATA_CTL_B1 = 4'b0000
        DATA_CTL_B2 = 4'b0000
        DATA_CTL_B3 = 4'b0000
        DATA_CTL_B4 = 4'b0000
    Set property "ASYNC_REG = TRUE" for signal <pi_dqs_found_lanes_r1>.
    Set property "ASYNC_REG = TRUE" for signal <pi_dqs_found_lanes_r2>.
    Set property "ASYNC_REG = TRUE" for signal <pi_dqs_found_lanes_r3>.
WARNING:Xst:647 - Input <po_counter_read_val> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dqsfound_retry> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dbg_dqs_found_cal<255:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dqsfound_retry_done> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 6-bit register for signal <final_do_max<0>>.
    Found 2-bit register for signal <pi_dqs_found_any_bank>.
    Found 2-bit register for signal <pi_dqs_found_all_bank_r>.
    Found 2-bit register for signal <pi_dqs_found_any_bank_r>.
    Found 4-bit register for signal <detect_rd_cnt>.
    Found 1-bit register for signal <rst_dqs_find_r1>.
    Found 1-bit register for signal <rst_dqs_find_r2>.
    Found 1-bit register for signal <fine_adjust>.
    Found 3-bit register for signal <ctl_lane_cnt>.
    Found 4-bit register for signal <fine_adj_state_r>.
    Found 1-bit register for signal <fine_adjust_done_r>.
    Found 1-bit register for signal <ck_po_stg2_f_indec>.
    Found 1-bit register for signal <ck_po_stg2_f_en>.
    Found 1-bit register for signal <rst_dqs_find>.
    Found 6-bit register for signal <init_dec_cnt>.
    Found 6-bit register for signal <dec_cnt>.
    Found 6-bit register for signal <inc_cnt>.
    Found 1-bit register for signal <init_dec_done>.
    Found 1-bit register for signal <final_dec_done>.
    Found 1-bit register for signal <first_fail_detect>.
    Found 1-bit register for signal <second_fail_detect>.
    Found 6-bit register for signal <first_fail_taps>.
    Found 6-bit register for signal <second_fail_taps>.
    Found 6-bit register for signal <stable_pass_cnt>.
    Found 1-bit register for signal <dqs_found_prech_req>.
    Found 1-bit register for signal <dqs_found_start_r>.
    Found 2-bit register for signal <rnk_cnt_r>.
    Found 1-bit register for signal <init_dqsfound_done_r>.
    Found 1-bit register for signal <rank_done_r>.
    Found 8-bit register for signal <pi_dqs_found_lanes_r1>.
    Found 8-bit register for signal <pi_dqs_found_lanes_r2>.
    Found 8-bit register for signal <pi_dqs_found_lanes_r3>.
    Found 1-bit register for signal <init_dqsfound_done_r1>.
    Found 1-bit register for signal <init_dqsfound_done_r2>.
    Found 1-bit register for signal <init_dqsfound_done_r3>.
    Found 1-bit register for signal <init_dqsfound_done_r4>.
    Found 1-bit register for signal <init_dqsfound_done_r5>.
    Found 1-bit register for signal <rank_done_r1>.
    Found 1-bit register for signal <dqs_found_done_r>.
    Found 1-bit register for signal <pi_rst_stg1_cal_r<0>>.
    Found 1-bit register for signal <pi_rst_stg1_cal_r<1>>.
    Found 1-bit register for signal <pi_rst_stg1_cal_r1<0>>.
    Found 1-bit register for signal <pi_rst_stg1_cal_r1<1>>.
    Found 1-bit register for signal <retry_cnt<9>>.
    Found 1-bit register for signal <retry_cnt<8>>.
    Found 1-bit register for signal <retry_cnt<7>>.
    Found 1-bit register for signal <retry_cnt<6>>.
    Found 1-bit register for signal <retry_cnt<5>>.
    Found 1-bit register for signal <retry_cnt<4>>.
    Found 1-bit register for signal <retry_cnt<3>>.
    Found 1-bit register for signal <retry_cnt<2>>.
    Found 1-bit register for signal <retry_cnt<1>>.
    Found 1-bit register for signal <retry_cnt<0>>.
    Found 1-bit register for signal <retry_cnt<19>>.
    Found 1-bit register for signal <retry_cnt<18>>.
    Found 1-bit register for signal <retry_cnt<17>>.
    Found 1-bit register for signal <retry_cnt<16>>.
    Found 1-bit register for signal <retry_cnt<15>>.
    Found 1-bit register for signal <retry_cnt<14>>.
    Found 1-bit register for signal <retry_cnt<13>>.
    Found 1-bit register for signal <retry_cnt<12>>.
    Found 1-bit register for signal <retry_cnt<11>>.
    Found 1-bit register for signal <retry_cnt<10>>.
    Found 1-bit register for signal <pi_dqs_found_err_r<0>>.
    Found 1-bit register for signal <pi_dqs_found_err_r<1>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><5>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><4>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><3>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><2>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><1>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><0>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><11>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><10>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><9>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><8>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><7>>.
    Found 1-bit register for signal <rd_byte_data_offset<0><6>>.
    Found 2-bit register for signal <pi_rst_stg1_cal>.
    Found 3-bit register for signal <final_do_index<0>>.
    Found 1-bit register for signal <final_data_offset<0><5>>.
    Found 1-bit register for signal <final_data_offset<0><4>>.
    Found 1-bit register for signal <final_data_offset<0><3>>.
    Found 1-bit register for signal <final_data_offset<0><2>>.
    Found 1-bit register for signal <final_data_offset<0><1>>.
    Found 1-bit register for signal <final_data_offset<0><0>>.
    Found 1-bit register for signal <final_data_offset_mc<0><5>>.
    Found 1-bit register for signal <final_data_offset_mc<0><4>>.
    Found 1-bit register for signal <final_data_offset_mc<0><3>>.
    Found 1-bit register for signal <final_data_offset_mc<0><2>>.
    Found 1-bit register for signal <final_data_offset_mc<0><1>>.
    Found 1-bit register for signal <final_data_offset_mc<0><0>>.
    Found 1-bit register for signal <final_data_offset<0><11>>.
    Found 1-bit register for signal <final_data_offset<0><10>>.
    Found 1-bit register for signal <final_data_offset<0><9>>.
    Found 1-bit register for signal <final_data_offset<0><8>>.
    Found 1-bit register for signal <final_data_offset<0><7>>.
    Found 1-bit register for signal <final_data_offset<0><6>>.
    Found 1-bit register for signal <final_data_offset_mc<0><11>>.
    Found 1-bit register for signal <final_data_offset_mc<0><10>>.
    Found 1-bit register for signal <final_data_offset_mc<0><9>>.
    Found 1-bit register for signal <final_data_offset_mc<0><8>>.
    Found 1-bit register for signal <final_data_offset_mc<0><7>>.
    Found 1-bit register for signal <final_data_offset_mc<0><6>>.
    Found 1-bit register for signal <pi_dqs_found_err>.
    Found 2-bit register for signal <pi_dqs_found_all_bank>.
    Found finite state machine <FSM_5> for signal <fine_adj_state_r>.
    -----------------------------------------------------------------------
    | States             | 16                                             |
    | Transitions        | 44                                             |
    | Inputs             | 22                                             |
    | Outputs            | 9                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit subtractor for signal <n0661> created at line 572.
    Found 7-bit subtractor for signal <GND_108_o_GND_108_o_sub_232_OUT> created at line 977.
    Found 7-bit subtractor for signal <GND_108_o_GND_108_o_sub_244_OUT> created at line 992.
    Found 6-bit adder for signal <inc_cnt[5]_GND_108_o_add_43_OUT> created at line 464.
    Found 6-bit adder for signal <n0741> created at line 506.
    Found 6-bit adder for signal <stable_pass_cnt[5]_GND_108_o_add_97_OUT> created at line 552.
    Found 3-bit adder for signal <ctl_lane_cnt[2]_GND_108_o_add_130_OUT> created at line 600.
    Found 2-bit adder for signal <rnk_cnt_r[1]_GND_108_o_add_178_OUT> created at line 653.
    Found 10-bit adder for signal <retry_cnt[9]_GND_108_o_add_210_OUT> created at line 930.
    Found 10-bit adder for signal <retry_cnt[19]_GND_108_o_add_214_OUT> created at line 940.
    Found 3-bit adder for signal <final_do_index[0][2]_GND_108_o_add_266_OUT> created at line 1148.
    Found 4-bit subtractor for signal <GND_108_o_GND_108_o_sub_31_OUT<3:0>> created at line 381.
    Found 6-bit subtractor for signal <GND_108_o_GND_108_o_sub_123_OUT<5:0>> created at line 591.
    Found 6-bit subtractor for signal <GND_108_o_GND_108_o_sub_126_OUT<5:0>> created at line 593.
    Found 6-bit subtractor for signal <GND_108_o_GND_108_o_sub_258_OUT<5:0>> created at line 1122.
    Found 6-bit subtractor for signal <GND_108_o_GND_108_o_sub_271_OUT<5:0>> created at line 1165.
    Found 6-bit 3-to-1 multiplexer for signal <_n1043> created at line 1081.
    Found 4-bit comparator greater for signal <GND_108_o_detect_rd_cnt[3]_LessThan_30_o> created at line 380
    Found 6-bit comparator greater for signal <GND_108_o_inc_cnt[5]_LessThan_57_o> created at line 500
    Found 6-bit comparator greater for signal <GND_108_o_stable_pass_cnt[5]_LessThan_58_o> created at line 500
    Found 6-bit comparator greater for signal <n0075> created at line 507
    Found 6-bit comparator greater for signal <inc_cnt[5]_PWR_107_o_LessThan_104_o> created at line 518
    Found 6-bit comparator greater for signal <stable_pass_cnt[5]_GND_108_o_LessThan_67_o> created at line 518
    Found 6-bit comparator greater for signal <PWR_107_o_first_fail_taps[5]_LessThan_105_o> created at line 562
    Found 6-bit comparator greater for signal <GND_108_o_dec_cnt[5]_LessThan_133_o> created at line 604
    Found 6-bit comparator greater for signal <GND_108_o_init_dec_cnt[5]_LessThan_134_o> created at line 604
    Found 6-bit comparator greater for signal <rnk_cnt_r[0]_GND_108_o_LessThan_202_o> created at line 889
    Found 6-bit comparator greater for signal <rnk_cnt_r[0]_GND_108_o_LessThan_205_o> created at line 899
    Found 2-bit comparator lessequal for signal <n0415> created at line 976
    Found 6-bit comparator lessequal for signal <final_do_max[0][5]_rank_final_loop[0].final_do_cand[0][5]_LessThan_257_o> created at line 1120
    Summary:
	inferred  15 Adder/Subtractor(s).
	inferred 173 D-type flip-flop(s).
	inferred  13 Comparator(s).
	inferred  31 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_dqs_found_cal> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_rdlvl>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_rdlvl.v".
        TCQ = 100
        nCK_PER_CLK = 4
        CLK_PERIOD = 6664
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_WIDTH = 8
        RANKS = 1
        PER_BIT_DESKEW = "OFF"
        SIM_CAL_OPTION = "NONE"
        DEBUG_PORT = "ON"
        DRAM_TYPE = "DDR3"
        OCAL_EN = "ON"
    Set property "KEEP = TRUE" for signal <rdlvl_stg1_done>.
    Set property "MAX_FANOUT = 30" for signal <rdlvl_stg1_done>.
WARNING:Xst:647 - Input <dbg_sel_idel_cpt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbg_idel_up_all> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbg_idel_down_all> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbg_idel_up_cpt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbg_idel_down_cpt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dbg_sel_all_idel_cpt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dbg_phy_rdlvl<255:234>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dbg_phy_rdlvl<169:99>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Register <pat0_match_rise1_r<7>> equivalent to <idel_pat0_match_rise1_r<7>> has been removed
    Register <pat1_match_rise1_r<3>> equivalent to <idel_pat1_match_rise1_r<3>> has been removed
    Register <pat0_match_rise1_r<3>> equivalent to <idel_pat0_match_rise1_r<3>> has been removed
    Register <pat1_match_rise1_r<4>> equivalent to <idel_pat1_match_rise1_r<4>> has been removed
    Register <pat0_match_rise1_r<0>> equivalent to <idel_pat0_match_rise1_r<0>> has been removed
    Register <pat1_match_rise1_r<5>> equivalent to <idel_pat0_match_rise1_r<5>> has been removed
    Register <idel_pat1_match_rise1_r<5>> equivalent to <idel_pat0_match_rise1_r<5>> has been removed
    Register <pat1_match_rise1_r<0>> equivalent to <idel_pat1_match_rise1_r<0>> has been removed
    Register <pat0_match_rise2_r<6>> equivalent to <idel_pat0_match_rise2_r<6>> has been removed
    Register <pat0_match_rise2_r<1>> equivalent to <idel_pat1_match_rise2_r<1>> has been removed
    Register <pat1_match_rise1_r<1>> equivalent to <idel_pat0_match_rise1_r<1>> has been removed
    Register <idel_pat1_match_rise1_r<1>> equivalent to <idel_pat0_match_rise1_r<1>> has been removed
    Register <pat1_match_rise1_r<2>> equivalent to <idel_pat0_match_rise1_r<2>> has been removed
    Register <pat0_match_rise1_r<2>> equivalent to <idel_pat0_match_rise1_r<2>> has been removed
    Register <pat1_match_fall1_r<0>> equivalent to <idel_pat0_match_fall1_r<0>> has been removed
    Register <pat0_match_fall3_r<6>> equivalent to <idel_pat0_match_fall3_r<6>> has been removed
    Register <idel_pat1_match_fall3_r<6>> equivalent to <idel_pat0_match_fall3_r<6>> has been removed
    Register <pat1_match_rise2_r<1>> equivalent to <idel_pat0_match_rise2_r<1>> has been removed
    Register <pat1_match_rise0_r<1>> equivalent to <idel_pat0_match_rise0_r<1>> has been removed
    Register <idel_pat1_match_rise0_r<1>> equivalent to <idel_pat0_match_rise0_r<1>> has been removed
    Register <idel_pat1_match_fall3_r<1>> equivalent to <idel_pat0_match_fall3_r<1>> has been removed
    Register <pat1_match_fall0_r<3>> equivalent to <idel_pat0_match_fall0_r<3>> has been removed
    Register <pat1_match_rise3_r<4>> equivalent to <idel_pat0_match_rise3_r<4>> has been removed
    Register <pat0_match_rise2_r<5>> equivalent to <idel_pat1_match_rise2_r<5>> has been removed
    Register <pat1_match_rise2_r<6>> equivalent to <idel_pat1_match_rise2_r<6>> has been removed
    Register <pat0_match_fall3_r<0>> equivalent to <idel_pat0_match_fall3_r<0>> has been removed
    Register <pat1_match_rise2_r<7>> equivalent to <idel_pat0_match_rise2_r<7>> has been removed
    Register <idel_pat1_match_rise2_r<7>> equivalent to <idel_pat0_match_rise2_r<7>> has been removed
    Register <pat1_match_rise2_r<5>> equivalent to <idel_pat0_match_rise2_r<5>> has been removed
    Register <pat1_match_rise2_r<2>> equivalent to <idel_pat1_match_rise2_r<2>> has been removed
    Register <pat1_match_rise2_r<3>> equivalent to <idel_pat0_match_rise2_r<3>> has been removed
    Register <idel_pat1_match_rise2_r<3>> equivalent to <idel_pat0_match_rise2_r<3>> has been removed
    Register <idel_pat1_match_rise3_r<5>> equivalent to <idel_pat0_match_rise3_r<5>> has been removed
    Register <pat1_match_fall0_r<2>> equivalent to <idel_pat1_match_fall0_r<2>> has been removed
    Register <pat0_match_fall3_r<2>> equivalent to <idel_pat0_match_fall3_r<2>> has been removed
    Register <idel_pat1_match_fall3_r<2>> equivalent to <idel_pat0_match_fall3_r<2>> has been removed
    Register <pat0_match_fall3_r<4>> equivalent to <idel_pat0_match_fall3_r<4>> has been removed
    Register <idel_pat1_match_fall3_r<5>> equivalent to <idel_pat0_match_fall3_r<5>> has been removed
    Register <pat1_match_rise3_r<2>> equivalent to <idel_pat1_match_rise3_r<2>> has been removed
    Register <pat0_match_rise3_r<2>> equivalent to <idel_pat1_match_rise3_r<2>> has been removed
    Register <pat1_match_rise3_r<0>> equivalent to <idel_pat0_match_rise3_r<0>> has been removed
    Register <pat1_match_rise1_r<7>> equivalent to <idel_pat1_match_rise1_r<7>> has been removed
    Register <pat0_match_fall1_r<5>> equivalent to <idel_pat0_match_fall1_r<5>> has been removed
    Register <pat1_match_fall3_r<7>> equivalent to <idel_pat1_match_fall3_r<7>> has been removed
    Register <pat0_match_fall3_r<7>> equivalent to <idel_pat1_match_fall3_r<7>> has been removed
    Register <pat0_match_rise0_r<3>> equivalent to <idel_pat0_match_rise0_r<3>> has been removed
    Register <idel_pat1_match_rise0_r<3>> equivalent to <idel_pat0_match_rise0_r<3>> has been removed
    Register <pat1_match_fall2_r<2>> equivalent to <idel_pat0_match_fall2_r<2>> has been removed
    Register <pat1_match_fall3_r<5>> equivalent to <pat0_match_fall3_r<5>> has been removed
    Register <pat1_match_fall3_r<0>> equivalent to <idel_pat1_match_fall3_r<0>> has been removed
    Register <cal1_cnt_cpt_timing_r> equivalent to <rd_mux_sel_r> has been removed
    Register <pat1_match_rise3_r<1>> equivalent to <pat0_match_rise3_r<1>> has been removed
    Register <pat0_match_rise3_r<3>> equivalent to <idel_pat1_match_rise3_r<3>> has been removed
    Register <pat1_match_rise2_r<4>> equivalent to <idel_pat1_match_rise2_r<4>> has been removed
    Register <pat0_match_rise2_r<4>> equivalent to <idel_pat1_match_rise2_r<4>> has been removed
    Register <pat0_match_rise3_r<0>> equivalent to <idel_pat1_match_rise3_r<0>> has been removed
    Register <pat1_match_fall2_r<5>> equivalent to <idel_pat1_match_fall2_r<5>> has been removed
    Register <pat0_match_fall2_r<5>> equivalent to <idel_pat1_match_fall2_r<5>> has been removed
    Register <pat1_match_fall3_r<1>> equivalent to <pat0_match_fall3_r<1>> has been removed
    Register <pat1_match_rise0_r<6>> equivalent to <idel_pat0_match_rise0_r<6>> has been removed
    Register <pat1_match_rise0_r<4>> equivalent to <idel_pat0_match_rise0_r<4>> has been removed
    Register <pat0_match_rise0_r<4>> equivalent to <idel_pat0_match_rise0_r<4>> has been removed
    Register <pat0_match_rise0_r<6>> equivalent to <idel_pat1_match_rise0_r<6>> has been removed
    Register <pat0_match_rise0_r<2>> equivalent to <idel_pat1_match_rise0_r<2>> has been removed
    Register <pat1_match_rise3_r<3>> equivalent to <idel_pat0_match_rise3_r<3>> has been removed
    Register <pat0_match_rise3_r<7>> equivalent to <idel_pat1_match_rise3_r<7>> has been removed
    Register <pat1_match_rise0_r<0>> equivalent to <idel_pat0_match_rise0_r<0>> has been removed
    Register <pat0_match_rise0_r<0>> equivalent to <idel_pat0_match_rise0_r<0>> has been removed
    Register <pat1_match_rise0_r<5>> equivalent to <idel_pat0_match_rise0_r<5>> has been removed
    Register <idel_pat1_match_rise0_r<5>> equivalent to <idel_pat0_match_rise0_r<5>> has been removed
    Register <pat0_match_rise3_r<4>> equivalent to <idel_pat1_match_rise3_r<4>> has been removed
    Register <pat1_match_rise3_r<5>> equivalent to <pat0_match_rise3_r<5>> has been removed
    Register <pat0_match_fall2_r<4>> equivalent to <idel_pat0_match_fall2_r<4>> has been removed
    Register <idel_pat1_match_fall2_r<4>> equivalent to <idel_pat0_match_fall2_r<4>> has been removed
    Register <pat1_match_fall1_r<4>> equivalent to <idel_pat0_match_fall1_r<4>> has been removed
    Register <dlyce_dq_r<0>> equivalent to <dlyce_dq_r<7>> has been removed
    Register <dlyce_dq_r<1>> equivalent to <dlyce_dq_r<7>> has been removed
    Register <dlyce_dq_r<2>> equivalent to <dlyce_dq_r<7>> has been removed
    Register <dlyce_dq_r<3>> equivalent to <dlyce_dq_r<7>> has been removed
    Register <dlyce_dq_r<4>> equivalent to <dlyce_dq_r<7>> has been removed
    Register <dlyce_dq_r<5>> equivalent to <dlyce_dq_r<7>> has been removed
    Register <dlyce_dq_r<6>> equivalent to <dlyce_dq_r<7>> has been removed
    Register <pat1_match_rise3_r<6>> equivalent to <idel_pat1_match_rise3_r<6>> has been removed
    Register <pat0_match_rise3_r<6>> equivalent to <idel_pat1_match_rise3_r<6>> has been removed
    Register <pat1_match_fall0_r<7>> equivalent to <idel_pat0_match_fall0_r<7>> has been removed
    Register <pat0_match_fall1_r<1>> equivalent to <idel_pat0_match_fall1_r<1>> has been removed
    Register <pat1_match_fall1_r<6>> equivalent to <idel_pat0_match_fall1_r<6>> has been removed
    Register <idel_pat1_match_fall1_r<6>> equivalent to <idel_pat0_match_fall1_r<6>> has been removed
    Register <pat0_match_rise1_r<4>> equivalent to <idel_pat0_match_rise1_r<4>> has been removed
    Register <pat1_match_fall1_r<7>> equivalent to <idel_pat0_match_fall1_r<7>> has been removed
    Register <pat0_match_fall1_r<7>> equivalent to <idel_pat0_match_fall1_r<7>> has been removed
    Register <pat1_match_fall1_r<3>> equivalent to <idel_pat0_match_fall1_r<3>> has been removed
    Register <pat0_match_fall1_r<3>> equivalent to <idel_pat0_match_fall1_r<3>> has been removed
    Register <pat0_match_fall1_r<4>> equivalent to <idel_pat1_match_fall1_r<4>> has been removed
    Register <pat1_match_fall1_r<5>> equivalent to <idel_pat1_match_fall1_r<5>> has been removed
    Register <pat0_match_fall1_r<0>> equivalent to <idel_pat1_match_fall1_r<0>> has been removed
    Register <pat1_match_fall1_r<1>> equivalent to <idel_pat1_match_fall1_r<1>> has been removed
    Register <pat1_match_fall1_r<2>> equivalent to <idel_pat0_match_fall1_r<2>> has been removed
    Register <idel_pat1_match_fall1_r<2>> equivalent to <idel_pat0_match_fall1_r<2>> has been removed
    Register <pat0_match_fall0_r<7>> equivalent to <idel_pat1_match_fall0_r<7>> has been removed
    Register <pat1_match_fall2_r<1>> equivalent to <idel_pat1_match_fall2_r<1>> has been removed
    Register <pat0_match_fall2_r<1>> equivalent to <idel_pat1_match_fall2_r<1>> has been removed
    Register <pat1_match_fall0_r<4>> equivalent to <idel_pat0_match_fall0_r<4>> has been removed
    Register <idel_pat1_match_fall0_r<4>> equivalent to <idel_pat0_match_fall0_r<4>> has been removed
    Register <pat1_match_fall0_r<5>> equivalent to <idel_pat0_match_fall0_r<5>> has been removed
    Register <pat0_match_fall0_r<5>> equivalent to <idel_pat0_match_fall0_r<5>> has been removed
    Register <pat0_match_fall2_r<0>> equivalent to <idel_pat0_match_fall2_r<0>> has been removed
    Register <idel_pat1_match_fall2_r<0>> equivalent to <idel_pat0_match_fall2_r<0>> has been removed
    Register <pat0_match_fall0_r<6>> equivalent to <idel_pat0_match_fall0_r<6>> has been removed
    Register <pat1_match_fall0_r<1>> equivalent to <idel_pat0_match_fall0_r<1>> has been removed
    Register <pat0_match_fall0_r<1>> equivalent to <idel_pat0_match_fall0_r<1>> has been removed
    Register <pat0_match_fall2_r<6>> equivalent to <idel_pat1_match_fall2_r<6>> has been removed
    Register <pat1_match_fall2_r<7>> equivalent to <idel_pat1_match_fall2_r<7>> has been removed
    Register <pat0_match_fall0_r<2>> equivalent to <idel_pat0_match_fall0_r<2>> has been removed
    Register <pat0_match_fall0_r<3>> equivalent to <idel_pat1_match_fall0_r<3>> has been removed
    Register <pat0_match_fall2_r<2>> equivalent to <idel_pat1_match_fall2_r<2>> has been removed
    Register <pat1_match_fall2_r<3>> equivalent to <idel_pat1_match_fall2_r<3>> has been removed
    Register <pat1_match_rise3_r<7>> equivalent to <idel_pat0_match_rise3_r<7>> has been removed
    Register <pat1_match_rise2_r<0>> equivalent to <idel_pat1_match_rise2_r<0>> has been removed
    Register <pat0_match_rise2_r<0>> equivalent to <idel_pat1_match_rise2_r<0>> has been removed
    Register <pat1_match_fall0_r<0>> equivalent to <idel_pat0_match_fall0_r<0>> has been removed
    Register <idel_pat1_match_fall0_r<0>> equivalent to <idel_pat0_match_fall0_r<0>> has been removed
    Register <pat1_match_fall3_r<4>> equivalent to <idel_pat1_match_fall3_r<4>> has been removed
    Register <idel_pat1_match_rise3_r<1>> equivalent to <idel_pat0_match_rise3_r<1>> has been removed
    Register <pat1_match_fall3_r<3>> equivalent to <idel_pat1_match_fall3_r<3>> has been removed
    Register <pat0_match_fall3_r<3>> equivalent to <idel_pat1_match_fall3_r<3>> has been removed
    Register <pat1_match_fall0_r<6>> equivalent to <idel_pat1_match_fall0_r<6>> has been removed
    Register <pat1_match_fall2_r<6>> equivalent to <idel_pat0_match_fall2_r<6>> has been removed
    Register <pat1_match_rise0_r<2>> equivalent to <idel_pat0_match_rise0_r<2>> has been removed
    Register <pat0_match_rise0_r<7>> equivalent to <idel_pat0_match_rise0_r<7>> has been removed
    Register <idel_pat1_match_rise0_r<7>> equivalent to <idel_pat0_match_rise0_r<7>> has been removed
    Register <pat0_match_rise2_r<2>> equivalent to <idel_pat0_match_rise2_r<2>> has been removed
    Register <pat0_match_fall2_r<7>> equivalent to <idel_pat0_match_fall2_r<7>> has been removed
    Register <pat0_match_fall2_r<3>> equivalent to <idel_pat0_match_fall2_r<3>> has been removed
    Register <pat1_match_rise1_r<6>> equivalent to <idel_pat0_match_rise1_r<6>> has been removed
    Register <pat0_match_rise1_r<6>> equivalent to <idel_pat0_match_rise1_r<6>> has been removed
    Found 24-bit register for signal <dbg_cpt_second_edge_taps>.
    Found 1-bit register for signal <rdlvl_assrt_common>.
    Found 3-bit register for signal <rd_mux_sel_r>.
    Found 1-bit register for signal <mux_rd_rise0_r<0>>.
    Found 1-bit register for signal <mux_rd_fall0_r<0>>.
    Found 1-bit register for signal <mux_rd_rise1_r<0>>.
    Found 1-bit register for signal <mux_rd_fall1_r<0>>.
    Found 1-bit register for signal <mux_rd_rise2_r<0>>.
    Found 1-bit register for signal <mux_rd_fall2_r<0>>.
    Found 1-bit register for signal <mux_rd_rise3_r<0>>.
    Found 1-bit register for signal <mux_rd_fall3_r<0>>.
    Found 1-bit register for signal <mux_rd_rise0_r<1>>.
    Found 1-bit register for signal <mux_rd_fall0_r<1>>.
    Found 1-bit register for signal <mux_rd_rise1_r<1>>.
    Found 1-bit register for signal <mux_rd_fall1_r<1>>.
    Found 1-bit register for signal <mux_rd_rise2_r<1>>.
    Found 1-bit register for signal <mux_rd_fall2_r<1>>.
    Found 1-bit register for signal <mux_rd_rise3_r<1>>.
    Found 1-bit register for signal <mux_rd_fall3_r<1>>.
    Found 1-bit register for signal <mux_rd_rise0_r<2>>.
    Found 1-bit register for signal <mux_rd_fall0_r<2>>.
    Found 1-bit register for signal <mux_rd_rise1_r<2>>.
    Found 1-bit register for signal <mux_rd_fall1_r<2>>.
    Found 1-bit register for signal <mux_rd_rise2_r<2>>.
    Found 1-bit register for signal <mux_rd_fall2_r<2>>.
    Found 1-bit register for signal <mux_rd_rise3_r<2>>.
    Found 1-bit register for signal <mux_rd_fall3_r<2>>.
    Found 1-bit register for signal <mux_rd_rise0_r<3>>.
    Found 1-bit register for signal <mux_rd_fall0_r<3>>.
    Found 1-bit register for signal <mux_rd_rise1_r<3>>.
    Found 1-bit register for signal <mux_rd_fall1_r<3>>.
    Found 1-bit register for signal <mux_rd_rise2_r<3>>.
    Found 1-bit register for signal <mux_rd_fall2_r<3>>.
    Found 1-bit register for signal <mux_rd_rise3_r<3>>.
    Found 1-bit register for signal <mux_rd_fall3_r<3>>.
    Found 1-bit register for signal <mux_rd_rise0_r<4>>.
    Found 1-bit register for signal <mux_rd_fall0_r<4>>.
    Found 1-bit register for signal <mux_rd_rise1_r<4>>.
    Found 1-bit register for signal <mux_rd_fall1_r<4>>.
    Found 1-bit register for signal <mux_rd_rise2_r<4>>.
    Found 1-bit register for signal <mux_rd_fall2_r<4>>.
    Found 1-bit register for signal <mux_rd_rise3_r<4>>.
    Found 1-bit register for signal <mux_rd_fall3_r<4>>.
    Found 1-bit register for signal <mux_rd_rise0_r<5>>.
    Found 1-bit register for signal <mux_rd_fall0_r<5>>.
    Found 1-bit register for signal <mux_rd_rise1_r<5>>.
    Found 1-bit register for signal <mux_rd_fall1_r<5>>.
    Found 1-bit register for signal <mux_rd_rise2_r<5>>.
    Found 1-bit register for signal <mux_rd_fall2_r<5>>.
    Found 1-bit register for signal <mux_rd_rise3_r<5>>.
    Found 1-bit register for signal <mux_rd_fall3_r<5>>.
    Found 1-bit register for signal <mux_rd_rise0_r<6>>.
    Found 1-bit register for signal <mux_rd_fall0_r<6>>.
    Found 1-bit register for signal <mux_rd_rise1_r<6>>.
    Found 1-bit register for signal <mux_rd_fall1_r<6>>.
    Found 1-bit register for signal <mux_rd_rise2_r<6>>.
    Found 1-bit register for signal <mux_rd_fall2_r<6>>.
    Found 1-bit register for signal <mux_rd_rise3_r<6>>.
    Found 1-bit register for signal <mux_rd_fall3_r<6>>.
    Found 1-bit register for signal <mux_rd_rise0_r<7>>.
    Found 1-bit register for signal <mux_rd_fall0_r<7>>.
    Found 1-bit register for signal <mux_rd_rise1_r<7>>.
    Found 1-bit register for signal <mux_rd_fall1_r<7>>.
    Found 1-bit register for signal <mux_rd_rise2_r<7>>.
    Found 1-bit register for signal <mux_rd_fall2_r<7>>.
    Found 1-bit register for signal <mux_rd_rise3_r<7>>.
    Found 1-bit register for signal <mux_rd_fall3_r<7>>.
    Found 1-bit register for signal <mpr_rd_rise0_prev_r>.
    Found 1-bit register for signal <mpr_rd_fall0_prev_r>.
    Found 1-bit register for signal <mpr_rd_rise1_prev_r>.
    Found 1-bit register for signal <mpr_rd_fall1_prev_r>.
    Found 1-bit register for signal <mpr_rd_rise2_prev_r>.
    Found 1-bit register for signal <mpr_rd_fall2_prev_r>.
    Found 1-bit register for signal <mpr_rd_rise3_prev_r>.
    Found 1-bit register for signal <mpr_rd_fall3_prev_r>.
    Found 3-bit register for signal <stable_idel_cnt>.
    Found 1-bit register for signal <inhibit_edge_detect_r>.
    Found 1-bit register for signal <idel_mpr_pat_detect_r>.
    Found 1-bit register for signal <mux_rd_valid_r>.
    Found 1-bit register for signal <dqs_po_dec_done_r1>.
    Found 1-bit register for signal <dqs_po_dec_done_r2>.
    Found 1-bit register for signal <fine_dly_dec_done_r2>.
    Found 1-bit register for signal <pi_fine_dly_dec_done>.
    Found 4-bit register for signal <wait_cnt_r>.
    Found 6-bit register for signal <pi_rdval_cnt>.
    Found 1-bit register for signal <pi_cnt_dec>.
    Found 1-bit register for signal <fine_dly_dec_done_r1>.
    Found 1-bit register for signal <pi_en_stg2_f_timing>.
    Found 1-bit register for signal <pi_stg2_f_incdec_timing>.
    Found 1-bit register for signal <pi_en_stg2_f>.
    Found 1-bit register for signal <pi_stg2_f_incdec>.
    Found 4-bit register for signal <done_cnt>.
    Found 1-bit register for signal <pi_stg2_load_timing>.
    Found 6-bit register for signal <pi_stg2_reg_l_timing>.
    Found 1-bit register for signal <pi_stg2_load>.
    Found 6-bit register for signal <pi_stg2_reg_l>.
    Found 2-bit register for signal <regl_rank_cnt>.
    Found 3-bit register for signal <regl_dqs_cnt>.
    Found 3-bit register for signal <regl_dqs_cnt_r>.
    Found 1-bit register for signal <dlyce_dq_r<7>>.
    Found 1-bit register for signal <dlyinc_dq_r>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><0><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><0><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><0><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><0><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><0><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><1><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><1><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><1><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><1><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><1><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><2><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><2><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><2><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><2><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><2><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><3><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><3><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><3><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><3><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><3><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><4><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><4><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><4><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><4><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><4><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><5><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><5><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><5><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><5><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><5><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><6><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><6><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><6><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><6><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><6><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><7><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><7><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><7><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><7><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><7><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><8><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><8><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><8><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><8><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><8><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><9><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><9><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><9><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><9><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><9><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><10><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><10><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><10><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><10><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><10><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><11><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><11><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><11><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><11><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><11><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><12><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><12><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><12><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><12><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><12><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><13><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><13><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><13><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><13><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><13><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><14><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><14><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><14><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><14><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><14><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><15><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><15><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><15><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><15><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><15><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><16><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><16><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><16><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><16><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><16><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><17><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><17><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><17><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><17><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><17><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><18><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><18><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><18><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><18><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><18><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><19><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><19><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><19><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><19><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><19><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><20><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><20><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><20><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><20><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><20><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><21><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><21><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><21><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><21><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><21><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><22><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><22><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><22><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><22><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><22><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><23><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><23><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><23><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><23><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><23><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><24><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><24><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><24><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><24><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><24><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><25><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><25><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><25><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><25><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><25><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><26><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><26><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><26><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><26><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><26><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><27><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><27><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><27><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><27><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><27><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><28><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><28><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><28><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><28><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><28><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><29><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><29><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><29><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><29><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><29><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><30><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><30><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><30><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><30><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><30><0>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><31><4>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><31><3>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><31><2>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><31><1>>.
    Found 1-bit register for signal <dlyval_dq_reg_r<0><31><0>>.
    Found 160-bit register for signal <dlyval_dq>.
    Found 1-bit register for signal <cal1_wait_cnt_en_r>.
    Found 5-bit register for signal <cal1_wait_cnt_r>.
    Found 1-bit register for signal <cal1_wait_r>.
    Found 1-bit register for signal <rdlvl_prech_req>.
    Found 1-bit register for signal <sr_rise0_r<0>>.
    Found 1-bit register for signal <sr_fall0_r<0>>.
    Found 1-bit register for signal <sr_rise1_r<0>>.
    Found 1-bit register for signal <sr_fall1_r<0>>.
    Found 1-bit register for signal <sr_rise2_r<0>>.
    Found 1-bit register for signal <sr_fall2_r<0>>.
    Found 1-bit register for signal <sr_rise3_r<0>>.
    Found 1-bit register for signal <sr_fall3_r<0>>.
    Found 1-bit register for signal <sr_rise0_r<1>>.
    Found 1-bit register for signal <sr_fall0_r<1>>.
    Found 1-bit register for signal <sr_rise1_r<1>>.
    Found 1-bit register for signal <sr_fall1_r<1>>.
    Found 1-bit register for signal <sr_rise2_r<1>>.
    Found 1-bit register for signal <sr_fall2_r<1>>.
    Found 1-bit register for signal <sr_rise3_r<1>>.
    Found 1-bit register for signal <sr_fall3_r<1>>.
    Found 1-bit register for signal <sr_rise0_r<2>>.
    Found 1-bit register for signal <sr_fall0_r<2>>.
    Found 1-bit register for signal <sr_rise1_r<2>>.
    Found 1-bit register for signal <sr_fall1_r<2>>.
    Found 1-bit register for signal <sr_rise2_r<2>>.
    Found 1-bit register for signal <sr_fall2_r<2>>.
    Found 1-bit register for signal <sr_rise3_r<2>>.
    Found 1-bit register for signal <sr_fall3_r<2>>.
    Found 1-bit register for signal <sr_rise0_r<3>>.
    Found 1-bit register for signal <sr_fall0_r<3>>.
    Found 1-bit register for signal <sr_rise1_r<3>>.
    Found 1-bit register for signal <sr_fall1_r<3>>.
    Found 1-bit register for signal <sr_rise2_r<3>>.
    Found 1-bit register for signal <sr_fall2_r<3>>.
    Found 1-bit register for signal <sr_rise3_r<3>>.
    Found 1-bit register for signal <sr_fall3_r<3>>.
    Found 1-bit register for signal <sr_rise0_r<4>>.
    Found 1-bit register for signal <sr_fall0_r<4>>.
    Found 1-bit register for signal <sr_rise1_r<4>>.
    Found 1-bit register for signal <sr_fall1_r<4>>.
    Found 1-bit register for signal <sr_rise2_r<4>>.
    Found 1-bit register for signal <sr_fall2_r<4>>.
    Found 1-bit register for signal <sr_rise3_r<4>>.
    Found 1-bit register for signal <sr_fall3_r<4>>.
    Found 1-bit register for signal <sr_rise0_r<5>>.
    Found 1-bit register for signal <sr_fall0_r<5>>.
    Found 1-bit register for signal <sr_rise1_r<5>>.
    Found 1-bit register for signal <sr_fall1_r<5>>.
    Found 1-bit register for signal <sr_rise2_r<5>>.
    Found 1-bit register for signal <sr_fall2_r<5>>.
    Found 1-bit register for signal <sr_rise3_r<5>>.
    Found 1-bit register for signal <sr_fall3_r<5>>.
    Found 1-bit register for signal <sr_rise0_r<6>>.
    Found 1-bit register for signal <sr_fall0_r<6>>.
    Found 1-bit register for signal <sr_rise1_r<6>>.
    Found 1-bit register for signal <sr_fall1_r<6>>.
    Found 1-bit register for signal <sr_rise2_r<6>>.
    Found 1-bit register for signal <sr_fall2_r<6>>.
    Found 1-bit register for signal <sr_rise3_r<6>>.
    Found 1-bit register for signal <sr_fall3_r<6>>.
    Found 1-bit register for signal <sr_rise0_r<7>>.
    Found 1-bit register for signal <sr_fall0_r<7>>.
    Found 1-bit register for signal <sr_rise1_r<7>>.
    Found 1-bit register for signal <sr_fall1_r<7>>.
    Found 1-bit register for signal <sr_rise2_r<7>>.
    Found 1-bit register for signal <sr_fall2_r<7>>.
    Found 1-bit register for signal <sr_rise3_r<7>>.
    Found 1-bit register for signal <sr_fall3_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<0>>.
    Found 1-bit register for signal <idel_pat1_match_rise0_r<0>>.
    Found 1-bit register for signal <idel_pat1_match_rise1_r<0>>.
    Found 1-bit register for signal <idel_pat1_match_fall1_r<0>>.
    Found 1-bit register for signal <idel_pat1_match_rise2_r<0>>.
    Found 1-bit register for signal <idel_pat1_match_rise3_r<0>>.
    Found 1-bit register for signal <idel_pat1_match_fall3_r<0>>.
    Found 1-bit register for signal <pat0_match_fall0_r<0>>.
    Found 1-bit register for signal <pat1_match_fall2_r<0>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<1>>.
    Found 1-bit register for signal <idel_pat1_match_fall0_r<1>>.
    Found 1-bit register for signal <idel_pat1_match_fall1_r<1>>.
    Found 1-bit register for signal <idel_pat1_match_rise2_r<1>>.
    Found 1-bit register for signal <idel_pat1_match_fall2_r<1>>.
    Found 1-bit register for signal <pat0_match_rise0_r<1>>.
    Found 1-bit register for signal <pat0_match_rise1_r<1>>.
    Found 1-bit register for signal <pat0_match_rise3_r<1>>.
    Found 1-bit register for signal <pat0_match_fall3_r<1>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<2>>.
    Found 1-bit register for signal <idel_pat1_match_rise0_r<2>>.
    Found 1-bit register for signal <idel_pat1_match_fall0_r<2>>.
    Found 1-bit register for signal <idel_pat1_match_rise1_r<2>>.
    Found 1-bit register for signal <idel_pat1_match_rise2_r<2>>.
    Found 1-bit register for signal <idel_pat1_match_fall2_r<2>>.
    Found 1-bit register for signal <idel_pat1_match_rise3_r<2>>.
    Found 1-bit register for signal <pat0_match_fall1_r<2>>.
    Found 1-bit register for signal <pat1_match_fall3_r<2>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<3>>.
    Found 1-bit register for signal <idel_pat1_match_fall0_r<3>>.
    Found 1-bit register for signal <idel_pat1_match_rise1_r<3>>.
    Found 1-bit register for signal <idel_pat1_match_fall1_r<3>>.
    Found 1-bit register for signal <idel_pat1_match_fall2_r<3>>.
    Found 1-bit register for signal <idel_pat1_match_rise3_r<3>>.
    Found 1-bit register for signal <idel_pat1_match_fall3_r<3>>.
    Found 1-bit register for signal <pat0_match_rise2_r<3>>.
    Found 1-bit register for signal <pat1_match_rise0_r<3>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<4>>.
    Found 1-bit register for signal <idel_pat1_match_rise0_r<4>>.
    Found 1-bit register for signal <idel_pat1_match_rise1_r<4>>.
    Found 1-bit register for signal <idel_pat1_match_fall1_r<4>>.
    Found 1-bit register for signal <idel_pat1_match_rise2_r<4>>.
    Found 1-bit register for signal <idel_pat1_match_rise3_r<4>>.
    Found 1-bit register for signal <idel_pat1_match_fall3_r<4>>.
    Found 1-bit register for signal <pat0_match_fall0_r<4>>.
    Found 1-bit register for signal <pat1_match_fall2_r<4>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<5>>.
    Found 1-bit register for signal <idel_pat1_match_fall0_r<5>>.
    Found 1-bit register for signal <idel_pat1_match_fall1_r<5>>.
    Found 1-bit register for signal <idel_pat1_match_rise2_r<5>>.
    Found 1-bit register for signal <idel_pat1_match_fall2_r<5>>.
    Found 1-bit register for signal <pat0_match_rise0_r<5>>.
    Found 1-bit register for signal <pat0_match_rise1_r<5>>.
    Found 1-bit register for signal <pat0_match_rise3_r<5>>.
    Found 1-bit register for signal <pat0_match_fall3_r<5>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<6>>.
    Found 1-bit register for signal <idel_pat1_match_rise0_r<6>>.
    Found 1-bit register for signal <idel_pat1_match_fall0_r<6>>.
    Found 1-bit register for signal <idel_pat1_match_rise1_r<6>>.
    Found 1-bit register for signal <idel_pat1_match_rise2_r<6>>.
    Found 1-bit register for signal <idel_pat1_match_fall2_r<6>>.
    Found 1-bit register for signal <idel_pat1_match_rise3_r<6>>.
    Found 1-bit register for signal <pat0_match_fall1_r<6>>.
    Found 1-bit register for signal <pat1_match_fall3_r<6>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_fall0_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_rise1_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_fall1_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_rise2_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_fall2_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_rise3_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_fall3_r<7>>.
    Found 1-bit register for signal <idel_pat1_match_fall0_r<7>>.
    Found 1-bit register for signal <idel_pat1_match_rise1_r<7>>.
    Found 1-bit register for signal <idel_pat1_match_fall1_r<7>>.
    Found 1-bit register for signal <idel_pat1_match_fall2_r<7>>.
    Found 1-bit register for signal <idel_pat1_match_rise3_r<7>>.
    Found 1-bit register for signal <idel_pat1_match_fall3_r<7>>.
    Found 1-bit register for signal <pat0_match_rise2_r<7>>.
    Found 1-bit register for signal <pat1_match_rise0_r<7>>.
    Found 1-bit register for signal <idel_pat0_match_rise0_and_r>.
    Found 1-bit register for signal <idel_pat0_match_fall0_and_r>.
    Found 1-bit register for signal <idel_pat0_match_rise1_and_r>.
    Found 1-bit register for signal <idel_pat0_match_fall1_and_r>.
    Found 1-bit register for signal <idel_pat0_match_rise2_and_r>.
    Found 1-bit register for signal <idel_pat0_match_fall2_and_r>.
    Found 1-bit register for signal <idel_pat0_match_rise3_and_r>.
    Found 1-bit register for signal <idel_pat0_match_fall3_and_r>.
    Found 1-bit register for signal <idel_pat0_data_match_r>.
    Found 1-bit register for signal <idel_pat1_match_rise0_and_r>.
    Found 1-bit register for signal <idel_pat1_match_fall0_and_r>.
    Found 1-bit register for signal <idel_pat1_match_rise1_and_r>.
    Found 1-bit register for signal <idel_pat1_match_fall1_and_r>.
    Found 1-bit register for signal <idel_pat1_match_rise2_and_r>.
    Found 1-bit register for signal <idel_pat1_match_fall2_and_r>.
    Found 1-bit register for signal <idel_pat1_match_rise3_and_r>.
    Found 1-bit register for signal <idel_pat1_match_fall3_and_r>.
    Found 1-bit register for signal <idel_pat1_data_match_r>.
    Found 1-bit register for signal <idel_pat_data_match_r>.
    Found 1-bit register for signal <pat0_match_rise0_and_r>.
    Found 1-bit register for signal <pat0_match_fall0_and_r>.
    Found 1-bit register for signal <pat0_match_rise1_and_r>.
    Found 1-bit register for signal <pat0_match_fall1_and_r>.
    Found 1-bit register for signal <pat0_match_rise2_and_r>.
    Found 1-bit register for signal <pat0_match_fall2_and_r>.
    Found 1-bit register for signal <pat0_match_rise3_and_r>.
    Found 1-bit register for signal <pat0_match_fall3_and_r>.
    Found 1-bit register for signal <pat0_data_match_r>.
    Found 1-bit register for signal <pat1_match_rise0_and_r>.
    Found 1-bit register for signal <pat1_match_fall0_and_r>.
    Found 1-bit register for signal <pat1_match_rise1_and_r>.
    Found 1-bit register for signal <pat1_match_fall1_and_r>.
    Found 1-bit register for signal <pat1_match_rise2_and_r>.
    Found 1-bit register for signal <pat1_match_fall2_and_r>.
    Found 1-bit register for signal <pat1_match_rise3_and_r>.
    Found 1-bit register for signal <pat1_match_fall3_and_r>.
    Found 1-bit register for signal <pat1_data_match_r>.
    Found 1-bit register for signal <rdlvl_stg1_start_r>.
    Found 1-bit register for signal <mpr_rdlvl_done_r1>.
    Found 1-bit register for signal <mpr_rdlvl_done_r2>.
    Found 1-bit register for signal <mpr_rdlvl_start_r>.
    Found 4-bit register for signal <cnt_shift_r>.
    Found 1-bit register for signal <sr_valid_r>.
    Found 1-bit register for signal <mpr_valid_r>.
    Found 1-bit register for signal <store_sr_r>.
    Found 1-bit register for signal <prev_sr_rise0_r<0>>.
    Found 1-bit register for signal <prev_sr_fall0_r<0>>.
    Found 1-bit register for signal <prev_sr_rise1_r<0>>.
    Found 1-bit register for signal <prev_sr_fall1_r<0>>.
    Found 1-bit register for signal <prev_sr_rise2_r<0>>.
    Found 1-bit register for signal <prev_sr_fall2_r<0>>.
    Found 1-bit register for signal <prev_sr_rise3_r<0>>.
    Found 1-bit register for signal <prev_sr_fall3_r<0>>.
    Found 1-bit register for signal <old_sr_rise0_r<0>>.
    Found 1-bit register for signal <old_sr_fall0_r<0>>.
    Found 1-bit register for signal <old_sr_rise1_r<0>>.
    Found 1-bit register for signal <old_sr_fall1_r<0>>.
    Found 1-bit register for signal <old_sr_rise2_r<0>>.
    Found 1-bit register for signal <old_sr_fall2_r<0>>.
    Found 1-bit register for signal <old_sr_rise3_r<0>>.
    Found 1-bit register for signal <old_sr_fall3_r<0>>.
    Found 1-bit register for signal <prev_sr_rise0_r<1>>.
    Found 1-bit register for signal <prev_sr_fall0_r<1>>.
    Found 1-bit register for signal <prev_sr_rise1_r<1>>.
    Found 1-bit register for signal <prev_sr_fall1_r<1>>.
    Found 1-bit register for signal <prev_sr_rise2_r<1>>.
    Found 1-bit register for signal <prev_sr_fall2_r<1>>.
    Found 1-bit register for signal <prev_sr_rise3_r<1>>.
    Found 1-bit register for signal <prev_sr_fall3_r<1>>.
    Found 1-bit register for signal <old_sr_rise0_r<1>>.
    Found 1-bit register for signal <old_sr_fall0_r<1>>.
    Found 1-bit register for signal <old_sr_rise1_r<1>>.
    Found 1-bit register for signal <old_sr_fall1_r<1>>.
    Found 1-bit register for signal <old_sr_rise2_r<1>>.
    Found 1-bit register for signal <old_sr_fall2_r<1>>.
    Found 1-bit register for signal <old_sr_rise3_r<1>>.
    Found 1-bit register for signal <old_sr_fall3_r<1>>.
    Found 1-bit register for signal <prev_sr_rise0_r<2>>.
    Found 1-bit register for signal <prev_sr_fall0_r<2>>.
    Found 1-bit register for signal <prev_sr_rise1_r<2>>.
    Found 1-bit register for signal <prev_sr_fall1_r<2>>.
    Found 1-bit register for signal <prev_sr_rise2_r<2>>.
    Found 1-bit register for signal <prev_sr_fall2_r<2>>.
    Found 1-bit register for signal <prev_sr_rise3_r<2>>.
    Found 1-bit register for signal <prev_sr_fall3_r<2>>.
    Found 1-bit register for signal <old_sr_rise0_r<2>>.
    Found 1-bit register for signal <old_sr_fall0_r<2>>.
    Found 1-bit register for signal <old_sr_rise1_r<2>>.
    Found 1-bit register for signal <old_sr_fall1_r<2>>.
    Found 1-bit register for signal <old_sr_rise2_r<2>>.
    Found 1-bit register for signal <old_sr_fall2_r<2>>.
    Found 1-bit register for signal <old_sr_rise3_r<2>>.
    Found 1-bit register for signal <old_sr_fall3_r<2>>.
    Found 1-bit register for signal <prev_sr_rise0_r<3>>.
    Found 1-bit register for signal <prev_sr_fall0_r<3>>.
    Found 1-bit register for signal <prev_sr_rise1_r<3>>.
    Found 1-bit register for signal <prev_sr_fall1_r<3>>.
    Found 1-bit register for signal <prev_sr_rise2_r<3>>.
    Found 1-bit register for signal <prev_sr_fall2_r<3>>.
    Found 1-bit register for signal <prev_sr_rise3_r<3>>.
    Found 1-bit register for signal <prev_sr_fall3_r<3>>.
    Found 1-bit register for signal <old_sr_rise0_r<3>>.
    Found 1-bit register for signal <old_sr_fall0_r<3>>.
    Found 1-bit register for signal <old_sr_rise1_r<3>>.
    Found 1-bit register for signal <old_sr_fall1_r<3>>.
    Found 1-bit register for signal <old_sr_rise2_r<3>>.
    Found 1-bit register for signal <old_sr_fall2_r<3>>.
    Found 1-bit register for signal <old_sr_rise3_r<3>>.
    Found 1-bit register for signal <old_sr_fall3_r<3>>.
    Found 1-bit register for signal <prev_sr_rise0_r<4>>.
    Found 1-bit register for signal <prev_sr_fall0_r<4>>.
    Found 1-bit register for signal <prev_sr_rise1_r<4>>.
    Found 1-bit register for signal <prev_sr_fall1_r<4>>.
    Found 1-bit register for signal <prev_sr_rise2_r<4>>.
    Found 1-bit register for signal <prev_sr_fall2_r<4>>.
    Found 1-bit register for signal <prev_sr_rise3_r<4>>.
    Found 1-bit register for signal <prev_sr_fall3_r<4>>.
    Found 1-bit register for signal <old_sr_rise0_r<4>>.
    Found 1-bit register for signal <old_sr_fall0_r<4>>.
    Found 1-bit register for signal <old_sr_rise1_r<4>>.
    Found 1-bit register for signal <old_sr_fall1_r<4>>.
    Found 1-bit register for signal <old_sr_rise2_r<4>>.
    Found 1-bit register for signal <old_sr_fall2_r<4>>.
    Found 1-bit register for signal <old_sr_rise3_r<4>>.
    Found 1-bit register for signal <old_sr_fall3_r<4>>.
    Found 1-bit register for signal <prev_sr_rise0_r<5>>.
    Found 1-bit register for signal <prev_sr_fall0_r<5>>.
    Found 1-bit register for signal <prev_sr_rise1_r<5>>.
    Found 1-bit register for signal <prev_sr_fall1_r<5>>.
    Found 1-bit register for signal <prev_sr_rise2_r<5>>.
    Found 1-bit register for signal <prev_sr_fall2_r<5>>.
    Found 1-bit register for signal <prev_sr_rise3_r<5>>.
    Found 1-bit register for signal <prev_sr_fall3_r<5>>.
    Found 1-bit register for signal <old_sr_rise0_r<5>>.
    Found 1-bit register for signal <old_sr_fall0_r<5>>.
    Found 1-bit register for signal <old_sr_rise1_r<5>>.
    Found 1-bit register for signal <old_sr_fall1_r<5>>.
    Found 1-bit register for signal <old_sr_rise2_r<5>>.
    Found 1-bit register for signal <old_sr_fall2_r<5>>.
    Found 1-bit register for signal <old_sr_rise3_r<5>>.
    Found 1-bit register for signal <old_sr_fall3_r<5>>.
    Found 1-bit register for signal <prev_sr_rise0_r<6>>.
    Found 1-bit register for signal <prev_sr_fall0_r<6>>.
    Found 1-bit register for signal <prev_sr_rise1_r<6>>.
    Found 1-bit register for signal <prev_sr_fall1_r<6>>.
    Found 1-bit register for signal <prev_sr_rise2_r<6>>.
    Found 1-bit register for signal <prev_sr_fall2_r<6>>.
    Found 1-bit register for signal <prev_sr_rise3_r<6>>.
    Found 1-bit register for signal <prev_sr_fall3_r<6>>.
    Found 1-bit register for signal <old_sr_rise0_r<6>>.
    Found 1-bit register for signal <old_sr_fall0_r<6>>.
    Found 1-bit register for signal <old_sr_rise1_r<6>>.
    Found 1-bit register for signal <old_sr_fall1_r<6>>.
    Found 1-bit register for signal <old_sr_rise2_r<6>>.
    Found 1-bit register for signal <old_sr_fall2_r<6>>.
    Found 1-bit register for signal <old_sr_rise3_r<6>>.
    Found 1-bit register for signal <old_sr_fall3_r<6>>.
    Found 1-bit register for signal <prev_sr_rise0_r<7>>.
    Found 1-bit register for signal <prev_sr_fall0_r<7>>.
    Found 1-bit register for signal <prev_sr_rise1_r<7>>.
    Found 1-bit register for signal <prev_sr_fall1_r<7>>.
    Found 1-bit register for signal <prev_sr_rise2_r<7>>.
    Found 1-bit register for signal <prev_sr_fall2_r<7>>.
    Found 1-bit register for signal <prev_sr_rise3_r<7>>.
    Found 1-bit register for signal <prev_sr_fall3_r<7>>.
    Found 1-bit register for signal <old_sr_rise0_r<7>>.
    Found 1-bit register for signal <old_sr_fall0_r<7>>.
    Found 1-bit register for signal <old_sr_rise1_r<7>>.
    Found 1-bit register for signal <old_sr_fall1_r<7>>.
    Found 1-bit register for signal <old_sr_rise2_r<7>>.
    Found 1-bit register for signal <old_sr_fall2_r<7>>.
    Found 1-bit register for signal <old_sr_rise3_r<7>>.
    Found 1-bit register for signal <old_sr_fall3_r<7>>.
    Found 1-bit register for signal <sr_valid_r1>.
    Found 1-bit register for signal <sr_valid_r2>.
    Found 1-bit register for signal <mpr_valid_r1>.
    Found 1-bit register for signal <mpr_valid_r2>.
    Found 1-bit register for signal <old_sr_match_rise0_r<0>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<0>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<0>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<0>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<0>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<0>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<0>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<0>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<0>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<0>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<0>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<0>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<0>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<0>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<0>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<0>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<0>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<0>>.
    Found 1-bit register for signal <old_sr_diff_r<0>>.
    Found 1-bit register for signal <prev_sr_diff_r<0>>.
    Found 1-bit register for signal <old_sr_match_rise0_r<1>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<1>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<1>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<1>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<1>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<1>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<1>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<1>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<1>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<1>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<1>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<1>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<1>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<1>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<1>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<1>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<1>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<1>>.
    Found 1-bit register for signal <old_sr_diff_r<1>>.
    Found 1-bit register for signal <prev_sr_diff_r<1>>.
    Found 1-bit register for signal <old_sr_match_rise0_r<2>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<2>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<2>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<2>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<2>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<2>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<2>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<2>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<2>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<2>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<2>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<2>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<2>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<2>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<2>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<2>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<2>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<2>>.
    Found 1-bit register for signal <old_sr_diff_r<2>>.
    Found 1-bit register for signal <prev_sr_diff_r<2>>.
    Found 1-bit register for signal <old_sr_match_rise0_r<3>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<3>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<3>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<3>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<3>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<3>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<3>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<3>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<3>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<3>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<3>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<3>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<3>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<3>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<3>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<3>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<3>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<3>>.
    Found 1-bit register for signal <old_sr_diff_r<3>>.
    Found 1-bit register for signal <prev_sr_diff_r<3>>.
    Found 1-bit register for signal <old_sr_match_rise0_r<4>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<4>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<4>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<4>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<4>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<4>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<4>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<4>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<4>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<4>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<4>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<4>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<4>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<4>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<4>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<4>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<4>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<4>>.
    Found 1-bit register for signal <old_sr_diff_r<4>>.
    Found 1-bit register for signal <prev_sr_diff_r<4>>.
    Found 1-bit register for signal <old_sr_match_rise0_r<5>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<5>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<5>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<5>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<5>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<5>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<5>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<5>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<5>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<5>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<5>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<5>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<5>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<5>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<5>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<5>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<5>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<5>>.
    Found 1-bit register for signal <old_sr_diff_r<5>>.
    Found 1-bit register for signal <prev_sr_diff_r<5>>.
    Found 1-bit register for signal <old_sr_match_rise0_r<6>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<6>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<6>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<6>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<6>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<6>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<6>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<6>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<6>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<6>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<6>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<6>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<6>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<6>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<6>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<6>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<6>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<6>>.
    Found 1-bit register for signal <old_sr_diff_r<6>>.
    Found 1-bit register for signal <prev_sr_diff_r<6>>.
    Found 1-bit register for signal <old_sr_match_rise0_r<7>>.
    Found 1-bit register for signal <old_sr_match_fall0_r<7>>.
    Found 1-bit register for signal <old_sr_match_rise1_r<7>>.
    Found 1-bit register for signal <old_sr_match_fall1_r<7>>.
    Found 1-bit register for signal <old_sr_match_rise2_r<7>>.
    Found 1-bit register for signal <old_sr_match_fall2_r<7>>.
    Found 1-bit register for signal <old_sr_match_rise3_r<7>>.
    Found 1-bit register for signal <old_sr_match_fall3_r<7>>.
    Found 1-bit register for signal <prev_sr_match_rise0_r<7>>.
    Found 1-bit register for signal <prev_sr_match_fall0_r<7>>.
    Found 1-bit register for signal <prev_sr_match_rise1_r<7>>.
    Found 1-bit register for signal <prev_sr_match_fall1_r<7>>.
    Found 1-bit register for signal <prev_sr_match_rise2_r<7>>.
    Found 1-bit register for signal <prev_sr_match_fall2_r<7>>.
    Found 1-bit register for signal <prev_sr_match_rise3_r<7>>.
    Found 1-bit register for signal <prev_sr_match_fall3_r<7>>.
    Found 1-bit register for signal <old_sr_match_cyc2_r<7>>.
    Found 1-bit register for signal <prev_sr_match_cyc2_r<7>>.
    Found 1-bit register for signal <old_sr_diff_r<7>>.
    Found 1-bit register for signal <prev_sr_diff_r<7>>.
    Found 1-bit register for signal <samp_edge_cnt0_en_r>.
    Found 12-bit register for signal <samp_edge_cnt0_r>.
    Found 1-bit register for signal <samp_edge_cnt1_en_r>.
    Found 12-bit register for signal <samp_edge_cnt1_r>.
    Found 1-bit register for signal <samp_cnt_done_r>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<0><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<0><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<0><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<0><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<0><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<0>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<0>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<0>>.
    Found 1-bit register for signal <pb_found_edge_last_r<0>>.
    Found 1-bit register for signal <pb_found_edge_r<0>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<1><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<1><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<1><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<1><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<1><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<1>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<1>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<1>>.
    Found 1-bit register for signal <pb_found_edge_last_r<1>>.
    Found 1-bit register for signal <pb_found_edge_r<1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<2><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<2><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<2><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<2><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<2><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<2>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<2>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<2>>.
    Found 1-bit register for signal <pb_found_edge_last_r<2>>.
    Found 1-bit register for signal <pb_found_edge_r<2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<3><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<3><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<3><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<3><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<3><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<3>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<3>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<3>>.
    Found 1-bit register for signal <pb_found_edge_last_r<3>>.
    Found 1-bit register for signal <pb_found_edge_r<3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<4><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<4><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<4><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<4><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<4><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<4>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<4>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<4>>.
    Found 1-bit register for signal <pb_found_edge_last_r<4>>.
    Found 1-bit register for signal <pb_found_edge_r<4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<5><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<5><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<5><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<5><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<5><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<5>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<5>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<5>>.
    Found 1-bit register for signal <pb_found_edge_last_r<5>>.
    Found 1-bit register for signal <pb_found_edge_r<5>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<6><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<6><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<6><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<6><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<6><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<6>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<6>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<6>>.
    Found 1-bit register for signal <pb_found_edge_last_r<6>>.
    Found 1-bit register for signal <pb_found_edge_r<6>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<7><4>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<7><3>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<7><2>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<7><1>>.
    Found 1-bit register for signal <pb_cnt_eye_size_r<7><0>>.
    Found 1-bit register for signal <pb_detect_edge_done_r<7>>.
    Found 1-bit register for signal <pb_found_stable_eye_r<7>>.
    Found 1-bit register for signal <pb_last_tap_jitter_r<7>>.
    Found 1-bit register for signal <pb_found_edge_last_r<7>>.
    Found 1-bit register for signal <pb_found_edge_r<7>>.
    Found 1-bit register for signal <detect_edge_done_r>.
    Found 1-bit register for signal <found_edge_r>.
    Found 1-bit register for signal <found_edge_all_r>.
    Found 1-bit register for signal <found_stable_eye_r>.
    Found 1-bit register for signal <found_stable_eye_last_r>.
    Found 5-bit register for signal <idelay_tap_cnt_slice_r>.
    Found 20-bit register for signal <n3794[19:0]>.
    Found 1-bit register for signal <idelay_tap_limit_r>.
    Found 6-bit register for signal <tap_cnt_cpt_r>.
    Found 1-bit register for signal <tap_limit_cpt_r>.
    Found 24-bit register for signal <n3807[23:0]>.
    Found 5-bit register for signal <idel_tap_cnt_dq_pb_r>.
    Found 1-bit register for signal <idel_tap_limit_dq_pb_r>.
    Found 6-bit register for signal <cal1_state_r1>.
    Found 3-bit register for signal <cal1_cnt_cpt_r>.
    Found 1-bit register for signal <cal1_dlyce_cpt_r>.
    Found 1-bit register for signal <cal1_dlyinc_cpt_r>.
    Found 1-bit register for signal <cal1_dq_idel_ce>.
    Found 1-bit register for signal <cal1_dq_idel_inc>.
    Found 1-bit register for signal <cal1_prech_req_r>.
    Found 6-bit register for signal <cal1_state_r>.
    Found 6-bit register for signal <cnt_idel_dec_cpt_r>.
    Found 1-bit register for signal <found_first_edge_r>.
    Found 1-bit register for signal <found_second_edge_r>.
    Found 6-bit register for signal <right_edge_taps_r>.
    Found 6-bit register for signal <first_edge_taps_r>.
    Found 1-bit register for signal <new_cnt_cpt_r>.
    Found 1-bit register for signal <rdlvl_stg1_done>.
    Found 1-bit register for signal <rdlvl_stg1_err>.
    Found 6-bit register for signal <second_edge_taps_r>.
    Found 1-bit register for signal <store_sr_req_pulsed_r>.
    Found 1-bit register for signal <store_sr_req_r>.
    Found 2-bit register for signal <rnk_cnt_r>.
    Found 1-bit register for signal <rdlvl_rank_done_r>.
    Found 5-bit register for signal <idel_dec_cnt>.
    Found 1-bit register for signal <rdlvl_last_byte_done>.
    Found 1-bit register for signal <idel_pat_detect_valid_r>.
    Found 1-bit register for signal <mpr_rank_done_r>.
    Found 1-bit register for signal <mpr_last_byte_done>.
    Found 1-bit register for signal <mpr_rdlvl_done_r>.
    Found 1-bit register for signal <mpr_dec_cpt_r>.
    Found 1-bit register for signal <cal1_dlyce_dq_r>.
    Found 24-bit register for signal <dbg_cpt_first_edge_taps>.
INFO:Xst:1799 - State 010001 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 011001 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 010010 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 010100 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 010011 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 010101 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 010110 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 010111 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 011000 is never reached in FSM <cal1_state_r>.
INFO:Xst:1799 - State 011010 is never reached in FSM <cal1_state_r>.
    Found finite state machine <FSM_6> for signal <cal1_state_r>.
    -----------------------------------------------------------------------
    | States             | 32                                             |
    | Transitions        | 65                                             |
    | Inputs             | 31                                             |
    | Outputs            | 25                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit subtractor for signal <cal1_cnt_cpt_r[2]_GND_109_o_sub_430_OUT> created at line 1150.
    Found 5-bit subtractor for signal <idelay_tap_cnt_slice_r[4]_GND_109_o_sub_1090_OUT> created at line 2561.
    Found 7-bit subtractor for signal <n4076> created at line 3113.
    Found 6-bit subtractor for signal <tap_cnt_cpt_r[5]_GND_109_o_sub_1249_OUT> created at line 3120.
    Found 6-bit subtractor for signal <n4079> created at line 3124.
    Found 8-bit adder for signal <n4320> created at line 641.
    Found 8-bit adder for signal <n3845> created at line 641.
    Found 6-bit adder for signal <n3875> created at line 710.
    Found 6-bit adder for signal <n3876> created at line 710.
    Found 6-bit adder for signal <n3877> created at line 710.
    Found 6-bit adder for signal <n3878> created at line 710.
    Found 6-bit adder for signal <n3879> created at line 710.
    Found 6-bit adder for signal <n3880> created at line 710.
    Found 6-bit adder for signal <n3881> created at line 710.
    Found 3-bit adder for signal <stable_idel_cnt[2]_GND_109_o_add_261_OUT> created at line 778.
    Found 2-bit adder for signal <regl_rank_cnt[1]_GND_109_o_add_352_OUT> created at line 1051.
    Found 3-bit adder for signal <regl_dqs_cnt[2]_GND_109_o_add_367_OUT> created at line 1067.
    Found 5-bit adder for signal <cal1_cnt_cpt_r[2]_GND_109_o_add_394_OUT> created at line 1147.
    Found 5-bit adder for signal <cal1_wait_cnt_r[4]_GND_109_o_add_477_OUT> created at line 1198.
    Found 4-bit adder for signal <cnt_shift_r[3]_GND_109_o_add_850_OUT> created at line 1967.
    Found 12-bit adder for signal <samp_edge_cnt0_r[11]_GND_109_o_add_1011_OUT> created at line 2351.
    Found 12-bit adder for signal <samp_edge_cnt1_r[11]_GND_109_o_add_1019_OUT> created at line 2375.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[0][4]_GND_109_o_add_1035_OUT> created at line 2452.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[1][4]_GND_109_o_add_1038_OUT> created at line 2452.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[2][4]_GND_109_o_add_1041_OUT> created at line 2452.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[3][4]_GND_109_o_add_1044_OUT> created at line 2452.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[4][4]_GND_109_o_add_1047_OUT> created at line 2452.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[5][4]_GND_109_o_add_1050_OUT> created at line 2452.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[6][4]_GND_109_o_add_1053_OUT> created at line 2452.
    Found 5-bit adder for signal <pb_cnt_eye_size_r[7][4]_GND_109_o_add_1056_OUT> created at line 2452.
    Found 5-bit adder for signal <idelay_tap_cnt_slice_r[4]_GND_109_o_add_1074_OUT> created at line 2559.
    Found 6-bit adder for signal <tap_cnt_cpt_r[5]_GND_109_o_add_1123_OUT> created at line 2582.
    Found 5-bit adder for signal <GND_109_o_idel_tap_cnt_dq_pb_r[4]_mux_1160_OUT> created at line 2637.
    Found 31-bit adder for signal <n4077> created at line 3113.
    Found 2-bit adder for signal <rnk_cnt_r[1]_GND_109_o_add_1276_OUT> created at line 3219.
    Found 3-bit adder for signal <cal1_cnt_cpt_r[2]_GND_109_o_add_1283_OUT> created at line 3228.
    Found 4-bit subtractor for signal <GND_109_o_GND_109_o_sub_292_OUT<3:0>> created at line 911.
    Found 6-bit subtractor for signal <GND_109_o_GND_109_o_sub_298_OUT<5:0>> created at line 921.
    Found 4-bit subtractor for signal <GND_109_o_GND_109_o_sub_321_OUT<3:0>> created at line 995.
    Found 6-bit subtractor for signal <GND_109_o_GND_109_o_sub_1126_OUT<5:0>> created at line 2584.
    Found 6-bit subtractor for signal <GND_109_o_GND_109_o_sub_1199_OUT<5:0>> created at line 2867.
    Found 5-bit subtractor for signal <GND_109_o_GND_109_o_sub_1219_OUT<4:0>> created at line 2959.
    Found 4x3-bit multiplier for signal <rnk_cnt_r[1]_PWR_108_o_MuLt_58_OUT> created at line 642.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise0[31]_Mux_105_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall0[31]_Mux_106_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise1[31]_Mux_107_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall1[31]_Mux_108_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise2[31]_Mux_109_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall2[31]_Mux_110_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise3[31]_Mux_111_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall3[31]_Mux_112_o> created at line 724.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_115_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_117_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_119_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_121_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_123_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_125_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_127_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_129_o> created at line 724.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_132_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_134_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_136_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_138_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_140_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_142_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_144_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_146_o> created at line 724.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_149_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_151_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_153_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_155_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_157_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_159_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_161_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_163_o> created at line 724.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_166_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_168_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_170_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_172_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_174_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_176_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_178_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_180_o> created at line 724.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_183_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_185_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_187_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_189_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_191_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_193_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_195_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_197_o> created at line 724.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_200_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_202_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_204_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_206_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_208_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_210_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_212_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_214_o> created at line 724.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_217_o> created at line 710.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_219_o> created at line 712.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_221_o> created at line 714.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_223_o> created at line 716.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_225_o> created at line 718.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_227_o> created at line 720.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_229_o> created at line 722.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_231_o> created at line 724.
    Found 5-bit 4-to-1 multiplexer for signal <cal1_cnt_cpt_timing[1]_rnk_cnt_r[0]_wide_mux_249_OUT> created at line 766.
    Found 6-bit 4-to-1 multiplexer for signal <regl_dqs_cnt[1]_rnk_cnt_r[0]_wide_mux_340_OUT> created at line 1029.
    Found 5-bit 8-to-1 multiplexer for signal <n4343> created at line 1150.
    Found 1-bit comparator equal for signal <n0281> created at line 757
    Found 1-bit comparator equal for signal <n0284> created at line 758
    Found 1-bit comparator equal for signal <n0287> created at line 759
    Found 1-bit comparator equal for signal <n0290> created at line 760
    Found 1-bit comparator equal for signal <n0293> created at line 761
    Found 1-bit comparator equal for signal <n0296> created at line 762
    Found 1-bit comparator equal for signal <n0299> created at line 763
    Found 1-bit comparator equal for signal <n0302> created at line 764
    Found 3-bit comparator greater for signal <stable_idel_cnt[2]_GND_109_o_LessThan_261_o> created at line 777
    Found 5-bit comparator greater for signal <GND_109_o_cal1_cnt_cpt_timing[1]_LessThan_274_o> created at line 792
    Found 4-bit comparator greater for signal <GND_109_o_wait_cnt_r[3]_LessThan_291_o> created at line 910
    Found 6-bit comparator greater for signal <GND_109_o_pi_rdval_cnt[5]_LessThan_297_o> created at line 919
    Found 3-bit comparator lessequal for signal <n0442> created at line 1026
    Found 2-bit comparator lessequal for signal <n0534> created at line 1149
    Found 1-bit comparator equal for signal <sr_rise0_r[0][0]_old_sr_rise0_r[0][0]_equal_871_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[0][0]_old_sr_fall0_r[0][0]_equal_872_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[0][0]_old_sr_rise1_r[0][0]_equal_873_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[0][0]_old_sr_fall1_r[0][0]_equal_874_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[0][0]_old_sr_rise2_r[0][0]_equal_875_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[0][0]_old_sr_fall2_r[0][0]_equal_876_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[0][0]_old_sr_rise3_r[0][0]_equal_877_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[0][0]_old_sr_fall3_r[0][0]_equal_878_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[0][0]_prev_sr_rise0_r[0][0]_equal_879_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[0][0]_prev_sr_fall0_r[0][0]_equal_880_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[0][0]_prev_sr_rise1_r[0][0]_equal_881_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[0][0]_prev_sr_fall1_r[0][0]_equal_882_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[0][0]_prev_sr_rise2_r[0][0]_equal_883_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[0][0]_prev_sr_fall2_r[0][0]_equal_884_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[0][0]_prev_sr_rise3_r[0][0]_equal_885_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[0][0]_prev_sr_fall3_r[0][0]_equal_886_o> created at line 2189
    Found 1-bit comparator equal for signal <sr_rise0_r[1][0]_old_sr_rise0_r[1][0]_equal_888_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[1][0]_old_sr_fall0_r[1][0]_equal_889_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[1][0]_old_sr_rise1_r[1][0]_equal_890_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[1][0]_old_sr_fall1_r[1][0]_equal_891_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[1][0]_old_sr_rise2_r[1][0]_equal_892_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[1][0]_old_sr_fall2_r[1][0]_equal_893_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[1][0]_old_sr_rise3_r[1][0]_equal_894_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[1][0]_old_sr_fall3_r[1][0]_equal_895_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[1][0]_prev_sr_rise0_r[1][0]_equal_896_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[1][0]_prev_sr_fall0_r[1][0]_equal_897_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[1][0]_prev_sr_rise1_r[1][0]_equal_898_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[1][0]_prev_sr_fall1_r[1][0]_equal_899_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[1][0]_prev_sr_rise2_r[1][0]_equal_900_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[1][0]_prev_sr_fall2_r[1][0]_equal_901_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[1][0]_prev_sr_rise3_r[1][0]_equal_902_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[1][0]_prev_sr_fall3_r[1][0]_equal_903_o> created at line 2189
    Found 1-bit comparator equal for signal <sr_rise0_r[2][0]_old_sr_rise0_r[2][0]_equal_905_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[2][0]_old_sr_fall0_r[2][0]_equal_906_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[2][0]_old_sr_rise1_r[2][0]_equal_907_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[2][0]_old_sr_fall1_r[2][0]_equal_908_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[2][0]_old_sr_rise2_r[2][0]_equal_909_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[2][0]_old_sr_fall2_r[2][0]_equal_910_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[2][0]_old_sr_rise3_r[2][0]_equal_911_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[2][0]_old_sr_fall3_r[2][0]_equal_912_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[2][0]_prev_sr_rise0_r[2][0]_equal_913_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[2][0]_prev_sr_fall0_r[2][0]_equal_914_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[2][0]_prev_sr_rise1_r[2][0]_equal_915_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[2][0]_prev_sr_fall1_r[2][0]_equal_916_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[2][0]_prev_sr_rise2_r[2][0]_equal_917_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[2][0]_prev_sr_fall2_r[2][0]_equal_918_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[2][0]_prev_sr_rise3_r[2][0]_equal_919_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[2][0]_prev_sr_fall3_r[2][0]_equal_920_o> created at line 2189
    Found 1-bit comparator equal for signal <sr_rise0_r[3][0]_old_sr_rise0_r[3][0]_equal_922_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[3][0]_old_sr_fall0_r[3][0]_equal_923_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[3][0]_old_sr_rise1_r[3][0]_equal_924_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[3][0]_old_sr_fall1_r[3][0]_equal_925_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[3][0]_old_sr_rise2_r[3][0]_equal_926_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[3][0]_old_sr_fall2_r[3][0]_equal_927_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[3][0]_old_sr_rise3_r[3][0]_equal_928_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[3][0]_old_sr_fall3_r[3][0]_equal_929_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[3][0]_prev_sr_rise0_r[3][0]_equal_930_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[3][0]_prev_sr_fall0_r[3][0]_equal_931_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[3][0]_prev_sr_rise1_r[3][0]_equal_932_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[3][0]_prev_sr_fall1_r[3][0]_equal_933_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[3][0]_prev_sr_rise2_r[3][0]_equal_934_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[3][0]_prev_sr_fall2_r[3][0]_equal_935_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[3][0]_prev_sr_rise3_r[3][0]_equal_936_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[3][0]_prev_sr_fall3_r[3][0]_equal_937_o> created at line 2189
    Found 1-bit comparator equal for signal <sr_rise0_r[4][0]_old_sr_rise0_r[4][0]_equal_939_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[4][0]_old_sr_fall0_r[4][0]_equal_940_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[4][0]_old_sr_rise1_r[4][0]_equal_941_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[4][0]_old_sr_fall1_r[4][0]_equal_942_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[4][0]_old_sr_rise2_r[4][0]_equal_943_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[4][0]_old_sr_fall2_r[4][0]_equal_944_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[4][0]_old_sr_rise3_r[4][0]_equal_945_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[4][0]_old_sr_fall3_r[4][0]_equal_946_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[4][0]_prev_sr_rise0_r[4][0]_equal_947_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[4][0]_prev_sr_fall0_r[4][0]_equal_948_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[4][0]_prev_sr_rise1_r[4][0]_equal_949_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[4][0]_prev_sr_fall1_r[4][0]_equal_950_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[4][0]_prev_sr_rise2_r[4][0]_equal_951_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[4][0]_prev_sr_fall2_r[4][0]_equal_952_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[4][0]_prev_sr_rise3_r[4][0]_equal_953_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[4][0]_prev_sr_fall3_r[4][0]_equal_954_o> created at line 2189
    Found 1-bit comparator equal for signal <sr_rise0_r[5][0]_old_sr_rise0_r[5][0]_equal_956_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[5][0]_old_sr_fall0_r[5][0]_equal_957_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[5][0]_old_sr_rise1_r[5][0]_equal_958_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[5][0]_old_sr_fall1_r[5][0]_equal_959_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[5][0]_old_sr_rise2_r[5][0]_equal_960_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[5][0]_old_sr_fall2_r[5][0]_equal_961_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[5][0]_old_sr_rise3_r[5][0]_equal_962_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[5][0]_old_sr_fall3_r[5][0]_equal_963_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[5][0]_prev_sr_rise0_r[5][0]_equal_964_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[5][0]_prev_sr_fall0_r[5][0]_equal_965_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[5][0]_prev_sr_rise1_r[5][0]_equal_966_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[5][0]_prev_sr_fall1_r[5][0]_equal_967_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[5][0]_prev_sr_rise2_r[5][0]_equal_968_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[5][0]_prev_sr_fall2_r[5][0]_equal_969_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[5][0]_prev_sr_rise3_r[5][0]_equal_970_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[5][0]_prev_sr_fall3_r[5][0]_equal_971_o> created at line 2189
    Found 1-bit comparator equal for signal <sr_rise0_r[6][0]_old_sr_rise0_r[6][0]_equal_973_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[6][0]_old_sr_fall0_r[6][0]_equal_974_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[6][0]_old_sr_rise1_r[6][0]_equal_975_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[6][0]_old_sr_fall1_r[6][0]_equal_976_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[6][0]_old_sr_rise2_r[6][0]_equal_977_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[6][0]_old_sr_fall2_r[6][0]_equal_978_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[6][0]_old_sr_rise3_r[6][0]_equal_979_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[6][0]_old_sr_fall3_r[6][0]_equal_980_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[6][0]_prev_sr_rise0_r[6][0]_equal_981_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[6][0]_prev_sr_fall0_r[6][0]_equal_982_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[6][0]_prev_sr_rise1_r[6][0]_equal_983_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[6][0]_prev_sr_fall1_r[6][0]_equal_984_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[6][0]_prev_sr_rise2_r[6][0]_equal_985_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[6][0]_prev_sr_fall2_r[6][0]_equal_986_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[6][0]_prev_sr_rise3_r[6][0]_equal_987_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[6][0]_prev_sr_fall3_r[6][0]_equal_988_o> created at line 2189
    Found 1-bit comparator equal for signal <sr_rise0_r[7][0]_old_sr_rise0_r[7][0]_equal_990_o> created at line 2084
    Found 1-bit comparator equal for signal <sr_fall0_r[7][0]_old_sr_fall0_r[7][0]_equal_991_o> created at line 2091
    Found 1-bit comparator equal for signal <sr_rise1_r[7][0]_old_sr_rise1_r[7][0]_equal_992_o> created at line 2098
    Found 1-bit comparator equal for signal <sr_fall1_r[7][0]_old_sr_fall1_r[7][0]_equal_993_o> created at line 2105
    Found 1-bit comparator equal for signal <sr_rise2_r[7][0]_old_sr_rise2_r[7][0]_equal_994_o> created at line 2112
    Found 1-bit comparator equal for signal <sr_fall2_r[7][0]_old_sr_fall2_r[7][0]_equal_995_o> created at line 2119
    Found 1-bit comparator equal for signal <sr_rise3_r[7][0]_old_sr_rise3_r[7][0]_equal_996_o> created at line 2126
    Found 1-bit comparator equal for signal <sr_fall3_r[7][0]_old_sr_fall3_r[7][0]_equal_997_o> created at line 2133
    Found 1-bit comparator equal for signal <sr_rise0_r[7][0]_prev_sr_rise0_r[7][0]_equal_998_o> created at line 2140
    Found 1-bit comparator equal for signal <sr_fall0_r[7][0]_prev_sr_fall0_r[7][0]_equal_999_o> created at line 2147
    Found 1-bit comparator equal for signal <sr_rise1_r[7][0]_prev_sr_rise1_r[7][0]_equal_1000_o> created at line 2154
    Found 1-bit comparator equal for signal <sr_fall1_r[7][0]_prev_sr_fall1_r[7][0]_equal_1001_o> created at line 2161
    Found 1-bit comparator equal for signal <sr_rise2_r[7][0]_prev_sr_rise2_r[7][0]_equal_1002_o> created at line 2168
    Found 1-bit comparator equal for signal <sr_fall2_r[7][0]_prev_sr_fall2_r[7][0]_equal_1003_o> created at line 2175
    Found 1-bit comparator equal for signal <sr_rise3_r[7][0]_prev_sr_rise3_r[7][0]_equal_1004_o> created at line 2182
    Found 1-bit comparator equal for signal <sr_fall3_r[7][0]_prev_sr_fall3_r[7][0]_equal_1005_o> created at line 2189
    Found 5-bit comparator lessequal for signal <n3407> created at line 2561
    Found 3-bit comparator lessequal for signal <n3427> created at line 2563
    Found 3-bit comparator lessequal for signal <n3467> created at line 2620
    Found 5-bit comparator greater for signal <GND_109_o_idel_dec_cnt[4]_LessThan_1221_o> created at line 2968
    Found 3-bit comparator greater for signal <n3612> created at line 3179
    Summary:
	inferred   1 Multiplier(s).
	inferred  42 Adder/Subtractor(s).
	inferred 1271 D-type flip-flop(s).
	inferred 147 Comparator(s).
	inferred 393 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_rdlvl> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_prbs_rdlvl>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_prbs_rdlvl.v".
        TCQ = 100
        nCK_PER_CLK = 4
        DQ_WIDTH = 32
        DQS_CNT_WIDTH = 2
        DQS_WIDTH = 4
        DRAM_WIDTH = 8
        RANKS = 1
        SIM_CAL_OPTION = "NONE"
        PRBS_WIDTH = 8
    Register <samples_cnt_en_r> equivalent to <rd_valid_r1> has been removed
    Found 1-bit register for signal <mux_rd_rise0_r1<0>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<0>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<0>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<0>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<0>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<0>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<0>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<0>>.
    Found 1-bit register for signal <mux_rd_rise0_r1<1>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<1>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<1>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<1>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<1>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<1>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<1>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<1>>.
    Found 1-bit register for signal <mux_rd_rise0_r1<2>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<2>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<2>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<2>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<2>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<2>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<2>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<2>>.
    Found 1-bit register for signal <mux_rd_rise0_r1<3>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<3>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<3>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<3>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<3>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<3>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<3>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<3>>.
    Found 1-bit register for signal <mux_rd_rise0_r1<4>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<4>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<4>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<4>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<4>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<4>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<4>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<4>>.
    Found 1-bit register for signal <mux_rd_rise0_r1<5>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<5>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<5>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<5>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<5>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<5>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<5>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<5>>.
    Found 1-bit register for signal <mux_rd_rise0_r1<6>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<6>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<6>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<6>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<6>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<6>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<6>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<6>>.
    Found 1-bit register for signal <mux_rd_rise0_r1<7>>.
    Found 1-bit register for signal <mux_rd_fall0_r1<7>>.
    Found 1-bit register for signal <mux_rd_rise1_r1<7>>.
    Found 1-bit register for signal <mux_rd_fall1_r1<7>>.
    Found 1-bit register for signal <mux_rd_rise2_r1<7>>.
    Found 1-bit register for signal <mux_rd_fall2_r1<7>>.
    Found 1-bit register for signal <mux_rd_rise3_r1<7>>.
    Found 1-bit register for signal <mux_rd_fall3_r1<7>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<0>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<0>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<0>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<0>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<0>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<0>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<0>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<0>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<1>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<1>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<1>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<1>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<1>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<1>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<1>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<1>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<2>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<2>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<2>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<2>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<2>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<2>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<2>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<2>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<3>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<3>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<3>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<3>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<3>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<3>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<3>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<3>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<4>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<4>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<4>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<4>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<4>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<4>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<4>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<4>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<5>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<5>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<5>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<5>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<5>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<5>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<5>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<5>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<6>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<6>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<6>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<6>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<6>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<6>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<6>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<6>>.
    Found 1-bit register for signal <mux_rd_rise0_r2<7>>.
    Found 1-bit register for signal <mux_rd_fall0_r2<7>>.
    Found 1-bit register for signal <mux_rd_rise1_r2<7>>.
    Found 1-bit register for signal <mux_rd_fall1_r2<7>>.
    Found 1-bit register for signal <mux_rd_rise2_r2<7>>.
    Found 1-bit register for signal <mux_rd_fall2_r2<7>>.
    Found 1-bit register for signal <mux_rd_rise3_r2<7>>.
    Found 1-bit register for signal <mux_rd_fall3_r2<7>>.
    Found 1-bit register for signal <mux_rd_valid_r>.
    Found 1-bit register for signal <rd_valid_r1>.
    Found 12-bit register for signal <samples_cnt_r>.
    Found 1-bit register for signal <samples_cnt1_en_r>.
    Found 12-bit register for signal <samples_cnt1_r>.
    Found 1-bit register for signal <samples_cnt2_en_r>.
    Found 12-bit register for signal <samples_cnt2_r>.
    Found 1-bit register for signal <num_samples_done_r>.
    Found 1-bit register for signal <compare_err>.
    Found 1-bit register for signal <compare_err_r0>.
    Found 1-bit register for signal <compare_err_f0>.
    Found 1-bit register for signal <compare_err_r1>.
    Found 1-bit register for signal <compare_err_f1>.
    Found 1-bit register for signal <compare_err_r2>.
    Found 1-bit register for signal <compare_err_f2>.
    Found 1-bit register for signal <compare_err_r3>.
    Found 1-bit register for signal <compare_err_f3>.
    Found 1-bit register for signal <pi_en_stg2_f_timing>.
    Found 1-bit register for signal <pi_stg2_f_incdec_timing>.
    Found 1-bit register for signal <pi_en_stg2_f>.
    Found 1-bit register for signal <pi_stg2_f_incdec>.
    Found 1-bit register for signal <prbs_rdlvl_prech_req>.
    Found 6-bit register for signal <prbs_dqs_tap_cnt_r>.
    Found 6-bit register for signal <rdlvl_cpt_tap_cnt>.
    Found 1-bit register for signal <prbs_dqs_tap_limit_r>.
    Found 1-bit register for signal <prbs_rdlvl_start_r>.
    Found 1-bit register for signal <wait_state_cnt_en_r>.
    Found 4-bit register for signal <wait_state_cnt_r>.
    Found 1-bit register for signal <cnt_wait_state>.
    Found 3-bit register for signal <prbs_dqs_cnt_r>.
    Found 1-bit register for signal <prbs_tap_en_r>.
    Found 1-bit register for signal <prbs_tap_inc_r>.
    Found 1-bit register for signal <prbs_prech_req_r>.
    Found 6-bit register for signal <prbs_state_r>.
    Found 1-bit register for signal <prbs_found_1st_edge_r>.
    Found 1-bit register for signal <prbs_found_2nd_edge_r>.
    Found 6-bit register for signal <prbs_1st_edge_taps_r>.
    Found 6-bit register for signal <prbs_inc_tap_cnt>.
    Found 6-bit register for signal <prbs_dec_tap_cnt>.
    Found 1-bit register for signal <new_cnt_dqs_r>.
    Found 1-bit register for signal <prbs_rdlvl_done>.
    Found 6-bit register for signal <prbs_2nd_edge_taps_r>.
    Found 1-bit register for signal <prbs_last_byte_done>.
    Found 2-bit register for signal <rnk_cnt_r>.
    Found 3-bit register for signal <rd_mux_sel_r>.
    Found finite state machine <FSM_7> for signal <prbs_state_r>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 38                                             |
    | Inputs             | 14                                             |
    | Outputs            | 16                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit subtractor for signal <rdlvl_cpt_tap_cnt[5]_prbs_dqs_tap_cnt_r[5]_sub_271_OUT> created at line 720.
    Found 7-bit subtractor for signal <n0649> created at line 769.
    Found 6-bit subtractor for signal <n0651> created at line 774.
    Found 6-bit adder for signal <n0595> created at line 282.
    Found 6-bit adder for signal <n0596> created at line 282.
    Found 6-bit adder for signal <n0597> created at line 282.
    Found 6-bit adder for signal <n0598> created at line 282.
    Found 6-bit adder for signal <n0599> created at line 282.
    Found 6-bit adder for signal <n0600> created at line 282.
    Found 6-bit adder for signal <n0601> created at line 282.
    Found 12-bit adder for signal <samples_cnt_r[11]_GND_111_o_add_164_OUT> created at line 360.
    Found 12-bit adder for signal <samples_cnt1_r[11]_GND_111_o_add_173_OUT> created at line 380.
    Found 12-bit adder for signal <samples_cnt2_r[11]_GND_111_o_add_180_OUT> created at line 399.
    Found 6-bit adder for signal <prbs_dqs_tap_cnt_r[5]_GND_111_o_add_201_OUT> created at line 534.
    Found 4-bit adder for signal <wait_state_cnt_r[3]_GND_111_o_add_259_OUT> created at line 597.
    Found 31-bit adder for signal <n0650> created at line 769.
    Found 2-bit adder for signal <rnk_cnt_r[1]_GND_111_o_add_310_OUT> created at line 838.
    Found 3-bit adder for signal <prbs_dqs_cnt_r[2]_GND_111_o_add_314_OUT> created at line 846.
    Found 6-bit subtractor for signal <GND_111_o_GND_111_o_sub_204_OUT<5:0>> created at line 536.
    Found 6-bit subtractor for signal <GND_111_o_GND_111_o_sub_290_OUT<5:0>> created at line 738.
    Found 6-bit subtractor for signal <GND_111_o_GND_111_o_sub_301_OUT<5:0>> created at line 795.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise0[31]_Mux_21_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall0[31]_Mux_22_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise1[31]_Mux_23_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall1[31]_Mux_24_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise2[31]_Mux_25_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall2[31]_Mux_26_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_rise3[31]_Mux_27_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[1]_rd_data_fall3[31]_Mux_28_o> created at line 296.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_31_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_33_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_35_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_37_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_39_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_41_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_43_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_45_o> created at line 296.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_48_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_50_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_52_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_54_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_56_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_58_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_60_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_62_o> created at line 296.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_65_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_67_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_69_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_71_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_73_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_75_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_77_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_79_o> created at line 296.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_82_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_84_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_86_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_88_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_90_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_92_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_94_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_96_o> created at line 296.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_99_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_101_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_103_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_105_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_107_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_109_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_111_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_113_o> created at line 296.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_116_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_118_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_120_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_122_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_124_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_126_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_128_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_130_o> created at line 296.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise0[31]_Mux_133_o> created at line 282.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall0[31]_Mux_135_o> created at line 284.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise1[31]_Mux_137_o> created at line 286.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall1[31]_Mux_139_o> created at line 288.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise2[31]_Mux_141_o> created at line 290.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall2[31]_Mux_143_o> created at line 292.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_rise3[31]_Mux_145_o> created at line 294.
    Found 1-bit 32-to-1 multiplexer for signal <rd_mux_sel_r[2]_rd_data_fall3[31]_Mux_147_o> created at line 296.
    Found 12-bit comparator greater for signal <samples_cnt_r[11]_PWR_110_o_LessThan_164_o> created at line 358
    Found 12-bit comparator greater for signal <samples_cnt1_r[11]_PWR_110_o_LessThan_173_o> created at line 379
    Found 8-bit comparator not equal for signal <n0329> created at line 435
    Found 8-bit comparator not equal for signal <n0331> created at line 436
    Found 8-bit comparator not equal for signal <n0333> created at line 437
    Found 8-bit comparator not equal for signal <n0335> created at line 438
    Found 8-bit comparator not equal for signal <n0337> created at line 439
    Found 8-bit comparator not equal for signal <n0339> created at line 440
    Found 8-bit comparator not equal for signal <n0341> created at line 441
    Found 8-bit comparator not equal for signal <n0343> created at line 442
    Found 4-bit comparator greater for signal <wait_state_cnt_r[3]_PWR_110_o_LessThan_259_o> created at line 596
    Found 3-bit comparator greater for signal <n0475> created at line 824
    Summary:
	inferred  20 Adder/Subtractor(s).
	inferred 243 D-type flip-flop(s).
	inferred  12 Comparator(s).
	inferred  86 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_prbs_rdlvl> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_phy_tempmon>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_tempmon.v".
        TCQ = 100
        BAND1_TEMP_MIN = 0
        BAND2_TEMP_MIN = 12
        BAND3_TEMP_MIN = 46
        BAND4_TEMP_MIN = 82
        TEMP_HYST = 5
    Found 12-bit register for signal <previous_temp>.
    Found 1-bit register for signal <device_temp_lt_previous_temp>.
    Found 1-bit register for signal <device_temp_gt_previous_temp>.
    Found 1-bit register for signal <device_temp_lt_band1>.
    Found 1-bit register for signal <device_temp_lt_band2>.
    Found 1-bit register for signal <device_temp_lt_band3>.
    Found 1-bit register for signal <device_temp_lt_band4>.
    Found 1-bit register for signal <device_temp_lt_band0_dec>.
    Found 1-bit register for signal <device_temp_lt_band1_dec>.
    Found 1-bit register for signal <device_temp_lt_band2_dec>.
    Found 1-bit register for signal <device_temp_lt_band3_dec>.
    Found 1-bit register for signal <device_temp_gt_band1_inc>.
    Found 1-bit register for signal <device_temp_gt_band2_inc>.
    Found 1-bit register for signal <device_temp_gt_band3_inc>.
    Found 1-bit register for signal <device_temp_gt_band4_inc>.
    Found 1-bit register for signal <target_band_gt_1>.
    Found 1-bit register for signal <target_band_gt_2>.
    Found 1-bit register for signal <target_band_gt_3>.
    Found 1-bit register for signal <target_band_lt_1>.
    Found 1-bit register for signal <target_band_lt_2>.
    Found 1-bit register for signal <target_band_lt_3>.
    Found 3-bit register for signal <target_band>.
    Found 1-bit register for signal <current_band_lt_target_band>.
    Found 1-bit register for signal <current_band_gt_target_band>.
    Found 3-bit register for signal <current_band>.
    Found 1-bit register for signal <pi_f_inc>.
    Found 1-bit register for signal <pi_f_dec>.
    Found 1-bit register for signal <sel_pi_incdec>.
    Found 3-bit register for signal <tempmon_state>.
    Found finite state machine <FSM_8> for signal <tempmon_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 7                                              |
    | Inputs             | 2                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <current_band[2]_GND_112_o_add_66_OUT> created at line 326.
    Found 3-bit subtractor for signal <GND_112_o_GND_112_o_sub_68_OUT<2:0>> created at line 328.
    Found 12-bit comparator greater for signal <device_temp[11]_previous_temp[11]_LessThan_19_o> created at line 219
    Found 12-bit comparator greater for signal <previous_temp[11]_device_temp[11]_LessThan_20_o> created at line 220
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_21_o> created at line 222
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_22_o> created at line 223
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_23_o> created at line 224
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_24_o> created at line 225
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_25_o> created at line 227
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_26_o> created at line 228
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_27_o> created at line 229
    Found 12-bit comparator greater for signal <device_temp[11]_PWR_111_o_LessThan_28_o> created at line 230
    Found 12-bit comparator greater for signal <PWR_111_o_device_temp[11]_LessThan_29_o> created at line 232
    Found 12-bit comparator greater for signal <PWR_111_o_device_temp[11]_LessThan_30_o> created at line 233
    Found 12-bit comparator greater for signal <PWR_111_o_device_temp[11]_LessThan_31_o> created at line 234
    Found 12-bit comparator greater for signal <PWR_111_o_device_temp[11]_LessThan_32_o> created at line 235
    Found 3-bit comparator greater for signal <GND_112_o_target_band[2]_LessThan_33_o> created at line 237
    Found 3-bit comparator greater for signal <GND_112_o_target_band[2]_LessThan_34_o> created at line 238
    Found 3-bit comparator greater for signal <GND_112_o_target_band[2]_LessThan_35_o> created at line 239
    Found 3-bit comparator greater for signal <target_band[2]_GND_112_o_LessThan_36_o> created at line 241
    Found 3-bit comparator greater for signal <target_band[2]_GND_112_o_LessThan_37_o> created at line 242
    Found 3-bit comparator greater for signal <target_band[2]_GND_112_o_LessThan_38_o> created at line 243
    Found 3-bit comparator greater for signal <current_band[2]_target_band[2]_LessThan_59_o> created at line 305
    Found 3-bit comparator greater for signal <target_band[2]_current_band[2]_LessThan_60_o> created at line 306
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  43 D-type flip-flop(s).
	inferred  22 Comparator(s).
	inferred  10 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_ddr_phy_tempmon> synthesized.

Synthesizing Unit <mig_7series_v1_8_ui_top>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_top.v".
        TCQ = 100
        APP_DATA_WIDTH = 256
        APP_MASK_WIDTH = 32
        BANK_WIDTH = 3
        COL_WIDTH = 10
        CWL = 7
        DATA_BUF_ADDR_WIDTH = 5
        ECC = "OFF"
        ECC_TEST = "OFF"
        ORDERING = "NORM"
        nCK_PER_CLK = 4
        RANKS = 1
        REG_CTRL = "ON"
        RANK_WIDTH = 1
        ROW_WIDTH = 15
        MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
WARNING:Xst:647 - Input <wr_data_addr<4:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ecc_multiple<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <accept> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ui_top> synthesized.

Synthesizing Unit <mig_7series_v1_8_ui_cmd>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_cmd.v".
        TCQ = 100
        ADDR_WIDTH = 29
        BANK_WIDTH = 3
        COL_WIDTH = 10
        DATA_BUF_ADDR_WIDTH = 5
        RANK_WIDTH = 1
        ROW_WIDTH = 15
        RANKS = 1
        MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
    Set property "syn_maxfan = 10" for signal <app_rdy_r>.
    Set property "KEEP = TRUE" for signal <app_rdy_r>.
    Set property "MAX_FANOUT = 10" for signal <app_rdy_r>.
    Found 29-bit register for signal <app_addr_r1>.
    Found 29-bit register for signal <app_addr_r2>.
    Found 3-bit register for signal <app_cmd_r1>.
    Found 3-bit register for signal <app_cmd_r2>.
    Found 1-bit register for signal <app_sz_r1>.
    Found 1-bit register for signal <app_sz_r2>.
    Found 1-bit register for signal <app_hi_pri_r1>.
    Found 1-bit register for signal <app_hi_pri_r2>.
    Found 1-bit register for signal <app_en_r1>.
    Found 1-bit register for signal <app_en_r2>.
    Found 1-bit register for signal <app_rdy_r>.
    Summary:
	inferred  71 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <mig_7series_v1_8_ui_cmd> synthesized.

Synthesizing Unit <mig_7series_v1_8_ui_wr_data>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_wr_data.v".
        TCQ = 100
        APP_DATA_WIDTH = 256
        APP_MASK_WIDTH = 32
        ECC = "OFF"
        nCK_PER_CLK = 4
        ECC_TEST = "OFF"
        CWL = 8
    Set property "equivalent_register_removal = no" for signal <app_wdf_rdy_r_copy1>.
    Set property "equivalent_register_removal = no" for signal <app_wdf_rdy_r_copy2>.
    Set property "equivalent_register_removal = no" for signal <app_wdf_rdy_r_copy3>.
    Set property "equivalent_register_removal = no" for signal <app_wdf_rdy_r_copy4>.
WARNING:Xst:647 - Input <app_raw_not_ecc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <app_wdf_mask_r1>.
    Found 1-bit register for signal <app_wdf_wren_r1>.
    Found 1-bit register for signal <app_wdf_end_r1>.
    Found 4-bit register for signal <rd_data_indx_r>.
    Found 1-bit register for signal <rd_data_upd_indx_r>.
    Found 4-bit register for signal <data_buf_addr_cnt_r>.
    Found 1-bit register for signal <app_wdf_rdy_r_copy1>.
    Found 1-bit register for signal <app_wdf_rdy_r_copy2>.
    Found 1-bit register for signal <app_wdf_rdy_r_copy3>.
    Found 4-bit register for signal <wr_data_indx_r>.
    Found 4-bit register for signal <write_data_control.wb_wr_data_addr_r>.
    Found 1-bit register for signal <write_data_control.wb_wr_data_addr0_r>.
    Found 16-bit register for signal <occupied_counter.occ_cnt>.
    Found 1-bit register for signal <app_wdf_rdy_r>.
    Found 5-bit register for signal <wr_req_counter.wr_req_cnt_r>.
    Found 288-bit register for signal <wr_buf_out_data>.
    Found 256-bit register for signal <app_wdf_data_r1>.
    Found 5-bit subtractor for signal <wr_req_counter.wr_req_cnt_r[4]_GND_115_o_sub_39_OUT> created at line 381.
    Found 4-bit adder for signal <rd_data_indx_r[3]_GND_115_o_add_6_OUT> created at line 235.
    Found 4-bit adder for signal <data_buf_addr_cnt_r[3]_GND_115_o_add_12_OUT> created at line 255.
    Found 4-bit adder for signal <wr_data_indx_r[3]_GND_115_o_add_18_OUT> created at line 287.
    Found 5-bit adder for signal <wr_req_counter.wr_req_cnt_r[4]_GND_115_o_add_39_OUT> created at line 382.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred 621 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <mig_7series_v1_8_ui_wr_data> synthesized.

Synthesizing Unit <mig_7series_v1_8_ui_rd_data>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/ui/mig_7series_v1_8_ui_rd_data.v".
        TCQ = 100
        APP_DATA_WIDTH = 256
        DATA_BUF_ADDR_WIDTH = 5
        ECC = "OFF"
        nCK_PER_CLK = 4
        ORDERING = "NORM"
    Set property "KEEP = TRUE" for signal <not_strict_mode.rd_buf.rd_buf_indx_copy_r>.
    Set property "KEEP = TRUE" for signal <ram_init_done_r_lcl>.
    Set property "MAX_FANOUT = 10" for signal <ram_init_done_r_lcl>.
    Set property "KEEP = TRUE" for signal <app_rd_data_valid>.
    Set property "MAX_FANOUT = 10" for signal <app_rd_data_valid>.
    Set property "KEEP = TRUE" for signal <not_strict_mode.rd_buf_we>.
    Set property "MAX_FANOUT = 10" for signal <not_strict_mode.rd_buf_we>.
    Set property "KEEP = TRUE" for signal <not_strict_mode.bypass>.
    Set property "MAX_FANOUT = 10" for signal <not_strict_mode.bypass>.
    Set property "syn_maxfan = 10" for signal <not_strict_mode.bypass>.
    Set property "equivalent_register_removal = no" for signal <not_strict_mode.app_rd_data_valid_copy>.
WARNING:Xst:647 - Input <ecc_multiple> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'app_ecc_multiple_err_r', unconnected in block 'mig_7series_v1_8_ui_rd_data', is tied to its initial value (00000000).
    Found 6-bit register for signal <rd_buf_indx_r>.
    Found 5-bit register for signal <not_strict_mode.status_ram.status_ram_wr_addr_r>.
    Found 1-bit register for signal <not_strict_mode.status_ram.wr_status_r1>.
    Found 2-bit register for signal <not_strict_mode.status_ram.status_ram_wr_data_r>.
    Found 1-bit register for signal <not_strict_mode.status_ram.rd_buf_we_r1>.
    Found 5-bit register for signal <not_strict_mode.rd_buf.rd_buf_indx_copy_r>.
    Found 1-bit register for signal <app_rd_data_valid>.
    Found 1-bit register for signal <app_rd_data_end>.
    Found 256-bit register for signal <app_rd_data>.
    Found 1-bit register for signal <not_strict_mode.app_rd_data_valid_copy>.
    Found 6-bit register for signal <not_strict_mode.occ_cnt_r>.
    Found 5-bit register for signal <not_strict_mode.rd_data_buf_addr_r_lcl>.
    Found 1-bit register for signal <ram_init_done_r_lcl>.
    Found 6-bit adder for signal <rd_buf_indx_r[5]_GND_116_o_add_2_OUT> created at line 186.
    Found 6-bit adder for signal <not_strict_mode.occ_plus_one> created at line 387.
    Found 5-bit adder for signal <not_strict_mode.rd_data_buf_addr_r_lcl[4]_GND_116_o_add_39_OUT> created at line 423.
    Found 6-bit subtractor for signal <not_strict_mode.occ_minus_one> created at line 386.
    Found 1-bit comparator equal for signal <not_strict_mode.rd_data_rdy> created at line 351
    Found 5-bit comparator equal for signal <not_strict_mode.rd_buf_wr_addr[4]_rd_buf_indx_r[4]_equal_23_o> created at line 352
INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal not_strict_mode.rd_buf_we may hinder XST clustering optimizations.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 291 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   6 Multiplexer(s).
Unit <mig_7series_v1_8_ui_rd_data> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v".
        C_FAMILY = "virtex7"
        C_S_AXI_ID_WIDTH = 4
        C_S_AXI_ADDR_WIDTH = 32
        C_S_AXI_DATA_WIDTH = 128
        C_MC_ADDR_WIDTH = 29
        C_MC_DATA_WIDTH = 256
        C_MC_BURST_MODE = "8"
        C_MC_nCK_PER_CLK = 4
        C_S_AXI_SUPPORTS_NARROW_BURST = 1
        C_S_AXI_REG_EN0 = 20'b00000000000000000000
        C_S_AXI_REG_EN1 = 20'b00000000000000000000
        C_RD_WR_ARB_ALGORITHM = "ROUND_ROBIN"
        C_ECC = "OFF"
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <S_AXI_BUSER> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <S_AXI_RUSER> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <M_AXI_AWREGION> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <M_AXI_AWUSER> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <M_AXI_WID> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <M_AXI_WUSER> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <M_AXI_ARREGION> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 464: Output port <M_AXI_ARUSER> of the instance <axi_register_slice_d1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <S_AXI_BUSER> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <S_AXI_RUSER> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <M_AXI_AWSIZE> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <M_AXI_AWREGION> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <M_AXI_AWUSER> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <M_AXI_WUSER> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <M_AXI_ARSIZE> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <M_AXI_ARREGION> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 585: Output port <M_AXI_ARUSER> of the instance <USE_UPSIZER.upsizer_d2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <S_AXI_BUSER> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <S_AXI_RUSER> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_AWSIZE> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_AWREGION> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_AWUSER> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_WID> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_WUSER> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_ARSIZE> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_ARREGION> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_ARUSER> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 738: Output port <M_AXI_WLAST> of the instance <axi_register_slice_d3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc.v" line 862: Output port <b_awlen> of the instance <axi_mc_aw_channel_0> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <mc_init_complete_r>.
    Found 1-bit register for signal <areset_d1>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <mig_7series_v1_8_axi_mc> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axi_register_slice_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_AXI_DATA_WIDTH = 128
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_AWUSER_WIDTH = 1
        C_AXI_ARUSER_WIDTH = 1
        C_AXI_WUSER_WIDTH = 1
        C_AXI_RUSER_WIDTH = 1
        C_AXI_BUSER_WIDTH = 1
        C_REG_CONFIG_AW = 0
        C_REG_CONFIG_W = 0
        C_REG_CONFIG_B = 0
        C_REG_CONFIG_AR = 0
        C_REG_CONFIG_R = 0
    Set property "shift_extract = no" for signal <reset>.
    Set property "IOB = FALSE" for signal <reset>.
    Set property "equivalent_register_removal = no" for signal <reset>.
WARNING:Xst:647 - Input <S_AXI_AWUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_WUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_ARUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_BUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_RUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <reset>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_axi_register_slice_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 66
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 149
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 6
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 135
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axi_upsizer>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_S_AXI_DATA_WIDTH = 128
        C_M_AXI_DATA_WIDTH = 256
        C_M_AXI_AW_REGISTER = 1
        C_M_AXI_W_REGISTER = 0
        C_M_AXI_AR_REGISTER = 1
        C_S_AXI_R_REGISTER = 0
        C_M_AXI_R_REGISTER = 1
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_AWUSER_WIDTH = 1
        C_AXI_ARUSER_WIDTH = 1
        C_AXI_WUSER_WIDTH = 1
        C_AXI_RUSER_WIDTH = 1
        C_AXI_BUSER_WIDTH = 1
        C_AXI_SUPPORTS_WRITE = 1
        C_AXI_SUPPORTS_READ = 1
        C_PACKING_LEVEL = 2
        C_SUPPORT_BURSTS = 1
        C_SINGLE_THREAD = 0
    Set property "equivalent_register_removal = no" for signal <ARESET>.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_BID> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_BRESP> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_BUSER> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_RID> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_RDATA> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_RRESP> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_RUSER> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_WID> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_WDATA> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_WSTRB> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_WUSER> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_WREADY> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_BVALID> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_RLAST> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <S_AXI_RVALID> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_WLAST> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_WVALID> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_BREADY> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 339: Output port <M_AXI_RREADY> of the instance <si_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <S_AXI_BID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <S_AXI_BRESP> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <S_AXI_BUSER> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWADDR> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWLEN> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWSIZE> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWBURST> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWLOCK> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWCACHE> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWPROT> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWREGION> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWQOS> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWUSER> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_WID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_WDATA> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_WSTRB> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_WUSER> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARADDR> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARLEN> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARSIZE> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARBURST> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARLOCK> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARCACHE> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARPROT> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARREGION> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARQOS> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARUSER> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <S_AXI_AWREADY> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <S_AXI_WREADY> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <S_AXI_BVALID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <S_AXI_ARREADY> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_AWVALID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_WLAST> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_WVALID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_BREADY> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 445: Output port <M_AXI_ARVALID> of the instance <mi_register_slice_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 654: Output port <M_AXI_WUSER> of the instance <USE_WRITE.write_data_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_upsizer.v" line 834: Output port <S_AXI_RUSER> of the instance <USE_READ.read_data_inst> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ARESET>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_axi_upsizer> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axi_register_slice_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_AXI_DATA_WIDTH = 128
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_AWUSER_WIDTH = 1
        C_AXI_ARUSER_WIDTH = 1
        C_AXI_WUSER_WIDTH = 1
        C_AXI_RUSER_WIDTH = 1
        C_AXI_BUSER_WIDTH = 1
        C_REG_CONFIG_AW = 32'b00000000000000000000000000000111
        C_REG_CONFIG_W = 32'b00000000000000000000000000000000
        C_REG_CONFIG_B = 32'b00000000000000000000000000000000
        C_REG_CONFIG_AR = 32'b00000000000000000000000000000111
        C_REG_CONFIG_R = 32'b00000000000000000000000000000000
    Set property "shift_extract = no" for signal <reset>.
    Set property "IOB = FALSE" for signal <reset>.
    Set property "equivalent_register_removal = no" for signal <reset>.
WARNING:Xst:647 - Input <S_AXI_AWUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_WUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_ARUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_BUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_RUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <reset>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_axi_register_slice_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_5>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 66
        C_REG_CONFIG = 32'b00000000000000000000000000000111
    Found 1-bit register for signal <s_ready_i>.
    Found 1-bit register for signal <m_valid_i>.
    Found 66-bit register for signal <storage_data1>.
    Found 2-bit register for signal <areset_d>.
    Summary:
	inferred  70 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_axic_register_slice_5> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_6>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 149
        C_REG_CONFIG = 32'b00000000000000000000000000000000
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_6> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_7>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 6
        C_REG_CONFIG = 32'b00000000000000000000000000000000
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_7> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_8>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 135
        C_REG_CONFIG = 32'b00000000000000000000000000000000
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_8> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axi_register_slice_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_AXI_DATA_WIDTH = 256
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_AWUSER_WIDTH = 1
        C_AXI_ARUSER_WIDTH = 1
        C_AXI_WUSER_WIDTH = 1
        C_AXI_RUSER_WIDTH = 1
        C_AXI_BUSER_WIDTH = 1
        C_REG_CONFIG_AW = 32'b00000000000000000000000000000000
        C_REG_CONFIG_W = 32'b00000000000000000000000000000000
        C_REG_CONFIG_B = 32'b00000000000000000000000000000000
        C_REG_CONFIG_AR = 32'b00000000000000000000000000000000
        C_REG_CONFIG_R = 1
    Set property "shift_extract = no" for signal <reset>.
    Set property "IOB = FALSE" for signal <reset>.
    Set property "equivalent_register_removal = no" for signal <reset>.
WARNING:Xst:647 - Input <S_AXI_AWUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_WUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_ARUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_BUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_RUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <reset>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_axi_register_slice_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_9>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 66
        C_REG_CONFIG = 32'b00000000000000000000000000000000
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_9> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_10>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 293
        C_REG_CONFIG = 32'b00000000000000000000000000000000
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_10> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_11>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 263
        C_REG_CONFIG = 1
    Set property "KEEP = TRUE" for signal <state>.
    Set property "MAX_FANOUT = 30" for signal <state>.
    Found 263-bit register for signal <storage_data1>.
    Found 263-bit register for signal <storage_data2>.
    Found 1-bit register for signal <s_ready_i>.
    Found 2-bit register for signal <state>.
    Found 2-bit register for signal <areset_d>.
    Summary:
	inferred 531 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_axic_register_slice_11> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_a_upsizer_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_S_AXI_DATA_WIDTH = 128
        C_M_AXI_DATA_WIDTH = 256
        C_M_AXI_REGISTER = 1
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_AUSER_WIDTH = 1
        C_AXI_CHANNEL = 0
        C_PACKING_LEVEL = 2
        C_SUPPORT_BURSTS = 1
        C_SINGLE_THREAD = 0
        C_S_AXI_BYTES_LOG = 4
        C_M_AXI_BYTES_LOG = 5
WARNING:Xst:647 - Input <S_AXI_AUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cmd_push_block>.
    Found 1-bit register for signal <USE_REGISTER.M_AXI_AVALID_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_AID_q>.
    Found 32-bit register for signal <USE_REGISTER.M_AXI_AADDR_q>.
    Found 8-bit register for signal <USE_REGISTER.M_AXI_ALEN_q>.
    Found 3-bit register for signal <USE_REGISTER.M_AXI_ASIZE_q>.
    Found 2-bit register for signal <USE_REGISTER.M_AXI_ABURST_q>.
    Found 2-bit register for signal <USE_REGISTER.M_AXI_ALOCK_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_ACACHE_q>.
    Found 3-bit register for signal <USE_REGISTER.M_AXI_APROT_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_AREGION_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_AQOS_q>.
    Found 1-bit register for signal <USE_REGISTER.M_AXI_AUSER_q>.
    Found 5-bit adder for signal <cmd_next_word_ii> created at line 568.
    Found 8-bit adder for signal <wrap_addr_aligned> created at line 724.
    Found 5-bit 7-to-1 multiplexer for signal <S_AXI_ASIZE[2]_GND_133_o_wide_mux_5_OUT> created at line 367.
    Found 8-bit 7-to-1 multiplexer for signal <S_AXI_ASIZE[2]_GND_133_o_wide_mux_7_OUT> created at line 401.
    Found 8-bit 8-to-1 multiplexer for signal <burst_mask> created at line 473.
    Found 8-bit comparator greater for signal <n0021> created at line 553
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  69 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  12 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_a_upsizer_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_carry_latch_and>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_and.v".
        C_FAMILY = "virtex7"
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_carry_latch_and> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_carry_and>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_and.v".
        C_FAMILY = "virtex7"
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_carry_and> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_command_fifo>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_command_fifo.v".
        C_FAMILY = "virtex7"
        C_ENABLE_S_VALID_CARRY = 1
        C_ENABLE_REGISTERED_OUTPUT = 1
        C_FIFO_DEPTH_LOG = 5
        C_FIFO_WIDTH = 42
    Found 1-bit register for signal <data_Exists_I>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_command_fifo> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_carry_latch_or>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_latch_or.v".
        C_FAMILY = "virtex7"
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_carry_latch_or> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_w_upsizer>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v".
        C_FAMILY = "virtex7"
        C_S_AXI_DATA_WIDTH = 128
        C_M_AXI_DATA_WIDTH = 256
        C_M_AXI_REGISTER = 1
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_WUSER_WIDTH = 1
        C_PACKING_LEVEL = 2
        C_SUPPORT_BURSTS = 1
        C_S_AXI_BYTES_LOG = 4
        C_M_AXI_BYTES_LOG = 5
        C_RATIO = 2
        C_RATIO_LOG = 1
WARNING:Xst:647 - Input <S_AXI_WUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v" line 402: Output port <O> of the instance <USE_FPGA_WORD_COMPLETED.word_complete_next_wrap_stall_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_w_upsizer.v" line 482: Output port <O> of the instance <USE_FPGA_WORD_COMPLETED.word_complete_rest_stall_inst> is unconnected or connected to loadless signal.
    Found 5-bit register for signal <USE_RTL_CURR_WORD.current_word_q>.
    Found 5-bit register for signal <USE_RTL_CURR_WORD.pre_next_word_q>.
    Found 1-bit register for signal <wrap_buffer_available>.
    Found 1-bit register for signal <USE_REGISTER.M_AXI_WLAST_q>.
    Found 1-bit register for signal <USE_REGISTER.M_AXI_WUSER_q>.
    Found 1-bit register for signal <USE_REGISTER.M_AXI_WVALID_q>.
    Found 1-bit register for signal <USE_RTL_CURR_WORD.first_word_q>.
    Summary:
	inferred  14 D-type flip-flop(s).
	inferred 577 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_w_upsizer> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_comparator_sel_static_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v".
        C_FAMILY = "virtex7"
        C_VALUE = 5'b00000
        C_DATA_WIDTH = 5
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_comparator_sel_static_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_carry_or>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_carry_or.v".
        C_FAMILY = "virtex7"
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_carry_or> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_comparator_sel_static_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel_static.v".
        C_FAMILY = "virtex7"
        C_VALUE = 8'b00000000
        C_DATA_WIDTH = 8
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_comparator_sel_static_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_comparator_sel>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_comparator_sel.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 5
    Found 1-bit comparator equal for signal <a_local[0]_v_local[0]_equal_4_o> created at line 138
    Found 1-bit comparator equal for signal <b_local[0]_v_local[0]_equal_6_o> created at line 140
    Found 1-bit comparator equal for signal <a_local[1]_v_local[1]_equal_8_o> created at line 138
    Found 1-bit comparator equal for signal <b_local[1]_v_local[1]_equal_10_o> created at line 140
    Found 1-bit comparator equal for signal <a_local[2]_v_local[2]_equal_12_o> created at line 138
    Found 1-bit comparator equal for signal <b_local[2]_v_local[2]_equal_14_o> created at line 140
    Found 1-bit comparator equal for signal <a_local[3]_v_local[3]_equal_16_o> created at line 138
    Found 1-bit comparator equal for signal <b_local[3]_v_local[3]_equal_18_o> created at line 140
    Found 1-bit comparator equal for signal <a_local[4]_v_local[4]_equal_20_o> created at line 138
    Found 1-bit comparator equal for signal <b_local[4]_v_local[4]_equal_22_o> created at line 140
    Summary:
	inferred  10 Comparator(s).
Unit <mig_7series_v1_8_ddr_comparator_sel> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_a_upsizer_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_a_upsizer.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_S_AXI_DATA_WIDTH = 128
        C_M_AXI_DATA_WIDTH = 256
        C_M_AXI_REGISTER = 1
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_AUSER_WIDTH = 1
        C_AXI_CHANNEL = 1
        C_PACKING_LEVEL = 2
        C_SUPPORT_BURSTS = 1
        C_SINGLE_THREAD = 0
        C_S_AXI_BYTES_LOG = 4
        C_M_AXI_BYTES_LOG = 5
WARNING:Xst:647 - Input <S_AXI_AUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cmd_push_block>.
    Found 1-bit register for signal <USE_REGISTER.M_AXI_AVALID_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_AID_q>.
    Found 32-bit register for signal <USE_REGISTER.M_AXI_AADDR_q>.
    Found 8-bit register for signal <USE_REGISTER.M_AXI_ALEN_q>.
    Found 3-bit register for signal <USE_REGISTER.M_AXI_ASIZE_q>.
    Found 2-bit register for signal <USE_REGISTER.M_AXI_ABURST_q>.
    Found 2-bit register for signal <USE_REGISTER.M_AXI_ALOCK_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_ACACHE_q>.
    Found 3-bit register for signal <USE_REGISTER.M_AXI_APROT_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_AREGION_q>.
    Found 4-bit register for signal <USE_REGISTER.M_AXI_AQOS_q>.
    Found 1-bit register for signal <USE_REGISTER.M_AXI_AUSER_q>.
    Found 5-bit adder for signal <cmd_next_word_ii> created at line 568.
    Found 5-bit 7-to-1 multiplexer for signal <S_AXI_ASIZE[2]_GND_154_o_wide_mux_5_OUT> created at line 367.
    Found 8-bit 7-to-1 multiplexer for signal <S_AXI_ASIZE[2]_GND_154_o_wide_mux_7_OUT> created at line 401.
    Found 8-bit 8-to-1 multiplexer for signal <burst_mask> created at line 473.
    Found 8-bit comparator greater for signal <n0021> created at line 553
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  69 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  12 Multiplexer(s).
Unit <mig_7series_v1_8_ddr_a_upsizer_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_r_upsizer>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_r_upsizer.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_S_AXI_DATA_WIDTH = 128
        C_M_AXI_DATA_WIDTH = 256
        C_S_AXI_REGISTER = 0
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_RUSER_WIDTH = 1
        C_PACKING_LEVEL = 2
        C_SUPPORT_BURSTS = 1
        C_S_AXI_BYTES_LOG = 4
        C_M_AXI_BYTES_LOG = 5
        C_RATIO = 2
        C_RATIO_LOG = 1
WARNING:Xst:647 - Input <M_AXI_RUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cmd_modified> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 5-bit register for signal <current_word_1>.
    Found 5-bit register for signal <pre_next_word_1>.
    Found 1-bit register for signal <wrap_buffer_available>.
    Found 1-bit register for signal <use_wrap_buffer>.
    Found 256-bit register for signal <M_AXI_RDATA_I>.
    Found 4-bit register for signal <rid_wrap_buffer>.
    Found 2-bit register for signal <rresp_wrap_buffer>.
    Found 1-bit register for signal <first_word>.
    Found 384-bit shifter logical right for signal <n0110> created at line 868
    Found 384-bit shifter logical right for signal <n0111> created at line 869
    Summary:
	inferred 275 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
	inferred   2 Combinational logic shifter(s).
Unit <mig_7series_v1_8_ddr_r_upsizer> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axi_register_slice_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axi_register_slice.v".
        C_FAMILY = "virtex7"
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_AXI_DATA_WIDTH = 256
        C_AXI_SUPPORTS_USER_SIGNALS = 0
        C_AXI_AWUSER_WIDTH = 1
        C_AXI_ARUSER_WIDTH = 1
        C_AXI_WUSER_WIDTH = 1
        C_AXI_RUSER_WIDTH = 1
        C_AXI_BUSER_WIDTH = 1
        C_REG_CONFIG_AW = 0
        C_REG_CONFIG_W = 0
        C_REG_CONFIG_B = 0
        C_REG_CONFIG_AR = 0
        C_REG_CONFIG_R = 0
    Set property "shift_extract = no" for signal <reset>.
    Set property "IOB = FALSE" for signal <reset>.
    Set property "equivalent_register_removal = no" for signal <reset>.
WARNING:Xst:647 - Input <S_AXI_AWUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_WUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_ARUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_BUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <M_AXI_RUSER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <reset>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mig_7series_v1_8_ddr_axi_register_slice_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_12>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 66
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_12> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_13>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 293
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_13> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_14>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 6
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_14> synthesized.

Synthesizing Unit <mig_7series_v1_8_ddr_axic_register_slice_15>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_ddr_axic_register_slice.v".
        C_FAMILY = "virtex7"
        C_DATA_WIDTH = 263
        C_REG_CONFIG = 0
WARNING:Xst:647 - Input <ACLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <mig_7series_v1_8_ddr_axic_register_slice_15> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_aw_channel>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v".
        C_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_MC_ADDR_WIDTH = 29
        C_DATA_WIDTH = 256
        C_MC_BURST_LEN = 1
        C_MC_nCK_PER_CLK = 4
        C_AXSIZE = 5
        C_ECC = "OFF"
WARNING:Xst:647 - Input <awlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <awcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <awprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <awqos> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v" line 198: Output port <w_push> of the instance <aw_cmd_fsm_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_aw_channel.v" line 198: Output port <r_push> of the instance <aw_cmd_fsm_0> is unconnected or connected to loadless signal.
    Found 8-bit register for signal <awlen_r>.
    Found 4-bit register for signal <awid_r>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <mig_7series_v1_8_axi_mc_aw_channel> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_cmd_translator>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_translator.v".
        C_AXI_ADDR_WIDTH = 32
        C_MC_ADDR_WIDTH = 29
        C_DATA_WIDTH = 256
        C_MC_BURST_LEN = 1
        C_MC_nCK_PER_CLK = 4
        C_AXSIZE = 5
    Found 2-bit register for signal <ax_burst_r>.
    Found 1-bit register for signal <axburst_eq1>.
    Found 1-bit register for signal <axburst_eq0>.
    Found 1-bit register for signal <sel_first>.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_cmd_translator> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_incr_cmd>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_incr_cmd.v".
        C_AXI_ADDR_WIDTH = 32
        C_MC_ADDR_WIDTH = 29
        C_DATA_WIDTH = 256
        C_MC_BURST_LEN = 1
        C_AXSIZE = 5
WARNING:Xst:647 - Input <axsize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <axlen_cnt>.
    Found 1-bit register for signal <next_pending_r>.
    Found 1-bit register for signal <sel_first>.
    Found 32-bit register for signal <axaddr_incr>.
    Found 10-bit subtractor for signal <GND_163_o_GND_163_o_sub_24_OUT> created at line 205.
    Found 32-bit adder for signal <axaddr[31]_GND_163_o_add_3_OUT> created at line 151.
    Found 32-bit adder for signal <axaddr_incr[31]_GND_163_o_add_5_OUT> created at line 153.
    Found 8-bit comparator lessequal for signal <n0014> created at line 201
    Found 9-bit comparator greater for signal <GND_163_o_axlen_cnt[8]_LessThan_23_o> created at line 204
    Found 32-bit comparator lessequal for signal <n0018> created at line 205
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  43 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_incr_cmd> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_wrap_cmd>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wrap_cmd.v".
        C_AXI_ADDR_WIDTH = 32
        C_MC_ADDR_WIDTH = 29
        C_MC_BURST_LEN = 1
        C_DATA_WIDTH = 256
        C_AXSIZE = 5
WARNING:Xst:647 - Input <axlen<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <axaddr_offset_r>.
    Found 4-bit register for signal <wrap_first_len_r>.
    Found 4-bit register for signal <wrap_second_len_r>.
    Found 32-bit register for signal <axaddr_wrap>.
    Found 5-bit register for signal <axlen_cnt>.
    Found 1-bit register for signal <next_pending_r>.
    Found 1-bit register for signal <sel_first>.
    Found 32-bit register for signal <wrap_boundary_axaddr_r>.
    Found 4-bit register for signal <wrap_cnt_r[3:0]>.
    Found 4-bit subtractor for signal <axlen_i[3]_axaddr_offset[3]_sub_11_OUT> created at line 210.
    Found 5-bit subtractor for signal <GND_164_o_GND_164_o_sub_13_OUT> created at line 213.
    Found 6-bit subtractor for signal <GND_164_o_GND_164_o_sub_63_OUT> created at line 300.
    Found 4-bit adder for signal <wrap_cnt<3:0>> created at line 254.
    Found 32-bit adder for signal <axaddr_wrap[31]_GND_164_o_add_35_OUT> created at line 265.
    Found 5-bit adder for signal <BUS_0005_GND_164_o_add_44_OUT> created at line 279.
    Found 5-bit adder for signal <n0132> created at line 296.
    Found 7-bit adder for signal <n0121> created at line 296.
    Found 32-bit shifter logical left for signal <GND_164_o_axsize[2]_shift_left_3_OUT> created at line 191
    Found 60-bit shifter logical right for signal <n0083> created at line 199
    Found 5-bit comparator equal for signal <axlen_cnt[4]_wrap_cnt_r[4]_equal_34_o> created at line 261
    Found 7-bit comparator lessequal for signal <n0045> created at line 296
    Found 5-bit comparator greater for signal <GND_164_o_axlen_cnt[4]_LessThan_62_o> created at line 299
    Found 32-bit comparator lessequal for signal <n0049> created at line 300
    WARNING:Xst:2404 -  FFs/Latches <wrap_cnt_r<4:4>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_axi_mc_wrap_cmd>.
    Summary:
	inferred   8 Adder/Subtractor(s).
	inferred  87 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  11 Multiplexer(s).
	inferred   2 Combinational logic shifter(s).
Unit <mig_7series_v1_8_axi_mc_wrap_cmd> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_wr_cmd_fsm>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_wr_cmd_fsm.v".
        C_MC_BURST_LEN = 1
        C_MC_RD_INST = 0
    Set property "MAX_FANOUT = 20" for signal <state>.
    Found 1-bit register for signal <init_complete_r1>.
    Found 2-bit register for signal <state>.
    Found 2-bit register for signal <state_r1>.
    Found 1-bit register for signal <init_complete_r>.
    Found finite state machine <FSM_9> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 12                                             |
    | Inputs             | 6                                              |
    | Outputs            | 7                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset_init_complete_r1_OR_1594_o (positive)       |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit 4-to-1 multiplexer for signal <next_state> created at line 174.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_axi_mc_wr_cmd_fsm> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_w_channel>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v".
        C_DATA_WIDTH = 256
        C_MC_BURST_LEN = 1
        C_AXI_ADDR_WIDTH = 32
WARNING:Xst:647 - Input <wwlen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <w_ignore_begin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <w_ignore_end> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <w_incr_burst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v" line 450: Output port <full> of the instance <wr_data_fifo_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_w_channel.v" line 450: Output port <a_empty> of the instance <wr_data_fifo_0> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <mc_init_complete_r1>.
    Found 5-bit register for signal <gen_bc1.w_cnt_r>.
    Found 1-bit register for signal <gen_bc1.w_cmd_pend_r>.
    Found 1-bit register for signal <fifo_wr_en>.
    Found 288-bit register for signal <fifo_in>.
    Found 1-bit register for signal <mc_init_complete_r>.
    Found 5-bit adder for signal <gen_bc1.w_cnt_r[4]_GND_166_o_add_8_OUT> created at line 194.
    Found 5-bit subtractor for signal <GND_166_o_GND_166_o_sub_6_OUT<4:0>> created at line 183.
    Found 5-bit comparator greater for signal <GND_166_o_gen_bc1.w_cnt_r[4]_LessThan_15_o> created at line 203
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 297 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_w_channel> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_simple_fifo_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v".
        C_WIDTH = 288
        C_AWIDTH = 3
        C_DEPTH = 8
    Set property "MAX_FANOUT = 10" for signal <cnt_read>.
    Found 3-bit register for signal <cnt_read>.
    Found 2304-bit register for signal <n0023[2303:0]>.
    Found 3-bit subtractor for signal <cnt_read[2]_GND_167_o_sub_6_OUT> created at line 126.
    Found 3-bit adder for signal <cnt_read[2]_GND_167_o_add_4_OUT> created at line 125.
    Found 288-bit 8-to-1 multiplexer for signal <dout> created at line 140.
    Found 3-bit comparator lessequal for signal <n0013> created at line 137
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 2307 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_simple_fifo_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_b_channel>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v".
        C_ID_WIDTH = 4
WARNING:Xst:647 - Input <b_resp_rdy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v" line 164: Output port <a_full> of the instance <bid_fifo_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_b_channel.v" line 164: Output port <a_empty> of the instance <bid_fifo_0> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <bhandshake_r>.
    Found 1-bit register for signal <bvalid_i>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <mig_7series_v1_8_axi_mc_b_channel> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_simple_fifo_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v".
        C_WIDTH = 4
        C_AWIDTH = 2
        C_DEPTH = 4
    Set property "MAX_FANOUT = 10" for signal <cnt_read>.
    Found 2-bit register for signal <cnt_read>.
    Found 16-bit register for signal <n0023[15:0]>.
    Found 2-bit subtractor for signal <cnt_read[1]_GND_169_o_sub_6_OUT> created at line 126.
    Found 2-bit adder for signal <cnt_read[1]_GND_169_o_add_4_OUT> created at line 125.
    Found 4-bit 4-to-1 multiplexer for signal <dout> created at line 140.
    Found 2-bit comparator lessequal for signal <n0013> created at line 137
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  18 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_simple_fifo_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_ar_channel>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v".
        C_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_MC_ADDR_WIDTH = 29
        C_DATA_WIDTH = 256
        C_MC_BURST_LEN = 1
        C_MC_nCK_PER_CLK = 4
        C_AXSIZE = 5
WARNING:Xst:647 - Input <arlock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <arcache> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <arprot> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <arqos> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v" line 181: Output port <b_push> of the instance <ar_cmd_fsm_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_ar_channel.v" line 181: Output port <w_push> of the instance <ar_cmd_fsm_0> is unconnected or connected to loadless signal.
    Found 4-bit register for signal <arid_r>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <mig_7series_v1_8_axi_mc_ar_channel> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_cmd_fsm>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_fsm.v".
        C_MC_BURST_LEN = 1
        C_MC_RD_INST = 1
    Set property "MAX_FANOUT = 20" for signal <state>.
WARNING:Xst:647 - Input <b_full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <init_complete_r1>.
    Found 2-bit register for signal <state>.
    Found 2-bit register for signal <state_r1>.
    Found 8-bit register for signal <axlen_r>.
    Found 1-bit register for signal <init_complete_r>.
    Found finite state machine <FSM_10> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 14                                             |
    | Inputs             | 6                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset_init_complete_r1_OR_1607_o (positive)       |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit 4-to-1 multiplexer for signal <next_state> created at line 178.
    Summary:
	inferred  14 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_axi_mc_cmd_fsm> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_r_channel>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v".
        C_ID_WIDTH = 4
        C_DATA_WIDTH = 256
        C_MC_BURST_LEN = 1
        C_AXI_ADDR_WIDTH = 32
        C_MC_nCK_PER_CLK = 2
        C_MC_BURST_MODE = "8"
WARNING:Xst:647 - Input <mc_app_rd_last> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" line 262: Output port <full> of the instance <rd_data_fifo_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" line 262: Output port <a_empty> of the instance <rd_data_fifo_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" line 285: Output port <full> of the instance <transaction_fifo_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_r_channel.v" line 285: Output port <a_empty> of the instance <transaction_fifo_0> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <r_rlast_r>.
    Found 1-bit register for signal <r_ignore_begin_r>.
    Found 1-bit register for signal <r_ignore_end_r>.
    Found 1-bit register for signal <r_push_r>.
    Found 7-bit register for signal <trans_buf_out_r>.
    Found 7-bit register for signal <trans_buf_out_r1>.
    Found 2-bit register for signal <state>.
    Found 4-bit register for signal <r_arid_r>.
    Found 2-bit 4-to-1 multiplexer for signal <state[1]_state[1]_wide_mux_29_OUT> created at line 347.
    HDL ADVISOR - Describing an operational reset or an explicit power-up state for register <state> would allow inference of a finite state machine and as consequence better performance and smaller area.
    Summary:
	inferred  24 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_r_channel> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_simple_fifo_3>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v".
        C_WIDTH = 257
        C_AWIDTH = 5
        C_DEPTH = 32
    Set property "MAX_FANOUT = 10" for signal <cnt_read>.
    Found 5-bit register for signal <cnt_read>.
    Found 8224-bit register for signal <n0023[8223:0]>.
    Found 5-bit subtractor for signal <cnt_read[4]_GND_173_o_sub_6_OUT> created at line 126.
    Found 5-bit adder for signal <cnt_read[4]_GND_173_o_add_4_OUT> created at line 125.
    Found 257-bit 32-to-1 multiplexer for signal <dout> created at line 140.
    Found 5-bit comparator lessequal for signal <n0013> created at line 137
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 8229 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_simple_fifo_3> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_simple_fifo_4>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_simple_fifo.v".
        C_WIDTH = 7
        C_AWIDTH = 5
        C_DEPTH = 32
    Set property "MAX_FANOUT = 10" for signal <cnt_read>.
    Found 5-bit register for signal <cnt_read>.
    Found 224-bit register for signal <n0023[223:0]>.
    Found 5-bit subtractor for signal <cnt_read[4]_GND_174_o_sub_6_OUT> created at line 126.
    Found 5-bit adder for signal <cnt_read[4]_GND_174_o_add_4_OUT> created at line 125.
    Found 7-bit 32-to-1 multiplexer for signal <dout> created at line 140.
    Found 5-bit comparator lessequal for signal <n0013> created at line 137
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 229 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_simple_fifo_4> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi_mc_cmd_arbiter>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/user_design/rtl/axi/mig_7series_v1_8_axi_mc_cmd_arbiter.v".
        C_MC_ADDR_WIDTH = 29
        C_MC_BURST_LEN = 1
        C_AXI_WR_STARVE_LIMIT = 256
        C_AXI_STARVE_CNT_WIDTH = 8
        C_RD_WR_ARB_ALGORITHM = "ROUND_ROBIN"
WARNING:Xst:647 - Input <wr_cmd_bl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rd_cmd_bl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <next_arqos> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <next_awqos> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rd_cmd_en_last> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wr_cmd_en_last> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <next_arvalid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <next_awvalid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <ROUND_ROBIN.rnw_i>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit <mig_7series_v1_8_axi_mc_cmd_arbiter> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi4_tg>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_tg.v".
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_AXI_DATA_WIDTH = 128
        C_AXI_NBURST_SUPPORT = 0
        C_EN_WRAP_TRANS = 0
        C_BEGIN_ADDRESS = 32'b00000000000000000000000000000000
        C_END_ADDRESS = 32'b00000000111111111111111111111111
        PRBS_EADDR_MASK_POS = 32'b11111111000000000000000000000000
        PRBS_SADDR_MASK_POS = 32'b00000000000000000010000000000000
        DBG_WR_STS_WIDTH = 32
        DBG_RD_STS_WIDTH = 32
        ENFORCE_RD_WR = 0
        ENFORCE_RD_WR_CMD = 8'b00010001
        EN_UPSIZER = 1
        ENFORCE_RD_WR_PATTERN = 3'b000
    Found 1-bit register for signal <cmptd_one_rd>.
    Found 1-bit register for signal <cmptd_one_wr_rd>.
    Found 1-bit register for signal <cmptd_one_wr>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <mig_7series_v1_8_axi4_tg> synthesized.

Synthesizing Unit <mig_7series_v1_8_axi4_wrapper>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_axi4_wrapper.v".
        C_AXI_ID_WIDTH = 4
        C_AXI_ADDR_WIDTH = 32
        C_AXI_DATA_WIDTH = 128
        C_AXI_NBURST_SUPPORT = 0
        C_BEGIN_ADDRESS = 32'b00000000000000000000000000000000
        C_END_ADDRESS = 32'b00000000111111111111111111111111
        CTL_SIG_WIDTH = 3
        WR_STS_WIDTH = 16
        RD_STS_WIDTH = 16
        EN_UPSIZER = 1
        WDG_TIMER_WIDTH = 11
WARNING:Xst:647 - Input <cmd<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wrdata_bvld> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <axi_rd_rresp<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 8-bit register for signal <blen_w>.
    Found 8-bit register for signal <blen_w_minus_1>.
    Found 32-bit register for signal <addr_w>.
    Found 3-bit register for signal <ctl_w>.
    Found 1-bit register for signal <wrap_r>.
    Found 8-bit register for signal <blen_r>.
    Found 32-bit register for signal <addr_r>.
    Found 3-bit register for signal <ctl_r>.
    Found 1-bit register for signal <wr_cmd_start>.
    Found 11-bit register for signal <wr_wdog_cntr>.
    Found 1-bit register for signal <wrdata_vld_r>.
    Found 1-bit register for signal <wrdata_cmptd_r>.
    Found 8-bit register for signal <blen_cntr>.
    Found 1-bit register for signal <pending_one_trans>.
    Found 8-bit register for signal <wr_len_cntr>.
    Found 9-bit register for signal <wstate>.
    Found 4-bit register for signal <wr_cntr>.
    Found 1-bit register for signal <axi_wvalid>.
    Found 128-bit register for signal <wrdata_r1>.
    Found 128-bit register for signal <wrdata_r2>.
    Found 1-bit register for signal <wrdata_rdy>.
    Found 1-bit register for signal <wrdata_sts_vld>.
    Found 1-bit register for signal <wrdata_mux_ctrl>.
    Found 1-bit register for signal <axi_wd_last>.
    Found 128-bit register for signal <axi_wd_data>.
    Found 16-bit register for signal <axi_wd_strb>.
    Found 1-bit register for signal <axi_wd_bready>.
    Found 3-bit register for signal <wrdata_fsm_sts>.
    Found 4-bit register for signal <brespid_r>.
    Found 2-bit register for signal <bresp_r>.
    Found 11-bit register for signal <rd_wdog_cntr>.
    Found 1-bit register for signal <rd_cmd_start>.
    Found 1-bit register for signal <rlast>.
    Found 6-bit register for signal <rstate>.
    Found 4-bit register for signal <rd_cntr>.
    Found 1-bit register for signal <axi_rvalid>.
    Found 1-bit register for signal <rddata_vld>.
    Found 1-bit register for signal <rddata_ppld>.
    Found 1-bit register for signal <axi_rd_rready>.
    Found 128-bit register for signal <rddata_p1>.
    Found 128-bit register for signal <rddata>.
    Found 1-bit register for signal <rddata_cmptd>.
    Found 1-bit register for signal <err_resp>.
    Found 2-bit register for signal <rddata_fsm_sts>.
    Found 1-bit register for signal <rrid_err>.
    Found 8-bit register for signal <rd_len_cntr>.
    Found 1-bit register for signal <wrap_w>.
INFO:Xst:1799 - State 000000000 is never reached in FSM <wstate>.
    Found finite state machine <FSM_13> for signal <wstate>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 69                                             |
    | Inputs             | 17                                             |
    | Outputs            | 12                                             |
    | Clock              | aclk (rising_edge)                             |
    | Reset              | aresetn (negative)                             |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000001                                      |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:1799 - State 000000 is never reached in FSM <rstate>.
    Found finite state machine <FSM_14> for signal <rstate>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 31                                             |
    | Inputs             | 11                                             |
    | Outputs            | 6                                              |
    | Clock              | aclk (rising_edge)                             |
    | Reset              | aresetn (negative)                             |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit subtractor for signal <blen[7]_GND_178_o_sub_2_OUT> created at line 276.
    Found 11-bit adder for signal <wr_wdog_cntr[10]_GND_178_o_add_26_OUT> created at line 319.
    Found 8-bit adder for signal <blen_cntr[7]_GND_178_o_add_33_OUT> created at line 334.
    Found 8-bit adder for signal <wr_len_cntr[7]_GND_178_o_add_39_OUT> created at line 349.
    Found 4-bit adder for signal <wr_cntr[3]_GND_178_o_add_84_OUT> created at line 466.
    Found 2-bit adder for signal <axi_wburst> created at line 482.
    Found 11-bit adder for signal <rd_wdog_cntr[10]_GND_178_o_add_136_OUT> created at line 631.
    Found 4-bit adder for signal <rd_cntr[3]_GND_178_o_add_163_OUT> created at line 723.
    Found 2-bit adder for signal <axi_rburst> created at line 749.
    Found 8-bit adder for signal <rd_len_cntr[7]_GND_178_o_add_197_OUT> created at line 855.
    Found 8-bit comparator greater for signal <wr_last_INV_1662_o> created at line 358
    Found 8-bit comparator greater for signal <wr_done_INV_1657_o> created at line 359
    Found 4-bit comparator not equal for signal <n0430> created at line 848
    Summary:
	inferred  10 Adder/Subtractor(s).
	inferred 836 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred  31 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <mig_7series_v1_8_axi4_wrapper> synthesized.

Synthesizing Unit <mig_7series_v1_8_tg>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_tg.v".
        C_AXI_ADDR_WIDTH = 32
        C_AXI_DATA_WIDTH = 128
        C_AXI_NBURST_SUPPORT = 0
        C_BEGIN_ADDRESS = 32'b00000000000000000000000000000000
        C_END_ADDRESS = 32'b00000000111111111111111111111111
        C_EN_WRAP_TRANS = 0
        CTL_SIG_WIDTH = 3
        WR_STS_WIDTH = 16
        RD_STS_WIDTH = 16
        DBG_WR_STS_WIDTH = 32
        DBG_RD_STS_WIDTH = 32
        ENFORCE_RD_WR = 0
        ENFORCE_RD_WR_CMD = 8'b00010001
        PRBS_EADDR_MASK_POS = 32'b11111111000000000000000000000000
        PRBS_SADDR_MASK_POS = 32'b00000000000000000010000000000000
        ENFORCE_RD_WR_PATTERN = 3'b000
    Found 1-bit register for signal <cmd_wr_en>.
    Found 1-bit register for signal <cmd_rd_en>.
    Found 1-bit register for signal <curr_wr_ptr>.
    Found 1-bit register for signal <curr_rd_ptr>.
    Found 1-bit register for signal <cmd_vld>.
    Found 1-bit register for signal <wr_proc>.
    Found 3-bit register for signal <shft_cntr>.
    Found 1-bit register for signal <cmd_wr_en_r>.
    Found 3-bit register for signal <seed_cntr>.
    Found 8-bit register for signal <cmd_gen_csr>.
    Found 8-bit register for signal <curr_blen1>.
    Found 8-bit register for signal <curr_blen2>.
    Found 8-bit register for signal <blen_cntr>.
    Found 32-bit register for signal <curr_addr1>.
    Found 32-bit register for signal <curr_addr2>.
    Found 1-bit register for signal <cmd_en>.
    Found 8-bit register for signal <blen>.
    Found 32-bit register for signal <addr>.
    Found 1-bit register for signal <wdata_cmptd>.
    Found 1-bit register for signal <cmd_err_dbg>.
    Found 1-bit register for signal <data_msmatch_err_dbg>.
    Found 1-bit register for signal <write_err_dbg>.
    Found 1-bit register for signal <read_err_dbg>.
    Found 1-bit register for signal <cmd_err>.
    Found 1-bit register for signal <data_msmatch_err>.
    Found 1-bit register for signal <write_err>.
    Found 1-bit register for signal <read_err>.
    Found 1-bit register for signal <dbg_wr_sts_vld>.
    Found 1-bit register for signal <dbg_rd_sts_vld>.
    Found 16-bit register for signal <wdata_sts_r>.
    Found 16-bit register for signal <rdata_sts_r>.
    Found 8-bit register for signal <tg_state>.
INFO:Xst:1799 - State 00000000 is never reached in FSM <tg_state>.
    Found finite state machine <FSM_15> for signal <tg_state>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 35                                             |
    | Inputs             | 13                                             |
    | Outputs            | 8                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | resetn (negative)                              |
    | Reset type         | synchronous                                    |
    | Reset State        | 00000001                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit subtractor for signal <blen_cntr[7]_GND_179_o_sub_75_OUT> created at line 484.
    Found 3-bit adder for signal <shft_cntr[2]_GND_179_o_add_43_OUT> created at line 365.
    Found 3-bit adder for signal <seed_cntr[2]_GND_179_o_add_51_OUT> created at line 421.
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 192 D-type flip-flop(s).
	inferred  23 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_tg> synthesized.

Synthesizing Unit <mig_7series_v1_8_data_gen_chk>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_data_gen_chk.v".
        C_AXI_DATA_WIDTH = 128
    Found 32-bit register for signal <walk0>.
    Found 8-bit register for signal <wrd_cntr>.
    Found 1-bit register for signal <msmatch_err_sig<0>>.
    Found 1-bit register for signal <msmatch_err_sig<1>>.
    Found 1-bit register for signal <msmatch_err_sig<2>>.
    Found 1-bit register for signal <msmatch_err_sig<3>>.
    Found 32-bit register for signal <lfsr_q>.
    Found 32-bit adder for signal <prbs_seed_i[31]_GND_180_o_add_1_OUT> created at line 101.
    Found 8-bit adder for signal <wrd_cntr[7]_GND_180_o_add_13_OUT> created at line 146.
    Found 8-bit comparator not equal for signal <n0019> created at line 156
    Found 8-bit comparator not equal for signal <n0022> created at line 157
    Found 8-bit comparator not equal for signal <n0026> created at line 158
    Found 8-bit comparator not equal for signal <n0030> created at line 159
    Found 8-bit comparator not equal for signal <n0037> created at line 156
    Found 8-bit comparator not equal for signal <n0040> created at line 157
    Found 8-bit comparator not equal for signal <n0044> created at line 158
    Found 8-bit comparator not equal for signal <n0048> created at line 159
    Found 8-bit comparator not equal for signal <n0055> created at line 156
    Found 8-bit comparator not equal for signal <n0058> created at line 157
    Found 8-bit comparator not equal for signal <n0062> created at line 158
    Found 8-bit comparator not equal for signal <n0066> created at line 159
    Found 8-bit comparator not equal for signal <n0073> created at line 156
    Found 8-bit comparator not equal for signal <n0076> created at line 157
    Found 8-bit comparator not equal for signal <n0080> created at line 158
    Found 8-bit comparator not equal for signal <n0084> created at line 159
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  76 D-type flip-flop(s).
	inferred  16 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <mig_7series_v1_8_data_gen_chk> synthesized.

Synthesizing Unit <mig_7series_v1_8_cmd_prbs_gen_axi_1>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v".
        TCQ = 100
        FAMILY = "SPARTAN6"
        ADDR_WIDTH = 32
        DWIDTH = 32
        PRBS_CMD = "BLEN"
        PRBS_WIDTH = 32
        SEED_WIDTH = 32
        PRBS_EADDR_MASK_POS = 32'b11111111111111111101000000000000
        PRBS_SADDR_MASK_POS = 32'b00000000000000000010000000000000
        PRBS_EADDR = 32'b00000000000000000010000000000000
        PRBS_SADDR = 32'b00000000000000000010000000000000
WARNING:Xst:647 - Input <prbs_seed_i<31:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <lfsr_q<31>>.
    Found 1-bit register for signal <lfsr_q<30>>.
    Found 1-bit register for signal <lfsr_q<29>>.
    Found 1-bit register for signal <lfsr_q<28>>.
    Found 1-bit register for signal <lfsr_q<27>>.
    Found 1-bit register for signal <lfsr_q<26>>.
    Found 1-bit register for signal <lfsr_q<25>>.
    Found 1-bit register for signal <lfsr_q<24>>.
    Found 1-bit register for signal <lfsr_q<23>>.
    Found 1-bit register for signal <lfsr_q<22>>.
    Found 1-bit register for signal <lfsr_q<21>>.
    Found 1-bit register for signal <lfsr_q<20>>.
    Found 1-bit register for signal <lfsr_q<19>>.
    Found 1-bit register for signal <lfsr_q<18>>.
    Found 1-bit register for signal <lfsr_q<17>>.
    Found 1-bit register for signal <lfsr_q<16>>.
    Found 1-bit register for signal <lfsr_q<15>>.
    Found 1-bit register for signal <lfsr_q<14>>.
    Found 1-bit register for signal <lfsr_q<13>>.
    Found 1-bit register for signal <lfsr_q<12>>.
    Found 1-bit register for signal <lfsr_q<11>>.
    Found 1-bit register for signal <lfsr_q<10>>.
    Found 1-bit register for signal <lfsr_q<9>>.
    Found 1-bit register for signal <lfsr_q<8>>.
    Found 1-bit register for signal <lfsr_q<7>>.
    Found 1-bit register for signal <lfsr_q<6>>.
    Found 1-bit register for signal <lfsr_q<5>>.
    Found 1-bit register for signal <lfsr_q<4>>.
    Found 1-bit register for signal <lfsr_q<3>>.
    Found 1-bit register for signal <lfsr_q<2>>.
    Found 1-bit register for signal <lfsr_q<1>>.
    Found 1-bit register for signal <lfsr_q<32>>.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred  15 Multiplexer(s).
Unit <mig_7series_v1_8_cmd_prbs_gen_axi_1> synthesized.

Synthesizing Unit <mig_7series_v1_8_cmd_prbs_gen_axi_2>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/traffic_gen/mig_7series_v1_8_cmd_prbs_gen_axi.v".
        TCQ = 100
        FAMILY = "VIRTEX7"
        ADDR_WIDTH = 32
        DWIDTH = 32
        PRBS_CMD = "ADDRESS"
        PRBS_WIDTH = 32
        SEED_WIDTH = 32
        PRBS_EADDR_MASK_POS = 32'b11111111000000000000000000000000
        PRBS_SADDR_MASK_POS = 32'b00000000000000000010000000000000
        PRBS_EADDR = 32'b00000000111111111111111111111111
        PRBS_SADDR = 32'b00000000000000000000000000000000
    Found 32-bit register for signal <lfsr_q>.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <mig_7series_v1_8_cmd_prbs_gen_axi_2> synthesized.

Synthesizing Unit <mig_7series_v1_8_chk_win>.
    Related source file is "/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/example_design/rtl/mig_7series_v1_8_chk_win.v".
        TCQ = 100
        nCK_PER_CLK = 4
        DLY_WIDTH = 26
        DQ_PER_DQS = 8
        DQ_WIDTH = 32
        SC_WIDTH = 3
        SDC_WIDTH = 5
        WIN_SIZE = 6
        SIM_OPTION = "FALSE"
WARNING:Xst:647 - Input <win_bit_select> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <win_current_bit> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 9-bit register for signal <po_curr_tap_cnt_r>.
    Found 1-bit register for signal <win_sel_pi_pon_r>.
    Found 4-bit register for signal <win_current_byte>.
    Found 1-bit register for signal <win_active>.
    Found 1-bit register for signal <win_clr_error>.
    Found 4-bit register for signal <byte_cntr>.
    Found 9-bit register for signal <offset_cntr>.
    Found 1-bit register for signal <read_valid_r>.
    Found 26-bit register for signal <delay_cntr>.
    Found 1-bit register for signal <pi_ss_right_r>.
    Found 1-bit register for signal <pi_ss_left_r>.
    Found 1-bit register for signal <po_ss_right_r>.
    Found 1-bit register for signal <po_ss_left_r>.
    Found 1-bit register for signal <po_win_tg_rst>.
    Found 9-bit register for signal <po_rst_cntr>.
    Found 1-bit register for signal <pi_win_up>.
    Found 1-bit register for signal <pi_win_down>.
    Found 1-bit register for signal <po_win_up>.
    Found 1-bit register for signal <po_win_down>.
    Found 1-bit register for signal <po_stg23_sel>.
    Found 3-bit register for signal <spread_cntr>.
    Found 1-bit register for signal <spread_cntr_msb_r>.
    Found 5-bit register for signal <short_dly_cntr>.
    Found 64-bit register for signal <rd_data_r>.
    Found 64-bit register for signal <cmp_data_r>.
    Found 1-bit register for signal <error_dqs>.
    Found 4-bit register for signal <win_state_r>.
    Found 6-bit register for signal <pi_curr_tap_cnt_r>.
    Found finite state machine <FSM_16> for signal <win_state_r>.
    -----------------------------------------------------------------------
    | States             | 15                                             |
    | Transitions        | 26                                             |
    | Inputs             | 7                                              |
    | Outputs            | 11                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <byte_cntr[3]_GND_189_o_add_17_OUT> created at line 354.
    Found 9-bit adder for signal <offset_cntr[8]_GND_189_o_add_23_OUT> created at line 369.
    Found 9-bit adder for signal <po_rst_cntr[8]_GND_189_o_add_40_OUT> created at line 434.
    Found 3-bit adder for signal <spread_cntr[2]_GND_189_o_add_59_OUT> created at line 577.
    Found 8-bit adder for signal <n0303> created at line 631.
    Found 8-bit adder for signal <n0306> created at line 633.
    Found 8-bit adder for signal <n0309> created at line 635.
    Found 8-bit adder for signal <GND_189_o_PWR_187_o_add_79_OUT> created at line 637.
    Found 8-bit adder for signal <GND_189_o_PWR_187_o_add_81_OUT> created at line 639.
    Found 8-bit adder for signal <GND_189_o_PWR_187_o_add_83_OUT> created at line 641.
    Found 8-bit adder for signal <GND_189_o_PWR_187_o_add_85_OUT> created at line 643.
    Found 9-bit subtractor for signal <GND_189_o_GND_189_o_sub_25_OUT<8:0>> created at line 371.
    Found 5-bit subtractor for signal <GND_189_o_GND_189_o_sub_67_OUT<4:0>> created at line 599.
    Found 504-bit shifter logical right for signal <n0226> created at line 629
    Found 504-bit shifter logical right for signal <n0228> created at line 631
    Found 504-bit shifter logical right for signal <n0230> created at line 633
    Found 504-bit shifter logical right for signal <n0232> created at line 635
    Found 504-bit shifter logical right for signal <n0234> created at line 637
    Found 504-bit shifter logical right for signal <n0236> created at line 639
    Found 504-bit shifter logical right for signal <n0238> created at line 641
    Found 504-bit shifter logical right for signal <n0240> created at line 643
    Found 504-bit shifter logical right for signal <n0241> created at line 645
    Found 504-bit shifter logical right for signal <n0242> created at line 647
    Found 504-bit shifter logical right for signal <n0243> created at line 649
    Found 504-bit shifter logical right for signal <n0244> created at line 651
    Found 504-bit shifter logical right for signal <n0245> created at line 653
    Found 504-bit shifter logical right for signal <n0246> created at line 655
    Found 504-bit shifter logical right for signal <n0247> created at line 657
    Found 504-bit shifter logical right for signal <n0248> created at line 659
    Found 64-bit comparator not equal for signal <n0148> created at line 670
    Found 4-bit comparator greater for signal <byte_cntr[3]_GND_189_o_LessThan_118_o> created at line 870
    WARNING:Xst:2404 -  FFs/Latches <mem_pattern_init_done_r<0:0>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_chk_win>.
    Summary:
	inferred  12 Adder/Subtractor(s).
	inferred 219 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  15 Multiplexer(s).
	inferred  16 Combinational logic shifter(s).
	inferred   1 Finite State Machine(s).
Unit <mig_7series_v1_8_chk_win> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 5
 4x3-bit single-port Read Only RAM                     : 1
 4x80-bit dual-port RAM                                : 4
# Multipliers                                          : 7
 3x2-bit multiplier                                    : 2
 3x3-bit multiplier                                    : 1
 4x2-bit multiplier                                    : 1
 4x3-bit multiplier                                    : 3
# Adders/Subtractors                                   : 568
 1-bit adder                                           : 15
 10-bit adder                                          : 4
 10-bit subtractor                                     : 2
 11-bit adder                                          : 3
 12-bit adder                                          : 5
 14-bit adder                                          : 1
 2-bit adder                                           : 45
 2-bit addsub                                          : 1
 2-bit subtractor                                      : 33
 20-bit subtractor                                     : 1
 3-bit adder                                           : 26
 3-bit addsub                                          : 2
 3-bit subtractor                                      : 11
 31-bit adder                                          : 12
 32-bit adder                                          : 7
 4-bit adder                                           : 20
 4-bit addsub                                          : 1
 4-bit subtractor                                      : 12
 5-bit adder                                           : 98
 5-bit addsub                                          : 10
 5-bit subtractor                                      : 9
 6-bit adder                                           : 71
 6-bit addsub                                          : 3
 6-bit subtractor                                      : 29
 7-bit adder                                           : 38
 7-bit addsub                                          : 1
 7-bit subtractor                                      : 11
 8-bit adder                                           : 52
 8-bit subtractor                                      : 12
 9-bit adder                                           : 30
 9-bit addsub                                          : 1
 9-bit subtractor                                      : 2
# Registers                                            : 2547
 1-bit register                                        : 1905
 10-bit register                                       : 3
 1024-bit register                                     : 1
 11-bit register                                       : 3
 12-bit register                                       : 23
 128-bit register                                      : 5
 129-bit register                                      : 1
 13-bit register                                       : 2
 14-bit register                                       : 2
 15-bit register                                       : 8
 16-bit register                                       : 7
 160-bit register                                      : 1
 17-bit register                                       : 1
 2-bit register                                        : 70
 20-bit register                                       : 2
 224-bit register                                      : 1
 2304-bit register                                     : 1
 24-bit register                                       : 11
 256-bit register                                      : 5
 26-bit register                                       : 1
 263-bit register                                      : 2
 288-bit register                                      : 2
 29-bit register                                       : 2
 3-bit register                                        : 86
 31-bit register                                       : 2
 32-bit register                                       : 19
 4-bit register                                        : 93
 44-bit register                                       : 8
 46-bit register                                       : 1
 5-bit register                                        : 51
 6-bit register                                        : 62
 60-bit register                                       : 1
 64-bit register                                       : 4
 66-bit register                                       : 2
 7-bit register                                        : 5
 8-bit register                                        : 76
 80-bit register                                       : 67
 8224-bit register                                     : 1
 9-bit register                                        : 10
# Comparators                                          : 497
 1-bit comparator equal                                : 210
 12-bit comparator greater                             : 16
 12-bit comparator not equal                           : 1
 15-bit comparator equal                               : 4
 2-bit comparator equal                                : 8
 2-bit comparator greater                              : 1
 2-bit comparator lessequal                            : 4
 3-bit comparator equal                                : 6
 3-bit comparator greater                              : 17
 3-bit comparator lessequal                            : 13
 32-bit comparator equal                               : 1
 32-bit comparator greater                             : 1
 32-bit comparator lessequal                           : 5
 4-bit comparator equal                                : 14
 4-bit comparator greater                              : 9
 4-bit comparator lessequal                            : 1
 4-bit comparator not equal                            : 1
 5-bit comparator equal                                : 4
 5-bit comparator greater                              : 9
 5-bit comparator lessequal                            : 39
 6-bit comparator greater                              : 31
 6-bit comparator lessequal                            : 19
 6-bit comparator not equal                            : 4
 64-bit comparator not equal                           : 1
 7-bit comparator equal                                : 1
 7-bit comparator lessequal                            : 16
 8-bit comparator greater                              : 4
 8-bit comparator lessequal                            : 16
 8-bit comparator not equal                            : 24
 9-bit comparator greater                              : 3
 9-bit comparator lessequal                            : 14
# Multiplexers                                         : 3078
 1-bit 2-to-1 multiplexer                              : 1943
 1-bit 3-to-1 multiplexer                              : 3
 1-bit 32-to-1 multiplexer                             : 256
 1-bit 4-to-1 multiplexer                              : 18
 1-bit 9-to-1 multiplexer                              : 1
 10-bit 2-to-1 multiplexer                             : 1
 12-bit 2-to-1 multiplexer                             : 13
 128-bit 2-to-1 multiplexer                            : 3
 15-bit 2-to-1 multiplexer                             : 15
 15-bit 4-to-1 multiplexer                             : 1
 17-bit 2-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 100
 2-bit 4-to-1 multiplexer                              : 3
 20-bit 2-to-1 multiplexer                             : 3
 22-bit 2-to-1 multiplexer                             : 22
 24-bit 2-to-1 multiplexer                             : 7
 257-bit 32-to-1 multiplexer                           : 1
 288-bit 8-to-1 multiplexer                            : 1
 29-bit 2-to-1 multiplexer                             : 1
 3-bit 2-to-1 multiplexer                              : 142
 3-bit 4-to-1 multiplexer                              : 6
 32-bit 2-to-1 multiplexer                             : 59
 4-bit 2-to-1 multiplexer                              : 79
 4-bit 4-to-1 multiplexer                              : 1
 42-bit 2-to-1 multiplexer                             : 2
 44-bit 2-to-1 multiplexer                             : 1
 44-bit 8-to-1 multiplexer                             : 1
 5-bit 2-to-1 multiplexer                              : 67
 5-bit 4-to-1 multiplexer                              : 1
 5-bit 7-to-1 multiplexer                              : 2
 5-bit 8-to-1 multiplexer                              : 1
 6-bit 2-to-1 multiplexer                              : 234
 6-bit 3-to-1 multiplexer                              : 2
 6-bit 4-to-1 multiplexer                              : 6
 60-bit 2-to-1 multiplexer                             : 1
 64-bit 2-to-1 multiplexer                             : 1
 7-bit 2-to-1 multiplexer                              : 5
 7-bit 32-to-1 multiplexer                             : 1
 8-bit 2-to-1 multiplexer                              : 22
 8-bit 7-to-1 multiplexer                              : 2
 8-bit 8-to-1 multiplexer                              : 2
 80-bit 2-to-1 multiplexer                             : 11
 80-bit 9-to-1 multiplexer                             : 7
 9-bit 2-to-1 multiplexer                              : 26
 9-bit 3-to-1 multiplexer                              : 1
 9-bit 4-to-1 multiplexer                              : 2
# Logic shifters                                       : 56
 1-bit shifter logical left                            : 9
 102-bit shifter logical right                         : 2
 14-bit shifter logical right                          : 1
 21-bit shifter logical right                          : 1
 285-bit shifter logical right                         : 1
 286-bit shifter logical right                         : 1
 32-bit shifter logical left                           : 2
 35-bit shifter logical right                          : 1
 384-bit shifter logical right                         : 2
 42-bit shifter logical right                          : 6
 504-bit shifter logical right                         : 24
 51-bit shifter logical right                          : 1
 6-bit shifter logical right                           : 3
 60-bit shifter logical right                          : 2
# FSMs                                                 : 15
# Xors                                                 : 31
 1-bit xor2                                            : 30
 1-bit xor4                                            : 1

=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_stg2_f_incdec<2> and po_stg2_f_incdec<2>1 po_stg2_f_incdec<2>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_stg2_f_incdec<1> and po_stg2_f_incdec<1>1 po_stg2_f_incdec<1>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_stg2_f_incdec<0> and po_stg2_f_incdec<0>1 po_stg2_f_incdec<0>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_sel_stg2stg3<2> and po_sel_stg2stg3<2>1 po_sel_stg2stg3<2>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_sel_stg2stg3<1> and po_sel_stg2stg3<1>1 po_sel_stg2stg3<1>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_sel_stg2stg3<0> and po_sel_stg2stg3<0>1 po_sel_stg2stg3<0>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_en_stg2_f<2> and po_en_stg2_f<2>1 po_en_stg2_f<2>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_en_stg2_f<1> and po_en_stg2_f<1>1 po_en_stg2_f<1>1 signal will be lost.
WARNING:Xst:638 - in unit mig_7series_v1_8_ddr_calib_top Conflict on KEEP property on signal po_en_stg2_f<0> and po_en_stg2_f<0>1 po_en_stg2_f<0>1 signal will be lost.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:2404 -  FFs/Latches <pi_dqs_found_any_bank<1:1>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_dqs_found_cal>.
WARNING:Xst:2404 -  FFs/Latches <phy_tmp_odt_r<3:1>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2404 -  FFs/Latches <pi_dqs_found_any_bank_r<1:1>> (without init value) have a constant value of 0 in block <mig_7series_v1_8_ddr_phy_dqs_found_cal>.

Synthesizing (advanced) Unit <example_top>.
Unit <example_top> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi4_wrapper>.
The following registers are absorbed into counter <wr_wdog_cntr>: 1 register on signal <wr_wdog_cntr>.
The following registers are absorbed into counter <wr_len_cntr>: 1 register on signal <wr_len_cntr>.
The following registers are absorbed into counter <blen_cntr>: 1 register on signal <blen_cntr>.
The following registers are absorbed into counter <wr_cntr>: 1 register on signal <wr_cntr>.
The following registers are absorbed into counter <rd_cntr>: 1 register on signal <rd_cntr>.
The following registers are absorbed into counter <rd_wdog_cntr>: 1 register on signal <rd_wdog_cntr>.
The following registers are absorbed into counter <rd_len_cntr>: 1 register on signal <rd_len_cntr>.
Unit <mig_7series_v1_8_axi4_wrapper> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_1>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_1> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_2>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_2> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_3>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_3> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_4>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_4> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_w_channel>.
The following registers are absorbed into accumulator <gen_bc1.w_cnt_r>: 1 register on signal <gen_bc1.w_cnt_r>.
Unit <mig_7series_v1_8_axi_mc_w_channel> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_bank_common>.
The following registers are absorbed into counter <rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r>: 1 register on signal <rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r>.
	The following adders/subtractors are grouped into adder tree <Madd_generate_maint_cmds.present_count_Madd1> :
 	<Madd_n0230> in block <mig_7series_v1_8_bank_common>, 	<Madd_n0236_Madd> in block <mig_7series_v1_8_bank_common>, 	<Madd_n0242_Madd> in block <mig_7series_v1_8_bank_common>, 	<Madd_generate_maint_cmds.present_count_Madd> in block <mig_7series_v1_8_bank_common>.
Unit <mig_7series_v1_8_bank_common> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_bank_state_1>.
The following registers are absorbed into counter <act_starve_limit_cntr_r>: 1 register on signal <act_starve_limit_cntr_r>.
The following registers are absorbed into counter <starve_limit_cntr_r>: 1 register on signal <starve_limit_cntr_r>.
The following registers are absorbed into counter <rp_timer_r_0>: 1 register on signal <rp_timer_r_0>.
The following registers are absorbed into counter <rtp_timer_r>: 1 register on signal <rtp_timer_r>.
Unit <mig_7series_v1_8_bank_state_1> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_bank_state_2>.
The following registers are absorbed into counter <act_starve_limit_cntr_r>: 1 register on signal <act_starve_limit_cntr_r>.
The following registers are absorbed into counter <starve_limit_cntr_r>: 1 register on signal <starve_limit_cntr_r>.
The following registers are absorbed into counter <rp_timer_r_0>: 1 register on signal <rp_timer_r_0>.
The following registers are absorbed into counter <rtp_timer_r>: 1 register on signal <rtp_timer_r>.
Unit <mig_7series_v1_8_bank_state_2> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_bank_state_3>.
The following registers are absorbed into counter <act_starve_limit_cntr_r>: 1 register on signal <act_starve_limit_cntr_r>.
The following registers are absorbed into counter <starve_limit_cntr_r>: 1 register on signal <starve_limit_cntr_r>.
The following registers are absorbed into counter <rp_timer_r_0>: 1 register on signal <rp_timer_r_0>.
The following registers are absorbed into counter <rtp_timer_r>: 1 register on signal <rtp_timer_r>.
Unit <mig_7series_v1_8_bank_state_3> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_bank_state_4>.
The following registers are absorbed into counter <act_starve_limit_cntr_r>: 1 register on signal <act_starve_limit_cntr_r>.
The following registers are absorbed into counter <starve_limit_cntr_r>: 1 register on signal <starve_limit_cntr_r>.
The following registers are absorbed into counter <rp_timer_r_0>: 1 register on signal <rp_timer_r_0>.
The following registers are absorbed into counter <rtp_timer_r>: 1 register on signal <rtp_timer_r>.
Unit <mig_7series_v1_8_bank_state_4> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_chk_win>.
The following registers are absorbed into counter <offset_cntr>: 1 register on signal <offset_cntr>.
The following registers are absorbed into counter <byte_cntr>: 1 register on signal <byte_cntr>.
The following registers are absorbed into counter <spread_cntr>: 1 register on signal <spread_cntr>.
The following registers are absorbed into counter <po_rst_cntr>: 1 register on signal <po_rst_cntr>.
The following registers are absorbed into counter <short_dly_cntr>: 1 register on signal <short_dly_cntr>.
Unit <mig_7series_v1_8_chk_win> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_col_mach>.
The following registers are absorbed into counter <read_fifo.head_r>: 1 register on signal <read_fifo.head_r>.
Unit <mig_7series_v1_8_col_mach> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_data_gen_chk>.
The following registers are absorbed into counter <wrd_cntr>: 1 register on signal <wrd_cntr>.
Unit <mig_7series_v1_8_data_gen_chk> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_if_post_fifo>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_mem> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 80-bit                     |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <wr_en>         | high     |
    |     addrA          | connected to signal <wr_ptr>        |          |
    |     diA            | connected to signal <d_in>          |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 4-word x 80-bit                     |          |
    |     addrB          | connected to signal <rd_ptr>        |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <mig_7series_v1_8_ddr_if_post_fifo> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_of_pre_fifo_1>.
The following registers are absorbed into counter <entry_cnt>: 1 register on signal <entry_cnt>.
Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_of_pre_fifo_2>.
The following registers are absorbed into counter <entry_cnt>: 1 register on signal <entry_cnt>.
Unit <mig_7series_v1_8_ddr_of_pre_fifo_2> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay>.
The following registers are absorbed into counter <delaydec_cnt_r>: 1 register on signal <delaydec_cnt_r>.
The following registers are absorbed into counter <wait_cnt_r>: 1 register on signal <wait_cnt_r>.
The following registers are absorbed into counter <delay_cnt_r>: 1 register on signal <delay_cnt_r>.
The following registers are absorbed into counter <ctl_lane_cnt>: 1 register on signal <ctl_lane_cnt>.
Unit <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_dqs_found_cal>.
The following registers are absorbed into counter <final_do_index_0>: 1 register on signal <final_do_index_0>.
The following registers are absorbed into counter <detect_rd_cnt>: 1 register on signal <detect_rd_cnt>.
The following registers are absorbed into counter <init_dec_cnt>: 1 register on signal <init_dec_cnt>.
The following registers are absorbed into counter <ctl_lane_cnt>: 1 register on signal <ctl_lane_cnt>.
The following registers are absorbed into counter <inc_cnt>: 1 register on signal <inc_cnt>.
The following registers are absorbed into counter <stable_pass_cnt>: 1 register on signal <stable_pass_cnt>.
The following registers are absorbed into counter <rnk_cnt_r>: 1 register on signal <rnk_cnt_r>.
The following registers are absorbed into counter <retry_cnt<9:0>>: 1 register on signal <retry_cnt<9:0>>.
The following registers are absorbed into counter <retry_cnt<10>_retry_cnt<11>_retry_cnt<12>_retry_cnt<13>_retry_cnt<14>_retry_cnt<15>_retry_cnt<16>_retry_cnt<17>_retry_cnt<18>_retry_cnt<19>>: 1 register on signal <retry_cnt<10>_retry_cnt<11>_retry_cnt<12>_retry_cnt<13>_retry_cnt<14>_retry_cnt<15>_retry_cnt<16>_retry_cnt<17>_retry_cnt<18>_retry_cnt<19>>.
Unit <mig_7series_v1_8_ddr_phy_dqs_found_cal> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_init>.
The following registers are absorbed into counter <cnt_cmd_r>: 1 register on signal <cnt_cmd_r>.
The following registers are absorbed into counter <cnt_wait>: 1 register on signal <cnt_wait>.
The following registers are absorbed into counter <cnt_pwron_ce_r>: 1 register on signal <cnt_pwron_ce_r>.
The following registers are absorbed into counter <cnt_txpr_r>: 1 register on signal <cnt_txpr_r>.
The following registers are absorbed into counter <cnt_dllk_zqinit_r>: 1 register on signal <cnt_dllk_zqinit_r>.
The following registers are absorbed into counter <oclk_wr_cnt>: 1 register on signal <oclk_wr_cnt>.
The following registers are absorbed into counter <wrcal_wr_cnt>: 1 register on signal <wrcal_wr_cnt>.
The following registers are absorbed into counter <enable_wrlvl_cnt>: 1 register on signal <enable_wrlvl_cnt>.
The following registers are absorbed into counter <dqs_asrt_cnt>: 1 register on signal <dqs_asrt_cnt>.
The following registers are absorbed into counter <cnt_pwron_r>: 1 register on signal <cnt_pwron_r>.
The following registers are absorbed into counter <cnt_init_mr_r>: 1 register on signal <cnt_init_mr_r>.
The following registers are absorbed into counter <cnt_init_af_r>: 1 register on signal <cnt_init_af_r>.
The following registers are absorbed into counter <num_refresh>: 1 register on signal <num_refresh>.
The following registers are absorbed into counter <reg_ctrl_cnt_r>: 1 register on signal <reg_ctrl_cnt_r>.
The following registers are absorbed into counter <pi_phaselock_timer>: 1 register on signal <pi_phaselock_timer>.
The following registers are absorbed into counter <num_reads>: 1 register on signal <num_reads>.
The following registers are absorbed into counter <calib_seq>: 1 register on signal <calib_seq>.
The following registers are absorbed into counter <wrcal_reads>: 1 register on signal <wrcal_reads>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cnt_init_mr_r[1]_GND_100_o_wide_mux_602_OUT> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 3-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cnt_init_mr_r> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <mig_7series_v1_8_ddr_phy_init> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_oclkdelay_cal>.
The following registers are absorbed into counter <wait_cnt_r>: 1 register on signal <wait_cnt_r>.
The following registers are absorbed into counter <delay_cnt_r>: 1 register on signal <delay_cnt_r>.
The following registers are absorbed into counter <stable_stg3_cnt>: 1 register on signal <stable_stg3_cnt>.
The following registers are absorbed into counter <cnt_dqs_r>: 1 register on signal <cnt_dqs_r>.
The following registers are absorbed into counter <stg2_inc2_cnt>: 1 register on signal <stg2_inc2_cnt>.
The following registers are absorbed into counter <stg2_dec2_cnt>: 1 register on signal <stg2_dec2_cnt>.
The following registers are absorbed into counter <ocal_dec_cnt>: 1 register on signal <ocal_dec_cnt>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <mig_7series_v1_8_ddr_phy_oclkdelay_cal> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_prbs_rdlvl>.
The following registers are absorbed into counter <wait_state_cnt_r>: 1 register on signal <wait_state_cnt_r>.
The following registers are absorbed into counter <samples_cnt_r>: 1 register on signal <samples_cnt_r>.
The following registers are absorbed into counter <samples_cnt1_r>: 1 register on signal <samples_cnt1_r>.
The following registers are absorbed into counter <samples_cnt2_r>: 1 register on signal <samples_cnt2_r>.
The following registers are absorbed into counter <prbs_dqs_cnt_r>: 1 register on signal <prbs_dqs_cnt_r>.
The following registers are absorbed into counter <prbs_dec_tap_cnt>: 1 register on signal <prbs_dec_tap_cnt>.
The following registers are absorbed into counter <rnk_cnt_r>: 1 register on signal <rnk_cnt_r>.
Unit <mig_7series_v1_8_ddr_phy_prbs_rdlvl> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_rdlvl>.
The following registers are absorbed into counter <tap_cnt_cpt_r>: 1 register on signal <tap_cnt_cpt_r>.
The following registers are absorbed into counter <pi_rdval_cnt>: 1 register on signal <pi_rdval_cnt>.
The following registers are absorbed into counter <cal1_wait_cnt_r>: 1 register on signal <cal1_wait_cnt_r>.
The following registers are absorbed into counter <wait_cnt_r>: 1 register on signal <wait_cnt_r>.
The following registers are absorbed into counter <stable_idel_cnt>: 1 register on signal <stable_idel_cnt>.
The following registers are absorbed into counter <done_cnt>: 1 register on signal <done_cnt>.
The following registers are absorbed into counter <regl_rank_cnt>: 1 register on signal <regl_rank_cnt>.
The following registers are absorbed into counter <regl_dqs_cnt>: 1 register on signal <regl_dqs_cnt>.
The following registers are absorbed into counter <cnt_shift_r>: 1 register on signal <cnt_shift_r>.
The following registers are absorbed into counter <samp_edge_cnt1_r>: 1 register on signal <samp_edge_cnt1_r>.
The following registers are absorbed into counter <samp_edge_cnt0_r>: 1 register on signal <samp_edge_cnt0_r>.
The following registers are absorbed into counter <idel_tap_cnt_dq_pb_r>: 1 register on signal <idel_tap_cnt_dq_pb_r>.
	Multiplier <Mmult_rnk_cnt_r[1]_PWR_108_o_MuLt_58_OUT> in block <mig_7series_v1_8_ddr_phy_rdlvl> and adder/subtractor <Madd_n3845_Madd> in block <mig_7series_v1_8_ddr_phy_rdlvl> are combined into a MAC<Maddsub_rnk_cnt_r[1]_PWR_108_o_MuLt_58_OUT>.
Unit <mig_7series_v1_8_ddr_phy_rdlvl> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_tempmon>.
The following registers are absorbed into counter <current_band>: 1 register on signal <current_band>.
Unit <mig_7series_v1_8_ddr_phy_tempmon> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_wrcal>.
The following registers are absorbed into counter <tap_inc_wait_cnt>: 1 register on signal <tap_inc_wait_cnt>.
The following registers are absorbed into counter <not_empty_wait_cnt>: 1 register on signal <not_empty_wait_cnt>.
The following registers are absorbed into counter <fine_inc_cnt>: 1 register on signal <fine_inc_cnt>.
The following registers are absorbed into counter <dec_cnt>: 1 register on signal <dec_cnt>.
The following registers are absorbed into counter <fine_dec_cnt>: 1 register on signal <fine_dec_cnt>.
The following registers are absorbed into counter <cal2_po_dly_cnt>: 1 register on signal <cal2_po_dly_cnt>.
The following registers are absorbed into counter <stable_pass_cnt>: 1 register on signal <stable_pass_cnt>.
The following registers are absorbed into counter <stable_pass_cnt1>: 1 register on signal <stable_pass_cnt1>.
The following registers are absorbed into counter <cal2_rd_cnt>: 1 register on signal <cal2_rd_cnt>.
Unit <mig_7series_v1_8_ddr_phy_wrcal> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_phy_wrlvl>.
The following registers are absorbed into counter <po_rdval_cnt>: 1 register on signal <po_rdval_cnt>.
The following registers are absorbed into counter <incdec_wait_cnt>: 1 register on signal <incdec_wait_cnt>.
The following registers are absorbed into counter <wait_cnt>: 1 register on signal <wait_cnt>.
The following registers are absorbed into counter <stable_cnt>: 1 register on signal <stable_cnt>.
The following registers are absorbed into counter <rank_cnt_r>: 1 register on signal <rank_cnt_r>.
The following registers are absorbed into counter <wrlvl_redo_corse_inc>: 1 register on signal <wrlvl_redo_corse_inc>.
Unit <mig_7series_v1_8_ddr_phy_wrlvl> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ddr_prbs_gen>.
The following registers are absorbed into counter <sample_cnt_r>: 1 register on signal <sample_cnt_r>.
Unit <mig_7series_v1_8_ddr_prbs_gen> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_rank_cntrl>.
The following registers are absorbed into counter <refresh_generation.refresh_bank_r_0>: 1 register on signal <refresh_generation.refresh_bank_r_0>.
The following registers are absorbed into counter <periodic_rd_generation.periodic_rd_cntr1_r>: 1 register on signal <periodic_rd_generation.periodic_rd_cntr1_r>.
The following registers are absorbed into counter <periodic_rd_generation.periodic_rd_timer_r>: 1 register on signal <periodic_rd_generation.periodic_rd_timer_r>.
Unit <mig_7series_v1_8_rank_cntrl> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_rank_common>.
The following registers are absorbed into counter <refresh_timer.refresh_timer_r>: 1 register on signal <refresh_timer.refresh_timer_r>.
The following registers are absorbed into counter <zq_cntrl.zq_timer.zq_timer_r>: 1 register on signal <zq_cntrl.zq_timer.zq_timer_r>.
The following registers are absorbed into counter <maint_prescaler.maint_prescaler_r>: 1 register on signal <maint_prescaler.maint_prescaler_r>.
The following registers are absorbed into counter <sr_cntrl.ckesr_timer.ckesr_timer_r>: 1 register on signal <sr_cntrl.ckesr_timer.ckesr_timer_r>.
Unit <mig_7series_v1_8_rank_common> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_tempmon>.
The following registers are absorbed into counter <sync_cntr>: 1 register on signal <sync_cntr>.
The following registers are absorbed into counter <xadc_supplied_temperature.sample_timer>: 1 register on signal <xadc_supplied_temperature.sample_timer>.
Unit <mig_7series_v1_8_tempmon> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_tg>.
The following registers are absorbed into counter <shft_cntr>: 1 register on signal <shft_cntr>.
The following registers are absorbed into counter <seed_cntr>: 1 register on signal <seed_cntr>.
The following registers are absorbed into counter <blen_cntr>: 1 register on signal <blen_cntr>.
Unit <mig_7series_v1_8_tg> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ui_rd_data>.
The following registers are absorbed into counter <not_strict_mode.rd_data_buf_addr_r_lcl>: 1 register on signal <not_strict_mode.rd_data_buf_addr_r_lcl>.
Unit <mig_7series_v1_8_ui_rd_data> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_ui_wr_data>.
The following registers are absorbed into counter <wr_data_indx_r>: 1 register on signal <wr_data_indx_r>.
The following registers are absorbed into counter <rd_data_indx_r>: 1 register on signal <rd_data_indx_r>.
The following registers are absorbed into counter <data_buf_addr_cnt_r>: 1 register on signal <data_buf_addr_cnt_r>.
Unit <mig_7series_v1_8_ui_wr_data> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_1>.
	Found 8-bit dynamic shift register for signal <dout<0>>.
	Found 8-bit dynamic shift register for signal <dout<1>>.
	Found 8-bit dynamic shift register for signal <dout<2>>.
	Found 8-bit dynamic shift register for signal <dout<3>>.
	Found 8-bit dynamic shift register for signal <dout<4>>.
	Found 8-bit dynamic shift register for signal <dout<5>>.
	Found 8-bit dynamic shift register for signal <dout<6>>.
	Found 8-bit dynamic shift register for signal <dout<7>>.
	Found 8-bit dynamic shift register for signal <dout<8>>.
	Found 8-bit dynamic shift register for signal <dout<9>>.
	Found 8-bit dynamic shift register for signal <dout<10>>.
	Found 8-bit dynamic shift register for signal <dout<11>>.
	Found 8-bit dynamic shift register for signal <dout<12>>.
	Found 8-bit dynamic shift register for signal <dout<13>>.
	Found 8-bit dynamic shift register for signal <dout<14>>.
	Found 8-bit dynamic shift register for signal <dout<15>>.
	Found 8-bit dynamic shift register for signal <dout<16>>.
	Found 8-bit dynamic shift register for signal <dout<17>>.
	Found 8-bit dynamic shift register for signal <dout<18>>.
	Found 8-bit dynamic shift register for signal <dout<19>>.
	Found 8-bit dynamic shift register for signal <dout<20>>.
	Found 8-bit dynamic shift register for signal <dout<21>>.
	Found 8-bit dynamic shift register for signal <dout<22>>.
	Found 8-bit dynamic shift register for signal <dout<23>>.
	Found 8-bit dynamic shift register for signal <dout<24>>.
	Found 8-bit dynamic shift register for signal <dout<25>>.
	Found 8-bit dynamic shift register for signal <dout<26>>.
	Found 8-bit dynamic shift register for signal <dout<27>>.
	Found 8-bit dynamic shift register for signal <dout<28>>.
	Found 8-bit dynamic shift register for signal <dout<29>>.
	Found 8-bit dynamic shift register for signal <dout<30>>.
	Found 8-bit dynamic shift register for signal <dout<31>>.
	Found 8-bit dynamic shift register for signal <dout<32>>.
	Found 8-bit dynamic shift register for signal <dout<33>>.
	Found 8-bit dynamic shift register for signal <dout<34>>.
	Found 8-bit dynamic shift register for signal <dout<35>>.
	Found 8-bit dynamic shift register for signal <dout<36>>.
	Found 8-bit dynamic shift register for signal <dout<37>>.
	Found 8-bit dynamic shift register for signal <dout<38>>.
	Found 8-bit dynamic shift register for signal <dout<39>>.
	Found 8-bit dynamic shift register for signal <dout<40>>.
	Found 8-bit dynamic shift register for signal <dout<41>>.
	Found 8-bit dynamic shift register for signal <dout<42>>.
	Found 8-bit dynamic shift register for signal <dout<43>>.
	Found 8-bit dynamic shift register for signal <dout<44>>.
	Found 8-bit dynamic shift register for signal <dout<45>>.
	Found 8-bit dynamic shift register for signal <dout<46>>.
	Found 8-bit dynamic shift register for signal <dout<47>>.
	Found 8-bit dynamic shift register for signal <dout<48>>.
	Found 8-bit dynamic shift register for signal <dout<49>>.
	Found 8-bit dynamic shift register for signal <dout<50>>.
	Found 8-bit dynamic shift register for signal <dout<51>>.
	Found 8-bit dynamic shift register for signal <dout<52>>.
	Found 8-bit dynamic shift register for signal <dout<53>>.
	Found 8-bit dynamic shift register for signal <dout<54>>.
	Found 8-bit dynamic shift register for signal <dout<55>>.
	Found 8-bit dynamic shift register for signal <dout<56>>.
	Found 8-bit dynamic shift register for signal <dout<57>>.
	Found 8-bit dynamic shift register for signal <dout<58>>.
	Found 8-bit dynamic shift register for signal <dout<59>>.
	Found 8-bit dynamic shift register for signal <dout<60>>.
	Found 8-bit dynamic shift register for signal <dout<61>>.
	Found 8-bit dynamic shift register for signal <dout<62>>.
	Found 8-bit dynamic shift register for signal <dout<63>>.
	Found 8-bit dynamic shift register for signal <dout<64>>.
	Found 8-bit dynamic shift register for signal <dout<65>>.
	Found 8-bit dynamic shift register for signal <dout<66>>.
	Found 8-bit dynamic shift register for signal <dout<67>>.
	Found 8-bit dynamic shift register for signal <dout<68>>.
	Found 8-bit dynamic shift register for signal <dout<69>>.
	Found 8-bit dynamic shift register for signal <dout<70>>.
	Found 8-bit dynamic shift register for signal <dout<71>>.
	Found 8-bit dynamic shift register for signal <dout<72>>.
	Found 8-bit dynamic shift register for signal <dout<73>>.
	Found 8-bit dynamic shift register for signal <dout<74>>.
	Found 8-bit dynamic shift register for signal <dout<75>>.
	Found 8-bit dynamic shift register for signal <dout<76>>.
	Found 8-bit dynamic shift register for signal <dout<77>>.
	Found 8-bit dynamic shift register for signal <dout<78>>.
	Found 8-bit dynamic shift register for signal <dout<79>>.
	Found 8-bit dynamic shift register for signal <dout<80>>.
	Found 8-bit dynamic shift register for signal <dout<81>>.
	Found 8-bit dynamic shift register for signal <dout<82>>.
	Found 8-bit dynamic shift register for signal <dout<83>>.
	Found 8-bit dynamic shift register for signal <dout<84>>.
	Found 8-bit dynamic shift register for signal <dout<85>>.
	Found 8-bit dynamic shift register for signal <dout<86>>.
	Found 8-bit dynamic shift register for signal <dout<87>>.
	Found 8-bit dynamic shift register for signal <dout<88>>.
	Found 8-bit dynamic shift register for signal <dout<89>>.
	Found 8-bit dynamic shift register for signal <dout<90>>.
	Found 8-bit dynamic shift register for signal <dout<91>>.
	Found 8-bit dynamic shift register for signal <dout<92>>.
	Found 8-bit dynamic shift register for signal <dout<93>>.
	Found 8-bit dynamic shift register for signal <dout<94>>.
	Found 8-bit dynamic shift register for signal <dout<95>>.
	Found 8-bit dynamic shift register for signal <dout<96>>.
	Found 8-bit dynamic shift register for signal <dout<97>>.
	Found 8-bit dynamic shift register for signal <dout<98>>.
	Found 8-bit dynamic shift register for signal <dout<99>>.
	Found 8-bit dynamic shift register for signal <dout<100>>.
	Found 8-bit dynamic shift register for signal <dout<101>>.
	Found 8-bit dynamic shift register for signal <dout<102>>.
	Found 8-bit dynamic shift register for signal <dout<103>>.
	Found 8-bit dynamic shift register for signal <dout<104>>.
	Found 8-bit dynamic shift register for signal <dout<105>>.
	Found 8-bit dynamic shift register for signal <dout<106>>.
	Found 8-bit dynamic shift register for signal <dout<107>>.
	Found 8-bit dynamic shift register for signal <dout<108>>.
	Found 8-bit dynamic shift register for signal <dout<109>>.
	Found 8-bit dynamic shift register for signal <dout<110>>.
	Found 8-bit dynamic shift register for signal <dout<111>>.
	Found 8-bit dynamic shift register for signal <dout<112>>.
	Found 8-bit dynamic shift register for signal <dout<113>>.
	Found 8-bit dynamic shift register for signal <dout<114>>.
	Found 8-bit dynamic shift register for signal <dout<115>>.
	Found 8-bit dynamic shift register for signal <dout<116>>.
	Found 8-bit dynamic shift register for signal <dout<117>>.
	Found 8-bit dynamic shift register for signal <dout<118>>.
	Found 8-bit dynamic shift register for signal <dout<119>>.
	Found 8-bit dynamic shift register for signal <dout<120>>.
	Found 8-bit dynamic shift register for signal <dout<121>>.
	Found 8-bit dynamic shift register for signal <dout<122>>.
	Found 8-bit dynamic shift register for signal <dout<123>>.
	Found 8-bit dynamic shift register for signal <dout<124>>.
	Found 8-bit dynamic shift register for signal <dout<125>>.
	Found 8-bit dynamic shift register for signal <dout<126>>.
	Found 8-bit dynamic shift register for signal <dout<127>>.
	Found 8-bit dynamic shift register for signal <dout<128>>.
	Found 8-bit dynamic shift register for signal <dout<129>>.
	Found 8-bit dynamic shift register for signal <dout<130>>.
	Found 8-bit dynamic shift register for signal <dout<131>>.
	Found 8-bit dynamic shift register for signal <dout<132>>.
	Found 8-bit dynamic shift register for signal <dout<133>>.
	Found 8-bit dynamic shift register for signal <dout<134>>.
	Found 8-bit dynamic shift register for signal <dout<135>>.
	Found 8-bit dynamic shift register for signal <dout<136>>.
	Found 8-bit dynamic shift register for signal <dout<137>>.
	Found 8-bit dynamic shift register for signal <dout<138>>.
	Found 8-bit dynamic shift register for signal <dout<139>>.
	Found 8-bit dynamic shift register for signal <dout<140>>.
	Found 8-bit dynamic shift register for signal <dout<141>>.
	Found 8-bit dynamic shift register for signal <dout<142>>.
	Found 8-bit dynamic shift register for signal <dout<143>>.
	Found 8-bit dynamic shift register for signal <dout<144>>.
	Found 8-bit dynamic shift register for signal <dout<145>>.
	Found 8-bit dynamic shift register for signal <dout<146>>.
	Found 8-bit dynamic shift register for signal <dout<147>>.
	Found 8-bit dynamic shift register for signal <dout<148>>.
	Found 8-bit dynamic shift register for signal <dout<149>>.
	Found 8-bit dynamic shift register for signal <dout<150>>.
	Found 8-bit dynamic shift register for signal <dout<151>>.
	Found 8-bit dynamic shift register for signal <dout<152>>.
	Found 8-bit dynamic shift register for signal <dout<153>>.
	Found 8-bit dynamic shift register for signal <dout<154>>.
	Found 8-bit dynamic shift register for signal <dout<155>>.
	Found 8-bit dynamic shift register for signal <dout<156>>.
	Found 8-bit dynamic shift register for signal <dout<157>>.
	Found 8-bit dynamic shift register for signal <dout<158>>.
	Found 8-bit dynamic shift register for signal <dout<159>>.
	Found 8-bit dynamic shift register for signal <dout<160>>.
	Found 8-bit dynamic shift register for signal <dout<161>>.
	Found 8-bit dynamic shift register for signal <dout<162>>.
	Found 8-bit dynamic shift register for signal <dout<163>>.
	Found 8-bit dynamic shift register for signal <dout<164>>.
	Found 8-bit dynamic shift register for signal <dout<165>>.
	Found 8-bit dynamic shift register for signal <dout<166>>.
	Found 8-bit dynamic shift register for signal <dout<167>>.
	Found 8-bit dynamic shift register for signal <dout<168>>.
	Found 8-bit dynamic shift register for signal <dout<169>>.
	Found 8-bit dynamic shift register for signal <dout<170>>.
	Found 8-bit dynamic shift register for signal <dout<171>>.
	Found 8-bit dynamic shift register for signal <dout<172>>.
	Found 8-bit dynamic shift register for signal <dout<173>>.
	Found 8-bit dynamic shift register for signal <dout<174>>.
	Found 8-bit dynamic shift register for signal <dout<175>>.
	Found 8-bit dynamic shift register for signal <dout<176>>.
	Found 8-bit dynamic shift register for signal <dout<177>>.
	Found 8-bit dynamic shift register for signal <dout<178>>.
	Found 8-bit dynamic shift register for signal <dout<179>>.
	Found 8-bit dynamic shift register for signal <dout<180>>.
	Found 8-bit dynamic shift register for signal <dout<181>>.
	Found 8-bit dynamic shift register for signal <dout<182>>.
	Found 8-bit dynamic shift register for signal <dout<183>>.
	Found 8-bit dynamic shift register for signal <dout<184>>.
	Found 8-bit dynamic shift register for signal <dout<185>>.
	Found 8-bit dynamic shift register for signal <dout<186>>.
	Found 8-bit dynamic shift register for signal <dout<187>>.
	Found 8-bit dynamic shift register for signal <dout<188>>.
	Found 8-bit dynamic shift register for signal <dout<189>>.
	Found 8-bit dynamic shift register for signal <dout<190>>.
	Found 8-bit dynamic shift register for signal <dout<191>>.
	Found 8-bit dynamic shift register for signal <dout<192>>.
	Found 8-bit dynamic shift register for signal <dout<193>>.
	Found 8-bit dynamic shift register for signal <dout<194>>.
	Found 8-bit dynamic shift register for signal <dout<195>>.
	Found 8-bit dynamic shift register for signal <dout<196>>.
	Found 8-bit dynamic shift register for signal <dout<197>>.
	Found 8-bit dynamic shift register for signal <dout<198>>.
	Found 8-bit dynamic shift register for signal <dout<199>>.
	Found 8-bit dynamic shift register for signal <dout<200>>.
	Found 8-bit dynamic shift register for signal <dout<201>>.
	Found 8-bit dynamic shift register for signal <dout<202>>.
	Found 8-bit dynamic shift register for signal <dout<203>>.
	Found 8-bit dynamic shift register for signal <dout<204>>.
	Found 8-bit dynamic shift register for signal <dout<205>>.
	Found 8-bit dynamic shift register for signal <dout<206>>.
	Found 8-bit dynamic shift register for signal <dout<207>>.
	Found 8-bit dynamic shift register for signal <dout<208>>.
	Found 8-bit dynamic shift register for signal <dout<209>>.
	Found 8-bit dynamic shift register for signal <dout<210>>.
	Found 8-bit dynamic shift register for signal <dout<211>>.
	Found 8-bit dynamic shift register for signal <dout<212>>.
	Found 8-bit dynamic shift register for signal <dout<213>>.
	Found 8-bit dynamic shift register for signal <dout<214>>.
	Found 8-bit dynamic shift register for signal <dout<215>>.
	Found 8-bit dynamic shift register for signal <dout<216>>.
	Found 8-bit dynamic shift register for signal <dout<217>>.
	Found 8-bit dynamic shift register for signal <dout<218>>.
	Found 8-bit dynamic shift register for signal <dout<219>>.
	Found 8-bit dynamic shift register for signal <dout<220>>.
	Found 8-bit dynamic shift register for signal <dout<221>>.
	Found 8-bit dynamic shift register for signal <dout<222>>.
	Found 8-bit dynamic shift register for signal <dout<223>>.
	Found 8-bit dynamic shift register for signal <dout<224>>.
	Found 8-bit dynamic shift register for signal <dout<225>>.
	Found 8-bit dynamic shift register for signal <dout<226>>.
	Found 8-bit dynamic shift register for signal <dout<227>>.
	Found 8-bit dynamic shift register for signal <dout<228>>.
	Found 8-bit dynamic shift register for signal <dout<229>>.
	Found 8-bit dynamic shift register for signal <dout<230>>.
	Found 8-bit dynamic shift register for signal <dout<231>>.
	Found 8-bit dynamic shift register for signal <dout<232>>.
	Found 8-bit dynamic shift register for signal <dout<233>>.
	Found 8-bit dynamic shift register for signal <dout<234>>.
	Found 8-bit dynamic shift register for signal <dout<235>>.
	Found 8-bit dynamic shift register for signal <dout<236>>.
	Found 8-bit dynamic shift register for signal <dout<237>>.
	Found 8-bit dynamic shift register for signal <dout<238>>.
	Found 8-bit dynamic shift register for signal <dout<239>>.
	Found 8-bit dynamic shift register for signal <dout<240>>.
	Found 8-bit dynamic shift register for signal <dout<241>>.
	Found 8-bit dynamic shift register for signal <dout<242>>.
	Found 8-bit dynamic shift register for signal <dout<243>>.
	Found 8-bit dynamic shift register for signal <dout<244>>.
	Found 8-bit dynamic shift register for signal <dout<245>>.
	Found 8-bit dynamic shift register for signal <dout<246>>.
	Found 8-bit dynamic shift register for signal <dout<247>>.
	Found 8-bit dynamic shift register for signal <dout<248>>.
	Found 8-bit dynamic shift register for signal <dout<249>>.
	Found 8-bit dynamic shift register for signal <dout<250>>.
	Found 8-bit dynamic shift register for signal <dout<251>>.
	Found 8-bit dynamic shift register for signal <dout<252>>.
	Found 8-bit dynamic shift register for signal <dout<253>>.
	Found 8-bit dynamic shift register for signal <dout<254>>.
	Found 8-bit dynamic shift register for signal <dout<255>>.
	Found 8-bit dynamic shift register for signal <dout<256>>.
	Found 8-bit dynamic shift register for signal <dout<257>>.
	Found 8-bit dynamic shift register for signal <dout<258>>.
	Found 8-bit dynamic shift register for signal <dout<259>>.
	Found 8-bit dynamic shift register for signal <dout<260>>.
	Found 8-bit dynamic shift register for signal <dout<261>>.
	Found 8-bit dynamic shift register for signal <dout<262>>.
	Found 8-bit dynamic shift register for signal <dout<263>>.
	Found 8-bit dynamic shift register for signal <dout<264>>.
	Found 8-bit dynamic shift register for signal <dout<265>>.
	Found 8-bit dynamic shift register for signal <dout<266>>.
	Found 8-bit dynamic shift register for signal <dout<267>>.
	Found 8-bit dynamic shift register for signal <dout<268>>.
	Found 8-bit dynamic shift register for signal <dout<269>>.
	Found 8-bit dynamic shift register for signal <dout<270>>.
	Found 8-bit dynamic shift register for signal <dout<271>>.
	Found 8-bit dynamic shift register for signal <dout<272>>.
	Found 8-bit dynamic shift register for signal <dout<273>>.
	Found 8-bit dynamic shift register for signal <dout<274>>.
	Found 8-bit dynamic shift register for signal <dout<275>>.
	Found 8-bit dynamic shift register for signal <dout<276>>.
	Found 8-bit dynamic shift register for signal <dout<277>>.
	Found 8-bit dynamic shift register for signal <dout<278>>.
	Found 8-bit dynamic shift register for signal <dout<279>>.
	Found 8-bit dynamic shift register for signal <dout<280>>.
	Found 8-bit dynamic shift register for signal <dout<281>>.
	Found 8-bit dynamic shift register for signal <dout<282>>.
	Found 8-bit dynamic shift register for signal <dout<283>>.
	Found 8-bit dynamic shift register for signal <dout<284>>.
	Found 8-bit dynamic shift register for signal <dout<285>>.
	Found 8-bit dynamic shift register for signal <dout<286>>.
	Found 8-bit dynamic shift register for signal <dout<287>>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_1> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_2>.
	Found 4-bit dynamic shift register for signal <dout<0>>.
	Found 4-bit dynamic shift register for signal <dout<1>>.
	Found 4-bit dynamic shift register for signal <dout<2>>.
	Found 4-bit dynamic shift register for signal <dout<3>>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_2> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_3>.
	Found 32-bit dynamic shift register for signal <dout<0>>.
	Found 32-bit dynamic shift register for signal <dout<1>>.
	Found 32-bit dynamic shift register for signal <dout<2>>.
	Found 32-bit dynamic shift register for signal <dout<3>>.
	Found 32-bit dynamic shift register for signal <dout<4>>.
	Found 32-bit dynamic shift register for signal <dout<5>>.
	Found 32-bit dynamic shift register for signal <dout<6>>.
	Found 32-bit dynamic shift register for signal <dout<7>>.
	Found 32-bit dynamic shift register for signal <dout<8>>.
	Found 32-bit dynamic shift register for signal <dout<9>>.
	Found 32-bit dynamic shift register for signal <dout<10>>.
	Found 32-bit dynamic shift register for signal <dout<11>>.
	Found 32-bit dynamic shift register for signal <dout<12>>.
	Found 32-bit dynamic shift register for signal <dout<13>>.
	Found 32-bit dynamic shift register for signal <dout<14>>.
	Found 32-bit dynamic shift register for signal <dout<15>>.
	Found 32-bit dynamic shift register for signal <dout<16>>.
	Found 32-bit dynamic shift register for signal <dout<17>>.
	Found 32-bit dynamic shift register for signal <dout<18>>.
	Found 32-bit dynamic shift register for signal <dout<19>>.
	Found 32-bit dynamic shift register for signal <dout<20>>.
	Found 32-bit dynamic shift register for signal <dout<21>>.
	Found 32-bit dynamic shift register for signal <dout<22>>.
	Found 32-bit dynamic shift register for signal <dout<23>>.
	Found 32-bit dynamic shift register for signal <dout<24>>.
	Found 32-bit dynamic shift register for signal <dout<25>>.
	Found 32-bit dynamic shift register for signal <dout<26>>.
	Found 32-bit dynamic shift register for signal <dout<27>>.
	Found 32-bit dynamic shift register for signal <dout<28>>.
	Found 32-bit dynamic shift register for signal <dout<29>>.
	Found 32-bit dynamic shift register for signal <dout<30>>.
	Found 32-bit dynamic shift register for signal <dout<31>>.
	Found 32-bit dynamic shift register for signal <dout<32>>.
	Found 32-bit dynamic shift register for signal <dout<33>>.
	Found 32-bit dynamic shift register for signal <dout<34>>.
	Found 32-bit dynamic shift register for signal <dout<35>>.
	Found 32-bit dynamic shift register for signal <dout<36>>.
	Found 32-bit dynamic shift register for signal <dout<37>>.
	Found 32-bit dynamic shift register for signal <dout<38>>.
	Found 32-bit dynamic shift register for signal <dout<39>>.
	Found 32-bit dynamic shift register for signal <dout<40>>.
	Found 32-bit dynamic shift register for signal <dout<41>>.
	Found 32-bit dynamic shift register for signal <dout<42>>.
	Found 32-bit dynamic shift register for signal <dout<43>>.
	Found 32-bit dynamic shift register for signal <dout<44>>.
	Found 32-bit dynamic shift register for signal <dout<45>>.
	Found 32-bit dynamic shift register for signal <dout<46>>.
	Found 32-bit dynamic shift register for signal <dout<47>>.
	Found 32-bit dynamic shift register for signal <dout<48>>.
	Found 32-bit dynamic shift register for signal <dout<49>>.
	Found 32-bit dynamic shift register for signal <dout<50>>.
	Found 32-bit dynamic shift register for signal <dout<51>>.
	Found 32-bit dynamic shift register for signal <dout<52>>.
	Found 32-bit dynamic shift register for signal <dout<53>>.
	Found 32-bit dynamic shift register for signal <dout<54>>.
	Found 32-bit dynamic shift register for signal <dout<55>>.
	Found 32-bit dynamic shift register for signal <dout<56>>.
	Found 32-bit dynamic shift register for signal <dout<57>>.
	Found 32-bit dynamic shift register for signal <dout<58>>.
	Found 32-bit dynamic shift register for signal <dout<59>>.
	Found 32-bit dynamic shift register for signal <dout<60>>.
	Found 32-bit dynamic shift register for signal <dout<61>>.
	Found 32-bit dynamic shift register for signal <dout<62>>.
	Found 32-bit dynamic shift register for signal <dout<63>>.
	Found 32-bit dynamic shift register for signal <dout<64>>.
	Found 32-bit dynamic shift register for signal <dout<65>>.
	Found 32-bit dynamic shift register for signal <dout<66>>.
	Found 32-bit dynamic shift register for signal <dout<67>>.
	Found 32-bit dynamic shift register for signal <dout<68>>.
	Found 32-bit dynamic shift register for signal <dout<69>>.
	Found 32-bit dynamic shift register for signal <dout<70>>.
	Found 32-bit dynamic shift register for signal <dout<71>>.
	Found 32-bit dynamic shift register for signal <dout<72>>.
	Found 32-bit dynamic shift register for signal <dout<73>>.
	Found 32-bit dynamic shift register for signal <dout<74>>.
	Found 32-bit dynamic shift register for signal <dout<75>>.
	Found 32-bit dynamic shift register for signal <dout<76>>.
	Found 32-bit dynamic shift register for signal <dout<77>>.
	Found 32-bit dynamic shift register for signal <dout<78>>.
	Found 32-bit dynamic shift register for signal <dout<79>>.
	Found 32-bit dynamic shift register for signal <dout<80>>.
	Found 32-bit dynamic shift register for signal <dout<81>>.
	Found 32-bit dynamic shift register for signal <dout<82>>.
	Found 32-bit dynamic shift register for signal <dout<83>>.
	Found 32-bit dynamic shift register for signal <dout<84>>.
	Found 32-bit dynamic shift register for signal <dout<85>>.
	Found 32-bit dynamic shift register for signal <dout<86>>.
	Found 32-bit dynamic shift register for signal <dout<87>>.
	Found 32-bit dynamic shift register for signal <dout<88>>.
	Found 32-bit dynamic shift register for signal <dout<89>>.
	Found 32-bit dynamic shift register for signal <dout<90>>.
	Found 32-bit dynamic shift register for signal <dout<91>>.
	Found 32-bit dynamic shift register for signal <dout<92>>.
	Found 32-bit dynamic shift register for signal <dout<93>>.
	Found 32-bit dynamic shift register for signal <dout<94>>.
	Found 32-bit dynamic shift register for signal <dout<95>>.
	Found 32-bit dynamic shift register for signal <dout<96>>.
	Found 32-bit dynamic shift register for signal <dout<97>>.
	Found 32-bit dynamic shift register for signal <dout<98>>.
	Found 32-bit dynamic shift register for signal <dout<99>>.
	Found 32-bit dynamic shift register for signal <dout<100>>.
	Found 32-bit dynamic shift register for signal <dout<101>>.
	Found 32-bit dynamic shift register for signal <dout<102>>.
	Found 32-bit dynamic shift register for signal <dout<103>>.
	Found 32-bit dynamic shift register for signal <dout<104>>.
	Found 32-bit dynamic shift register for signal <dout<105>>.
	Found 32-bit dynamic shift register for signal <dout<106>>.
	Found 32-bit dynamic shift register for signal <dout<107>>.
	Found 32-bit dynamic shift register for signal <dout<108>>.
	Found 32-bit dynamic shift register for signal <dout<109>>.
	Found 32-bit dynamic shift register for signal <dout<110>>.
	Found 32-bit dynamic shift register for signal <dout<111>>.
	Found 32-bit dynamic shift register for signal <dout<112>>.
	Found 32-bit dynamic shift register for signal <dout<113>>.
	Found 32-bit dynamic shift register for signal <dout<114>>.
	Found 32-bit dynamic shift register for signal <dout<115>>.
	Found 32-bit dynamic shift register for signal <dout<116>>.
	Found 32-bit dynamic shift register for signal <dout<117>>.
	Found 32-bit dynamic shift register for signal <dout<118>>.
	Found 32-bit dynamic shift register for signal <dout<119>>.
	Found 32-bit dynamic shift register for signal <dout<120>>.
	Found 32-bit dynamic shift register for signal <dout<121>>.
	Found 32-bit dynamic shift register for signal <dout<122>>.
	Found 32-bit dynamic shift register for signal <dout<123>>.
	Found 32-bit dynamic shift register for signal <dout<124>>.
	Found 32-bit dynamic shift register for signal <dout<125>>.
	Found 32-bit dynamic shift register for signal <dout<126>>.
	Found 32-bit dynamic shift register for signal <dout<127>>.
	Found 32-bit dynamic shift register for signal <dout<128>>.
	Found 32-bit dynamic shift register for signal <dout<129>>.
	Found 32-bit dynamic shift register for signal <dout<130>>.
	Found 32-bit dynamic shift register for signal <dout<131>>.
	Found 32-bit dynamic shift register for signal <dout<132>>.
	Found 32-bit dynamic shift register for signal <dout<133>>.
	Found 32-bit dynamic shift register for signal <dout<134>>.
	Found 32-bit dynamic shift register for signal <dout<135>>.
	Found 32-bit dynamic shift register for signal <dout<136>>.
	Found 32-bit dynamic shift register for signal <dout<137>>.
	Found 32-bit dynamic shift register for signal <dout<138>>.
	Found 32-bit dynamic shift register for signal <dout<139>>.
	Found 32-bit dynamic shift register for signal <dout<140>>.
	Found 32-bit dynamic shift register for signal <dout<141>>.
	Found 32-bit dynamic shift register for signal <dout<142>>.
	Found 32-bit dynamic shift register for signal <dout<143>>.
	Found 32-bit dynamic shift register for signal <dout<144>>.
	Found 32-bit dynamic shift register for signal <dout<145>>.
	Found 32-bit dynamic shift register for signal <dout<146>>.
	Found 32-bit dynamic shift register for signal <dout<147>>.
	Found 32-bit dynamic shift register for signal <dout<148>>.
	Found 32-bit dynamic shift register for signal <dout<149>>.
	Found 32-bit dynamic shift register for signal <dout<150>>.
	Found 32-bit dynamic shift register for signal <dout<151>>.
	Found 32-bit dynamic shift register for signal <dout<152>>.
	Found 32-bit dynamic shift register for signal <dout<153>>.
	Found 32-bit dynamic shift register for signal <dout<154>>.
	Found 32-bit dynamic shift register for signal <dout<155>>.
	Found 32-bit dynamic shift register for signal <dout<156>>.
	Found 32-bit dynamic shift register for signal <dout<157>>.
	Found 32-bit dynamic shift register for signal <dout<158>>.
	Found 32-bit dynamic shift register for signal <dout<159>>.
	Found 32-bit dynamic shift register for signal <dout<160>>.
	Found 32-bit dynamic shift register for signal <dout<161>>.
	Found 32-bit dynamic shift register for signal <dout<162>>.
	Found 32-bit dynamic shift register for signal <dout<163>>.
	Found 32-bit dynamic shift register for signal <dout<164>>.
	Found 32-bit dynamic shift register for signal <dout<165>>.
	Found 32-bit dynamic shift register for signal <dout<166>>.
	Found 32-bit dynamic shift register for signal <dout<167>>.
	Found 32-bit dynamic shift register for signal <dout<168>>.
	Found 32-bit dynamic shift register for signal <dout<169>>.
	Found 32-bit dynamic shift register for signal <dout<170>>.
	Found 32-bit dynamic shift register for signal <dout<171>>.
	Found 32-bit dynamic shift register for signal <dout<172>>.
	Found 32-bit dynamic shift register for signal <dout<173>>.
	Found 32-bit dynamic shift register for signal <dout<174>>.
	Found 32-bit dynamic shift register for signal <dout<175>>.
	Found 32-bit dynamic shift register for signal <dout<176>>.
	Found 32-bit dynamic shift register for signal <dout<177>>.
	Found 32-bit dynamic shift register for signal <dout<178>>.
	Found 32-bit dynamic shift register for signal <dout<179>>.
	Found 32-bit dynamic shift register for signal <dout<180>>.
	Found 32-bit dynamic shift register for signal <dout<181>>.
	Found 32-bit dynamic shift register for signal <dout<182>>.
	Found 32-bit dynamic shift register for signal <dout<183>>.
	Found 32-bit dynamic shift register for signal <dout<184>>.
	Found 32-bit dynamic shift register for signal <dout<185>>.
	Found 32-bit dynamic shift register for signal <dout<186>>.
	Found 32-bit dynamic shift register for signal <dout<187>>.
	Found 32-bit dynamic shift register for signal <dout<188>>.
	Found 32-bit dynamic shift register for signal <dout<189>>.
	Found 32-bit dynamic shift register for signal <dout<190>>.
	Found 32-bit dynamic shift register for signal <dout<191>>.
	Found 32-bit dynamic shift register for signal <dout<192>>.
	Found 32-bit dynamic shift register for signal <dout<193>>.
	Found 32-bit dynamic shift register for signal <dout<194>>.
	Found 32-bit dynamic shift register for signal <dout<195>>.
	Found 32-bit dynamic shift register for signal <dout<196>>.
	Found 32-bit dynamic shift register for signal <dout<197>>.
	Found 32-bit dynamic shift register for signal <dout<198>>.
	Found 32-bit dynamic shift register for signal <dout<199>>.
	Found 32-bit dynamic shift register for signal <dout<200>>.
	Found 32-bit dynamic shift register for signal <dout<201>>.
	Found 32-bit dynamic shift register for signal <dout<202>>.
	Found 32-bit dynamic shift register for signal <dout<203>>.
	Found 32-bit dynamic shift register for signal <dout<204>>.
	Found 32-bit dynamic shift register for signal <dout<205>>.
	Found 32-bit dynamic shift register for signal <dout<206>>.
	Found 32-bit dynamic shift register for signal <dout<207>>.
	Found 32-bit dynamic shift register for signal <dout<208>>.
	Found 32-bit dynamic shift register for signal <dout<209>>.
	Found 32-bit dynamic shift register for signal <dout<210>>.
	Found 32-bit dynamic shift register for signal <dout<211>>.
	Found 32-bit dynamic shift register for signal <dout<212>>.
	Found 32-bit dynamic shift register for signal <dout<213>>.
	Found 32-bit dynamic shift register for signal <dout<214>>.
	Found 32-bit dynamic shift register for signal <dout<215>>.
	Found 32-bit dynamic shift register for signal <dout<216>>.
	Found 32-bit dynamic shift register for signal <dout<217>>.
	Found 32-bit dynamic shift register for signal <dout<218>>.
	Found 32-bit dynamic shift register for signal <dout<219>>.
	Found 32-bit dynamic shift register for signal <dout<220>>.
	Found 32-bit dynamic shift register for signal <dout<221>>.
	Found 32-bit dynamic shift register for signal <dout<222>>.
	Found 32-bit dynamic shift register for signal <dout<223>>.
	Found 32-bit dynamic shift register for signal <dout<224>>.
	Found 32-bit dynamic shift register for signal <dout<225>>.
	Found 32-bit dynamic shift register for signal <dout<226>>.
	Found 32-bit dynamic shift register for signal <dout<227>>.
	Found 32-bit dynamic shift register for signal <dout<228>>.
	Found 32-bit dynamic shift register for signal <dout<229>>.
	Found 32-bit dynamic shift register for signal <dout<230>>.
	Found 32-bit dynamic shift register for signal <dout<231>>.
	Found 32-bit dynamic shift register for signal <dout<232>>.
	Found 32-bit dynamic shift register for signal <dout<233>>.
	Found 32-bit dynamic shift register for signal <dout<234>>.
	Found 32-bit dynamic shift register for signal <dout<235>>.
	Found 32-bit dynamic shift register for signal <dout<236>>.
	Found 32-bit dynamic shift register for signal <dout<237>>.
	Found 32-bit dynamic shift register for signal <dout<238>>.
	Found 32-bit dynamic shift register for signal <dout<239>>.
	Found 32-bit dynamic shift register for signal <dout<240>>.
	Found 32-bit dynamic shift register for signal <dout<241>>.
	Found 32-bit dynamic shift register for signal <dout<242>>.
	Found 32-bit dynamic shift register for signal <dout<243>>.
	Found 32-bit dynamic shift register for signal <dout<244>>.
	Found 32-bit dynamic shift register for signal <dout<245>>.
	Found 32-bit dynamic shift register for signal <dout<246>>.
	Found 32-bit dynamic shift register for signal <dout<247>>.
	Found 32-bit dynamic shift register for signal <dout<248>>.
	Found 32-bit dynamic shift register for signal <dout<249>>.
	Found 32-bit dynamic shift register for signal <dout<250>>.
	Found 32-bit dynamic shift register for signal <dout<251>>.
	Found 32-bit dynamic shift register for signal <dout<252>>.
	Found 32-bit dynamic shift register for signal <dout<253>>.
	Found 32-bit dynamic shift register for signal <dout<254>>.
	Found 32-bit dynamic shift register for signal <dout<255>>.
	Found 32-bit dynamic shift register for signal <dout<256>>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_3> synthesized (advanced).

Synthesizing (advanced) Unit <mig_7series_v1_8_axi_mc_simple_fifo_4>.
	Found 32-bit dynamic shift register for signal <dout<0>>.
	Found 32-bit dynamic shift register for signal <dout<1>>.
	Found 32-bit dynamic shift register for signal <dout<2>>.
	Found 32-bit dynamic shift register for signal <dout<3>>.
	Found 32-bit dynamic shift register for signal <dout<4>>.
	Found 32-bit dynamic shift register for signal <dout<5>>.
	Found 32-bit dynamic shift register for signal <dout<6>>.
Unit <mig_7series_v1_8_axi_mc_simple_fifo_4> synthesized (advanced).
WARNING:Xst:2677 - Node <ctl_lane_sel_2> of sequential type is unconnected in block <mig_7series_v1_8_ddr_calib_top>.
WARNING:Xst:2677 - Node <pb_found_edge_last_r_1> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <pb_found_edge_last_r_2> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <pb_found_edge_last_r_3> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <pb_found_edge_last_r_4> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <pb_found_edge_last_r_5> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <pb_found_edge_last_r_6> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <pb_found_edge_last_r_7> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <rd_mux_sel_r_2> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_prbs_rdlvl>.
WARNING:Xst:2677 - Node <mux_sel_r_2> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_oclkdelay_cal>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_6> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_7> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_8> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_9> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_10> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_11> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_12> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_13> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <wrcal_start_dly_r_14> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_6> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_7> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_8> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_9> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_10> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_11> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_12> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_13> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <oclkdelay_start_dly_r_14> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <rclk_delay_12> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_13> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_14> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_15> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_16> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_17> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_18> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_19> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_20> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_21> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_22> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_23> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_24> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_25> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_26> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_27> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_28> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_29> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_30> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_1>.
WARNING:Xst:2677 - Node <rclk_delay_12> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_13> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_14> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_15> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_16> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_17> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_18> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_19> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_20> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_21> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_22> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_23> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_24> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_25> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_26> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_27> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_28> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_29> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <rclk_delay_30> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_4lanes_2>.
WARNING:Xst:2677 - Node <trans_buf_out_r_1> of sequential type is unconnected in block <mig_7series_v1_8_axi_mc_r_channel>.
WARNING:Xst:2677 - Node <app_addr_r1_28> of sequential type is unconnected in block <mig_7series_v1_8_ui_cmd>.
WARNING:Xst:2677 - Node <app_addr_r2_28> of sequential type is unconnected in block <mig_7series_v1_8_ui_cmd>.
WARNING:Xst:2677 - Node <addr_r_0> of sequential type is unconnected in block <mig_7series_v1_8_axi4_wrapper>.
WARNING:Xst:2677 - Node <addr_r_1> of sequential type is unconnected in block <mig_7series_v1_8_axi4_wrapper>.
WARNING:Xst:2677 - Node <addr_r_2> of sequential type is unconnected in block <mig_7series_v1_8_axi4_wrapper>.
WARNING:Xst:2677 - Node <addr_r_3> of sequential type is unconnected in block <mig_7series_v1_8_axi4_wrapper>.
WARNING:Xst:2677 - Node <delay_cntr_0> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_1> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_2> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_3> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_4> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_5> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_6> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_7> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_8> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_9> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_10> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_11> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_12> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_13> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_14> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_15> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_16> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_17> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_18> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_19> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_20> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <delay_cntr_21> of sequential type is unconnected in block <mig_7series_v1_8_chk_win>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_36> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_37> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_38> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_39> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_40> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_41> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_42> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_43> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_44> of sequential type is unconnected in block <example_top>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 5
 4x3-bit single-port distributed Read Only RAM         : 1
 4x80-bit dual-port distributed RAM                    : 4
# MACs                                                 : 1
 4x3-to-5-bit MAC                                      : 1
# Multipliers                                          : 6
 3x2-bit multiplier                                    : 2
 3x3-bit multiplier                                    : 1
 4x2-bit multiplier                                    : 1
 4x3-bit multiplier                                    : 2
# Adders/Subtractors                                   : 343
 1-bit adder                                           : 9
 10-bit adder                                          : 1
 10-bit subtractor                                     : 2
 2-bit adder                                           : 24
 2-bit adder carry in                                  : 1
 2-bit addsub                                          : 1
 2-bit subtractor                                      : 26
 3-bit adder                                           : 10
 3-bit addsub                                          : 1
 3-bit subtractor                                      : 6
 32-bit adder                                          : 5
 4-bit adder                                           : 6
 4-bit adder carry in                                  : 14
 4-bit subtractor                                      : 4
 5-bit adder                                           : 64
 5-bit adder carry in                                  : 70
 5-bit addsub                                          : 2
 5-bit subtractor                                      : 6
 6-bit adder                                           : 24
 6-bit adder carry in                                  : 1
 6-bit addsub                                          : 2
 6-bit subtractor                                      : 22
 7-bit adder                                           : 8
 7-bit addsub                                          : 1
 7-bit subtractor                                      : 16
 8-bit adder                                           : 15
 8-bit subtractor                                      : 1
 9-bit subtractor                                      : 1
# Adder Trees                                          : 1
 2-bit / 5-inputs adder tree                           : 1
# Counters                                             : 130
 1-bit up counter                                      : 6
 10-bit up counter                                     : 3
 11-bit up counter                                     : 3
 12-bit up counter                                     : 5
 14-bit up counter                                     : 1
 2-bit down counter                                    : 7
 2-bit up counter                                      : 12
 20-bit down counter                                   : 1
 3-bit down counter                                    : 5
 3-bit up counter                                      : 16
 3-bit updown counter                                  : 1
 4-bit down counter                                    : 8
 4-bit up counter                                      : 15
 4-bit updown counter                                  : 1
 5-bit down counter                                    : 3
 5-bit up counter                                      : 8
 5-bit updown counter                                  : 7
 6-bit down counter                                    : 10
 6-bit up counter                                      : 2
 6-bit updown counter                                  : 1
 7-bit up counter                                      : 2
 8-bit down counter                                    : 3
 8-bit up counter                                      : 6
 9-bit down counter                                    : 1
 9-bit up counter                                      : 2
 9-bit updown counter                                  : 1
# Accumulators                                         : 1
 5-bit updown accumulator                              : 1
# Registers                                            : 16185
 Flip-Flops                                            : 16185
# Shift Registers                                      : 556
 32-bit dynamic shift register                         : 264
 4-bit dynamic shift register                          : 4
 8-bit dynamic shift register                          : 288
# Comparators                                          : 497
 1-bit comparator equal                                : 210
 12-bit comparator greater                             : 16
 12-bit comparator not equal                           : 1
 15-bit comparator equal                               : 4
 2-bit comparator equal                                : 8
 2-bit comparator greater                              : 1
 2-bit comparator lessequal                            : 4
 3-bit comparator equal                                : 6
 3-bit comparator greater                              : 17
 3-bit comparator lessequal                            : 13
 32-bit comparator equal                               : 1
 32-bit comparator greater                             : 1
 32-bit comparator lessequal                           : 5
 4-bit comparator equal                                : 14
 4-bit comparator greater                              : 9
 4-bit comparator lessequal                            : 1
 4-bit comparator not equal                            : 1
 5-bit comparator equal                                : 4
 5-bit comparator greater                              : 9
 5-bit comparator lessequal                            : 39
 6-bit comparator greater                              : 31
 6-bit comparator lessequal                            : 19
 6-bit comparator not equal                            : 4
 64-bit comparator not equal                           : 1
 7-bit comparator equal                                : 1
 7-bit comparator lessequal                            : 16
 8-bit comparator greater                              : 4
 8-bit comparator lessequal                            : 16
 8-bit comparator not equal                            : 24
 9-bit comparator greater                              : 3
 9-bit comparator lessequal                            : 14
# Multiplexers                                         : 3681
 1-bit 2-to-1 multiplexer                              : 2667
 1-bit 3-to-1 multiplexer                              : 3
 1-bit 32-to-1 multiplexer                             : 256
 1-bit 4-to-1 multiplexer                              : 27
 1-bit 9-to-1 multiplexer                              : 1
 12-bit 2-to-1 multiplexer                             : 9
 128-bit 2-to-1 multiplexer                            : 2
 15-bit 2-to-1 multiplexer                             : 14
 15-bit 4-to-1 multiplexer                             : 1
 17-bit 2-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 94
 2-bit 4-to-1 multiplexer                              : 3
 20-bit 2-to-1 multiplexer                             : 3
 22-bit 2-to-1 multiplexer                             : 22
 24-bit 2-to-1 multiplexer                             : 7
 29-bit 2-to-1 multiplexer                             : 1
 3-bit 2-to-1 multiplexer                              : 121
 3-bit 4-to-1 multiplexer                              : 5
 32-bit 2-to-1 multiplexer                             : 51
 4-bit 2-to-1 multiplexer                              : 63
 42-bit 2-to-1 multiplexer                             : 2
 44-bit 2-to-1 multiplexer                             : 1
 44-bit 8-to-1 multiplexer                             : 1
 5-bit 2-to-1 multiplexer                              : 58
 5-bit 4-to-1 multiplexer                              : 1
 5-bit 7-to-1 multiplexer                              : 2
 5-bit 8-to-1 multiplexer                              : 1
 6-bit 2-to-1 multiplexer                              : 180
 6-bit 3-to-1 multiplexer                              : 2
 6-bit 4-to-1 multiplexer                              : 5
 60-bit 2-to-1 multiplexer                             : 1
 64-bit 2-to-1 multiplexer                             : 1
 7-bit 2-to-1 multiplexer                              : 5
 8-bit 2-to-1 multiplexer                              : 20
 8-bit 7-to-1 multiplexer                              : 2
 8-bit 8-to-1 multiplexer                              : 2
 80-bit 2-to-1 multiplexer                             : 11
 80-bit 9-to-1 multiplexer                             : 7
 9-bit 2-to-1 multiplexer                              : 25
 9-bit 3-to-1 multiplexer                              : 1
 9-bit 4-to-1 multiplexer                              : 2
# Logic shifters                                       : 56
 1-bit shifter logical left                            : 9
 102-bit shifter logical right                         : 2
 14-bit shifter logical right                          : 1
 21-bit shifter logical right                          : 1
 285-bit shifter logical right                         : 1
 286-bit shifter logical right                         : 1
 32-bit shifter logical left                           : 2
 35-bit shifter logical right                          : 1
 384-bit shifter logical right                         : 2
 42-bit shifter logical right                          : 6
 504-bit shifter logical right                         : 24
 51-bit shifter logical right                          : 1
 6-bit shifter logical right                           : 3
 60-bit shifter logical right                          : 2
# FSMs                                                 : 15
# Xors                                                 : 31
 1-bit xor2                                            : 30
 1-bit xor4                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <periodic_rd_rank_r_lcl_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_rank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dlyval_dq_reg_r<0><25>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><25>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><25>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><25>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><24>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><25>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><24>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><24>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><24>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><24>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><23>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><23>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><23>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><23>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><23>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><22>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><22>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><22>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><22>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><22>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><21>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><21>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><21>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><21>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><20>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><20>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><21>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><20>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><20>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><20>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><31>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><31>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><31>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><31>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><30>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><31>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><30>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><30>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><30>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><29>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><30>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><29>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><29>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><29>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><28>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><28>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><29>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><28>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><28>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><27>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><27>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><28>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><27>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><27>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><27>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><26>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><26>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><26>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><26>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><26>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><13>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><14>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><13>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><13>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><12>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><12>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><13>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><12>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><12>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><12>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><11>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><11>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><11>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><11>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><11>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><10>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><10>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><10>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><10>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><9>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><10>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><9>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><9>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><9>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><9>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><8>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><8>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><8>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><8>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><8>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><19>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><19>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><19>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><19>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><19>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><18>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><18>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><18>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><18>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><17>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><18>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><17>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><17>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><17>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><16>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><13>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><14>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><14>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><15>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><14>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><14>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><15>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><15>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><16>_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><15>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><15>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><16>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><16>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><16>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r<0><17>_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_115> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_116> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_117> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_118> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_119> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_120> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_121> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_122> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_123> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_124> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_125> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_126> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_127> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_128> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_129> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_114> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_113> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_112> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_111> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_110> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_109> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_108> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_107> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_106> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_105> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_104> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_103> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_102> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_101> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_100> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_159> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_158> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_157> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_156> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_155> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_154> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_153> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_152> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_151> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_150> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_149> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_148> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_147> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_146> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_145> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_144> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_143> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_142> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_141> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_140> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_139> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_138> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_137> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_136> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_135> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_134> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_133> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_132> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_131> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_130> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_69> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_68> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_67> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_66> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_65> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_64> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_63> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_62> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_61> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_60> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_59> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_58> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_57> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_56> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_55> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_54> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_53> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_52> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_51> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_50> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_49> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_48> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_47> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_46> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_45> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_44> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_43> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_42> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_41> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_40> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_99> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_98> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_97> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_96> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_95> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_94> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_93> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_92> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_91> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_90> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_89> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_88> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_87> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_86> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_85> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_84> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_83> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_82> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_81> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_80> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_79> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_78> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_77> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_76> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_75> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_74> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_73> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_72> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_70> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ocal_if_rst> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_oclkdelay_cal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <no_po_fine_taps_left_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <no_po_fine_taps_left_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <no_po_fine_taps_left_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <no_po_fine_taps_left_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dqs_wcal_po_en_stg2_f_r> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dqs_po_en_stg2_c_r> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dqs_po_en_stg2_c> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dqs_wcal_po_en_stg2_f> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <phy_int_cs_n_3> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_int_cs_n_2> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_int_cs_n_0> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <extend_cal_pat> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_done> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_10> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_9> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_8> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tg_timer_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <temp_wrcal_done_r> is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:1710 - FF/Latch <rst_auxout_r> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rst_auxout_rr> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rst_auxout> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <aux_out_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <USE_REGISTER.M_AXI_AUSER_q_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_a_upsizer_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <USE_REGISTER.M_AXI_AUSER_q_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_a_upsizer_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmd_err> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr1_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr1_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr1_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr1_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr2_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr2_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr2_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr2_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <lfsr_q_29> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_31> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_30> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_26> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_28> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_27> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_23> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_25> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_32> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_22> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <lfsr_q_21> (without init value) has a constant value of 0 in block <mig_7series_v1_8_cmd_prbs_gen_axi_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <delay_cntr_22> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <delay_cntr_23> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <delay_cntr_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <calib_zero_ctrl_0> in Unit <mig_7series_v1_8_ddr_calib_top> is equivalent to the following FF/Latch, which will be removed : <calib_zero_ctrl_1> 
INFO:Xst:2261 - The FF/Latch <calib_cke_0> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <calib_cke_1> <calib_cke_2> <calib_cke_3> 
INFO:Xst:2261 - The FF/Latch <axi_wd_strb_0> in Unit <mig_7series_v1_8_axi4_wrapper> is equivalent to the following 15 FFs/Latches, which will be removed : <axi_wd_strb_1> <axi_wd_strb_2> <axi_wd_strb_3> <axi_wd_strb_4> <axi_wd_strb_5> <axi_wd_strb_6> <axi_wd_strb_7> <axi_wd_strb_8> <axi_wd_strb_9> <axi_wd_strb_10> <axi_wd_strb_11> <axi_wd_strb_12> <axi_wd_strb_13> <axi_wd_strb_14> <axi_wd_strb_15> 
INFO:Xst:2261 - The FF/Latch <ddr3_ila_basic_120> in Unit <example_top> is equivalent to the following 7 FFs/Latches, which will be removed : <ddr3_ila_basic_121> <ddr3_ila_basic_122> <ddr3_ila_basic_123> <ddr3_ila_basic_124> <ddr3_ila_basic_125> <ddr3_ila_basic_126> <ddr3_ila_basic_127> 
INFO:Xst:2261 - The FF/Latch <phy_ctl_wd_i1_3> in Unit <mig_7series_v1_8_ddr_mc_phy_wrapper> is equivalent to the following 18 FFs/Latches, which will be removed : <phy_ctl_wd_i1_4> <phy_ctl_wd_i1_5> <phy_ctl_wd_i1_6> <phy_ctl_wd_i1_7> <phy_ctl_wd_i1_8> <phy_ctl_wd_i1_9> <phy_ctl_wd_i1_10> <phy_ctl_wd_i1_11> <phy_ctl_wd_i1_12> <phy_ctl_wd_i1_13> <phy_ctl_wd_i1_14> <phy_ctl_wd_i1_15> <phy_ctl_wd_i1_16> <phy_ctl_wd_i1_27> <phy_ctl_wd_i1_28> <phy_ctl_wd_i1_29> <phy_ctl_wd_i1_30> <phy_ctl_wd_i1_31> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_71> in Unit <mig_7series_v1_8_ddr_byte_lane_1> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_70> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_69> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_68> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_67> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_66> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_65> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_64> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> in Unit <mig_7series_v1_8_ddr_byte_lane_2> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> in Unit <mig_7series_v1_8_ddr_byte_lane_3> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_0> 
INFO:Xst:2261 - The FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> in Unit <mig_7series_v1_8_ddr_byte_lane_4> is equivalent to the following 7 FFs/Latches, which will be removed : <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_6> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_5> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_3> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_2> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_1> <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_0> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/ofifo_rst> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 2 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst> <ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_0> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 71 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_1> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_2> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_3> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_5> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_6> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_8> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_9> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_10>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_11> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_12> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_13> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_14> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_15> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_16> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_17> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_18> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_19> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_20> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_21> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_22>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_23> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_24> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_25> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_26> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_27> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_28> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_29> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_30> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_31> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_32> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_33> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_34>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_35> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_36> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_37> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_38> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_39> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_40> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_41> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_42> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_43> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_48> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_49> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_50>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_51> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_56> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_57> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_58> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_59> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_60> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_61> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_62> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_63> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_64> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_65> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_66>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_67> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_68> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_69> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_70> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_71> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_72> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_73> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_74> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_75> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_76> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_77> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_78>
   <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_79>
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 31 FFs/Latches, which will be removed : <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_5> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_6> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_12> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_13> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_14> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_15> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_20> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_21> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_22>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_23> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_28> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_29> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_30> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_31> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_36> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_37> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_38> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_39> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_60> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_61> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_62>
   <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_63> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_68> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_69> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_70> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_71> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_76> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_77> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_78> <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 39 FFs/Latches, which will be removed : <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_5> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_6> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_12> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_13> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_14> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_15> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_20> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_21> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_22>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_23> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_28> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_29> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_30> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_31> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_36> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_37> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_38> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_39> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_44> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_45> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_46>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_47> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_52> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_53> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_54> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_55> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_60> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_61> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_62> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_63> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_68> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_69> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_70>
   <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_71> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_76> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_77> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_78> <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_79> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_47> 
INFO:Xst:2261 - The FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_44> in Unit <mig_7series_v1_8_ddr_phy_4lanes_2> is equivalent to the following 3 FFs/Latches, which will be removed : <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_45> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_46> <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_47> 
INFO:Xst:2261 - The FF/Latch <_o25850_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25850_4> <_o25850_5> <_o25850_6> <_o25850_7> <_o25850_8> <_o25850_9> <_o25850_10> <_o25850_11> <_o25850_12> <_o25850_13> <_o25850_14> <_o25850_15> <_o25850_16> <_o25850_27> <_o25850_28> <_o25850_29> <_o25850_30> <_o25850_31> 
INFO:Xst:2261 - The FF/Latch <_o25844_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25844_4> <_o25844_5> <_o25844_6> <_o25844_7> <_o25844_8> <_o25844_9> <_o25844_10> <_o25844_11> <_o25844_12> <_o25844_13> <_o25844_14> <_o25844_15> <_o25844_16> <_o25844_27> <_o25844_28> <_o25844_29> <_o25844_30> <_o25844_31> 
INFO:Xst:2261 - The FF/Latch <_o25852_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25852_4> <_o25852_5> <_o25852_6> <_o25852_7> <_o25852_8> <_o25852_9> <_o25852_10> <_o25852_11> <_o25852_12> <_o25852_13> <_o25852_14> <_o25852_15> <_o25852_16> <_o25852_27> <_o25852_28> <_o25852_29> <_o25852_30> <_o25852_31> 
INFO:Xst:2261 - The FF/Latch <_o25846_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25846_4> <_o25846_5> <_o25846_6> <_o25846_7> <_o25846_8> <_o25846_9> <_o25846_10> <_o25846_11> <_o25846_12> <_o25846_13> <_o25846_14> <_o25846_15> <_o25846_16> <_o25846_27> <_o25846_28> <_o25846_29> <_o25846_30> <_o25846_31> 
INFO:Xst:2261 - The FF/Latch <_o25840_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25840_4> <_o25840_5> <_o25840_6> <_o25840_7> <_o25840_8> <_o25840_9> <_o25840_10> <_o25840_11> <_o25840_12> <_o25840_13> <_o25840_14> <_o25840_15> <_o25840_16> <_o25840_27> <_o25840_28> <_o25840_29> <_o25840_30> <_o25840_31> 
INFO:Xst:2261 - The FF/Latch <_o25854_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25854_4> <_o25854_5> <_o25854_6> <_o25854_7> <_o25854_8> <_o25854_9> <_o25854_10> <_o25854_11> <_o25854_12> <_o25854_13> <_o25854_14> <_o25854_15> <_o25854_16> <_o25854_27> <_o25854_28> <_o25854_29> <_o25854_30> <_o25854_31> 
INFO:Xst:2261 - The FF/Latch <_o25848_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25848_4> <_o25848_5> <_o25848_6> <_o25848_7> <_o25848_8> <_o25848_9> <_o25848_10> <_o25848_11> <_o25848_12> <_o25848_13> <_o25848_14> <_o25848_15> <_o25848_16> <_o25848_27> <_o25848_28> <_o25848_29> <_o25848_30> <_o25848_31> 
INFO:Xst:2261 - The FF/Latch <_o25842_3> in Unit <mig_7series_v1_8_ddr_of_pre_fifo_1> is equivalent to the following 18 FFs/Latches, which will be removed : <_o25842_4> <_o25842_5> <_o25842_6> <_o25842_7> <_o25842_8> <_o25842_9> <_o25842_10> <_o25842_11> <_o25842_12> <_o25842_13> <_o25842_14> <_o25842_15> <_o25842_16> <_o25842_27> <_o25842_28> <_o25842_29> <_o25842_30> <_o25842_31> 
INFO:Xst:2261 - The FF/Latch <curr_addr2_24> in Unit <mig_7series_v1_8_tg> is equivalent to the following 7 FFs/Latches, which will be removed : <curr_addr2_25> <curr_addr2_26> <curr_addr2_27> <curr_addr2_28> <curr_addr2_29> <curr_addr2_30> <curr_addr2_31> 
INFO:Xst:2261 - The FF/Latch <curr_addr1_24> in Unit <mig_7series_v1_8_tg> is equivalent to the following 7 FFs/Latches, which will be removed : <curr_addr1_25> <curr_addr1_26> <curr_addr1_27> <curr_addr1_28> <curr_addr1_29> <curr_addr1_30> <curr_addr1_31> 
WARNING:Xst:2677 - Node <periodic_read_request.periodic_rd_arb0/grant_r_0> of sequential type is unconnected in block <mig_7series_v1_8_rank_common>.
WARNING:Xst:1293 - FF/Latch <app_ref_r> has a constant value of 0 in block <mig_7series_v1_8_rank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <app_ref_ack_r> has a constant value of 0 in block <mig_7series_v1_8_rank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <app_zq_r> has a constant value of 0 in block <mig_7series_v1_8_rank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <app_zq_ack_r> has a constant value of 0 in block <mig_7series_v1_8_rank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sr_cntrl.sre_request_logic.sre_request_r> (without init value) has a constant value of 0 in block <mig_7series_v1_8_rank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <po_dec_done> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <phy_wrdata_97> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_105> <phy_wrdata_113> <phy_wrdata_121> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_229> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_237> <phy_wrdata_245> <phy_wrdata_253> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_32> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_40> <phy_wrdata_48> <phy_wrdata_56> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_98> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_106> <phy_wrdata_114> <phy_wrdata_122> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_33> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_41> <phy_wrdata_49> <phy_wrdata_57> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_99> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_107> <phy_wrdata_115> <phy_wrdata_123> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_34> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_42> <phy_wrdata_50> <phy_wrdata_58> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_192> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_200> <phy_wrdata_208> <phy_wrdata_216> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_35> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_43> <phy_wrdata_51> <phy_wrdata_59> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_193> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_201> <phy_wrdata_209> <phy_wrdata_217> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_36> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_44> <phy_wrdata_52> <phy_wrdata_60> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_194> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_202> <phy_wrdata_210> <phy_wrdata_218> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_37> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_45> <phy_wrdata_53> <phy_wrdata_61> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_195> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_203> <phy_wrdata_211> <phy_wrdata_219> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_38> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_46> <phy_wrdata_54> <phy_wrdata_62> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_196> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_204> <phy_wrdata_212> <phy_wrdata_220> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_39> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_47> <phy_wrdata_55> <phy_wrdata_63> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_197> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_205> <phy_wrdata_213> <phy_wrdata_221> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_198> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_206> <phy_wrdata_214> <phy_wrdata_222> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_130> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_138> <phy_wrdata_146> <phy_wrdata_154> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_199> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_207> <phy_wrdata_215> <phy_wrdata_223> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_131> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_139> <phy_wrdata_147> <phy_wrdata_155> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_132> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_140> <phy_wrdata_148> <phy_wrdata_156> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_0> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_8> <phy_wrdata_16> <phy_wrdata_24> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_128> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_136> <phy_wrdata_144> <phy_wrdata_152> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_133> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_141> <phy_wrdata_149> <phy_wrdata_157> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_129> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_137> <phy_wrdata_145> <phy_wrdata_153> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_134> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_142> <phy_wrdata_150> <phy_wrdata_158> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_135> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_143> <phy_wrdata_151> <phy_wrdata_159> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_64> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_72> <phy_wrdata_80> <phy_wrdata_88> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_65> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_73> <phy_wrdata_81> <phy_wrdata_89> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_70> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_78> <phy_wrdata_86> <phy_wrdata_94> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_66> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_74> <phy_wrdata_82> <phy_wrdata_90> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_71> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_79> <phy_wrdata_87> <phy_wrdata_95> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_67> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_75> <phy_wrdata_83> <phy_wrdata_91> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_68> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_76> <phy_wrdata_84> <phy_wrdata_92> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_69> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_77> <phy_wrdata_85> <phy_wrdata_93> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_160> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_168> <phy_wrdata_176> <phy_wrdata_184> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_161> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_169> <phy_wrdata_177> <phy_wrdata_185> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_162> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_170> <phy_wrdata_178> <phy_wrdata_186> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_2> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_10> <phy_wrdata_18> <phy_wrdata_26> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_163> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_171> <phy_wrdata_179> <phy_wrdata_187> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_3> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_11> <phy_wrdata_19> <phy_wrdata_27> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_164> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_172> <phy_wrdata_180> <phy_wrdata_188> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_4> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_12> <phy_wrdata_20> <phy_wrdata_28> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_165> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_173> <phy_wrdata_181> <phy_wrdata_189> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_5> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_13> <phy_wrdata_21> <phy_wrdata_29> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_166> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_174> <phy_wrdata_182> <phy_wrdata_190> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_6> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_14> <phy_wrdata_22> <phy_wrdata_30> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_167> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_175> <phy_wrdata_183> <phy_wrdata_191> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_7> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_15> <phy_wrdata_23> <phy_wrdata_31> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_100> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_108> <phy_wrdata_116> <phy_wrdata_124> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_224> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_232> <phy_wrdata_240> <phy_wrdata_248> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_1> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_9> <phy_wrdata_17> <phy_wrdata_25> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_101> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_109> <phy_wrdata_117> <phy_wrdata_125> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_225> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_233> <phy_wrdata_241> <phy_wrdata_249> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_230> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_238> <phy_wrdata_246> <phy_wrdata_254> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_102> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_110> <phy_wrdata_118> <phy_wrdata_126> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_226> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_234> <phy_wrdata_242> <phy_wrdata_250> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_231> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_239> <phy_wrdata_247> <phy_wrdata_255> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_103> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_111> <phy_wrdata_119> <phy_wrdata_127> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_227> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_235> <phy_wrdata_243> <phy_wrdata_251> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_96> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_104> <phy_wrdata_112> <phy_wrdata_120> 
INFO:Xst:2261 - The FF/Latch <phy_wrdata_228> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following 3 FFs/Latches, which will be removed : <phy_wrdata_236> <phy_wrdata_244> <phy_wrdata_252> 
WARNING:Xst:1710 - FF/Latch <phy_ctl_wd_i1_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_31> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_30> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_29> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_28> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_27> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_16> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_15> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_14> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_10> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_9> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_8> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_ctl_wd_i2_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_mc_phy_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_71> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_byte_lane_4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <_o25844_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <_o25840_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <_o25842_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <_o25846_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <_o25848_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <_o25854_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <_o25850_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <_o25852_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_of_pre_fifo_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <curr_addr1_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <curr_addr2_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/cmptd_one_wr> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/cmptd_one_rd> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/cmptd_one_wr_rd> of sequential type is unconnected in block <example_top>.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/FSM_5> on signal <fine_adj_state_r[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0011  | 0011
 0010  | 0010
 0100  | 0100
 0001  | 0001
 1111  | 1111
 1101  | 1101
 0101  | 0101
 0110  | 0110
 1000  | 1000
 0111  | 0111
 1001  | 1001
 1011  | 1011
 1010  | 1010
 1100  | 1100
 1110  | 1110
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/FSM_6> on signal <cal1_state_r[1:22]> with one-hot encoding.
----------------------------------
 State  | Encoding
----------------------------------
 000000 | 0000000000000000000001
 000001 | 0000000000000000000010
 011101 | 0000000000000000000100
 000010 | 0000000000000000001000
 001100 | 0000000000000000010000
 000011 | 0000000000000000100000
 011100 | 0000000000000001000000
 000100 | 0000000000000010000000
 001000 | 0000000000000100000000
 000101 | 0000000000001000000000
 011111 | 0000000000010000000000
 000111 | 0000000000100000000000
 000110 | 0000000001000000000000
 001001 | 0000000010000000000000
 001011 | 0000000100000000000000
 001010 | 0000001000000000000000
 001101 | 0000010000000000000000
 001110 | 0000100000000000000000
 100000 | 0001000000000000000000
 011011 | 0010000000000000000000
 001111 | 0100000000000000000000
 010001 | unreached
 011001 | unreached
 010010 | unreached
 010100 | unreached
 010011 | unreached
 010101 | unreached
 010110 | unreached
 010111 | unreached
 011000 | unreached
 011010 | unreached
 011110 | 1000000000000000000000
----------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/FSM_7> on signal <prbs_state_r[1:6]> with user encoding.
--------------------
 State  | Encoding
--------------------
 000000 | 000000
 000001 | 000001
 000010 | 000010
 000011 | 000011
 000101 | 000101
 000111 | 000111
 000100 | 000100
 001000 | 001000
 000110 | 000110
 001001 | 001001
 001010 | 001010
--------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/FSM_3> on signal <wl_state_r[1:27]> with one-hot encoding.
--------------------------------------
 State | Encoding
--------------------------------------
 00000 | 000000000000000000000000001
 00001 | 000000000000000000000000010
 00010 | 000000000000000000000000100
 10000 | 000000000000000000000001000
 01110 | 000000000000000000000010000
 00011 | 000000000000000000000100000
 00100 | 000000000000000000001000000
 00101 | 000000000000000000010000000
 01000 | 000000000000000000100000000
 11001 | 000000000000000001000000000
 10111 | 000000000000000010000000000
 01001 | 000000000000000100000000000
 00111 | 000000000000001000000000000
 01011 | 000000000000010000000000000
 01010 | 000000000000100000000000000
 11010 | 000000000001000000000000000
 01101 | 000000000010000000000000000
 10100 | 000000000100000000000000000
 11011 | 000000001000000000000000000
 11000 | 000000010000000000000000000
 10010 | 000000100000000000000000000
 10011 | 000001000000000000000000000
 10101 | 000010000000000000000000000
 10110 | 000100000000000000000000000
 00110 | 001000000000000000000000000
 01111 | 010000000000000000000000000
 10001 | 100000000000000000000000000
--------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/FSM_4> on signal <ocal_state_r[1:21]> with one-hot encoding.
--------------------------------
 State | Encoding
--------------------------------
 00000 | 000000000000000000001
 00001 | 000000000000000000010
 00111 | 000000000000000000100
 00010 | 000000000000000001000
 00011 | 000000000000000010000
 00100 | 000000000000000100000
 00101 | 000000000000001000000
 01000 | 000000000000010000000
 00110 | 000000000000100000000
 10011 | 000000000001000000000
 10010 | 000000000010000000000
 01010 | 000000000100000000000
 01001 | 000000001000000000000
 10001 | 000000010000000000000
 01011 | 000000100000000000000
 01101 | 000001000000000000000
 01100 | 000010000000000000000
 01111 | 000100000000000000000
 01110 | 001000000000000000000
 10000 | 010000000000000000000
 10100 | 100000000000000000000
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/FSM_2> on signal <cal2_state_r[1:5]> with user encoding.
-------------------
 State | Encoding
-------------------
 00000 | 00000
 00001 | 00001
 01001 | 01001
 11001 | 11001
 11010 | 11010
 00111 | 00111
 00100 | unreached
 00011 | unreached
 00101 | unreached
 00110 | unreached
 01000 | 01000
 01011 | unreached
 01100 | unreached
 01101 | unreached
 10000 | unreached
 01110 | unreached
 01111 | unreached
 10111 | unreached
 10010 | unreached
 10100 | unreached
 10110 | unreached
 10011 | unreached
 10101 | unreached
 10001 | unreached
 11000 | unreached
 11011 | 11011
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/FSM_8> on signal <tempmon_state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 001   | 01
 010   | 10
 011   | 11
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/FSM_1> on signal <init_state_r[1:45]> with one-hot encoding.
---------------------------------------------------------
 State  | Encoding
---------------------------------------------------------
 000000 | 000000000000000000000000000000000000000000001
 000001 | 000000000000000000000000000000000000000000010
 000010 | 000000000000000000000000000000000000000000100
 000011 | 000000000000000000000000000000000000000001000
 000100 | 000000000000000000000000000000000000000010000
 010011 | 000000000000000000000000000000000000000100000
 010100 | 000000000000000000000000000000000000001000000
 000101 | 000000000000000000000000000000000000010000000
 001100 | 000000000000000000000000000000000000100000000
 000111 | 000000000000000000000000000000000001000000000
 001000 | 000000000000000000000000000000000010000000000
 001001 | 000000000000000000000000000000000100000000000
 001010 | 000000000000000000000000000000001000000000000
 001011 | 000000000000000000000000000000010000000000000
 000110 | 000000000000000000000000000000100000000000000
 001101 | 000000000000000000000000000001000000000000000
 010000 | 000000000000000000000000000010000000000000000
 001110 | 000000000000000000000000000100000000000000000
 100000 | 000000000000000000000000001000000000000000000
 010001 | 000000000000000000000000010000000000000000000
 100110 | 000000000000000000000000100000000000000000000
 001111 | 000000000000000000000001000000000000000000000
 010010 | 000000000000000000000010000000000000000000000
 010101 | 000000000000000000000100000000000000000000000
 011001 | 000000000000000000001000000000000000000000000
 100100 | 000000000000000000010000000000000000000000000
 010110 | 000000000000000000100000000000000000000000000
 011000 | unreached
 011010 | 000000000000000001000000000000000000000000000
 011111 | 000000000000000010000000000000000000000000000
 101101 | 000000000000000100000000000000000000000000000
 100111 | 000000000000001000000000000000000000000000000
 011100 | unreached
 011011 | unreached
 011110 | unreached
 010111 | unreached
 100001 | 000000000000010000000000000000000000000000000
 100010 | 000000000000100000000000000000000000000000000
 100011 | 000000000001000000000000000000000000000000000
 100101 | 000000000010000000000000000000000000000000000
 101000 | 000000000100000000000000000000000000000000000
 101001 | 000000001000000000000000000000000000000000000
 101010 | 000000010000000000000000000000000000000000000
 101011 | 000000100000000000000000000000000000000000000
 101100 | 000001000000000000000000000000000000000000000
 101110 | 000010000000000000000000000000000000000000000
 101111 | 000100000000000000000000000000000000000000000
 110000 | 001000000000000000000000000000000000000000000
 110001 | 010000000000000000000000000000000000000000000
 110010 | 100000000000000000000000000000000000000000000
---------------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/aw_cmd_fsm_0/FSM_9> on signal <state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 11    | 10
 10    | 11
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/ar_cmd_fsm_0/FSM_10> on signal <state[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 11    | 11
 10    | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <u_ddr3_interface_fast/temp_mon_enabled.u_mig_7series_v1_8_tempmon/FSM_0> on signal <xadc_supplied_temperature.tempmon_state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 001   | 01
 010   | 11
 011   | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/FSM_14> on signal <rstate[1:3]> with sequential encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 000
 000010 | 001
 010000 | 010
 000100 | 011
 100000 | 100
 001000 | 101
 000000 | unreached
--------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/FSM_13> on signal <wstate[1:9]> with user encoding.
------------------------
 State     | Encoding
------------------------
 000000001 | 000000001
 000000010 | 000000010
 000000100 | 000000100
 100000000 | 100000000
 000001000 | 000001000
 000100000 | 000100000
 000010000 | 000010000
 001000000 | 001000000
 010000000 | 010000000
 000000000 | unreached
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/FSM_15> on signal <tg_state[1:8]> with user encoding.
----------------------
 State    | Encoding
----------------------
 00000001 | 00000001
 00000010 | 00000010
 00100000 | 00100000
 00000100 | 00000100
 00001000 | 00001000
 10000000 | 10000000
 00010000 | 00010000
 01000000 | 01000000
 00000000 | unreached
----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win/FSM_16> on signal <win_state_r[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0010  | 0010
 0011  | 0011
 0001  | 0001
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 1000  | 1000
 1001  | 1001
 1010  | 1010
 1011  | 1011
 1100  | 1100
 1101  | 1101
 1110  | 1110
-------------------
WARNING:Xst:1710 - FF/Latch <cal1_dlyce_dq_r> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <pb_found_edge_last_r_0> is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <found_edge_all_r> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <idel_tap_limit_dq_pb_r> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:2677 - Node <dec_taps> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_wrcal>.
WARNING:Xst:1710 - FF/Latch <calib_odt_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <ddr2_pre_flag_r> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <ddr2_refresh_flag_r> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:1710 - FF/Latch <cmp_data_r_31> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_30> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_29> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_28> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_27> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_26> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_25> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_23> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_22> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_21> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_20> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_19> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_18> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_17> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_16> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_15> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_14> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_10> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_9> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_8> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_63> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_62> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_61> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_60> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_59> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_58> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_57> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_56> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_55> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_54> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_53> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_52> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_51> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_50> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_49> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_48> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_47> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_46> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_45> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_44> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_43> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_42> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_41> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_40> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_39> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_38> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_37> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_36> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_35> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_34> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_33> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_data_r_32> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_31> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_30> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_29> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_28> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_27> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_26> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_25> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_23> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_22> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_21> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_20> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_19> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_18> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_17> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_16> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_15> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_14> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_10> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_9> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_8> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_63> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_62> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_61> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_60> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_59> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_58> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_57> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_56> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_55> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_54> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_53> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_52> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_51> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_50> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_49> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_48> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_47> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_46> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_45> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_44> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_43> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_42> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_41> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_40> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_39> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_38> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_37> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_36> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_35> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_34> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_33> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_data_r_32> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_cmd_r_2> of sequential type is unconnected in block <mig_7series_v1_8_mc>.
WARNING:Xst:2677 - Node <bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_cmd_r_2> of sequential type is unconnected in block <mig_7series_v1_8_mc>.
WARNING:Xst:2677 - Node <bank_mach0/bank_cntrl[2].bank0/bank_compare0/req_cmd_r_2> of sequential type is unconnected in block <mig_7series_v1_8_mc>.
WARNING:Xst:2677 - Node <bank_mach0/bank_cntrl[3].bank0/bank_compare0/req_cmd_r_2> of sequential type is unconnected in block <mig_7series_v1_8_mc>.
WARNING:Xst:1710 - FF/Latch <maint_rank_r_lcl_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_rank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dlyce_dq_r_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_04> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_14> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_34> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_44> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_05> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_15> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_25> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_35> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_45> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_06> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_16> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_26> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_36> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_46> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_07> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_17> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_27> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_37> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_47> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_01> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_21> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_31> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_41> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_02> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_22> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_32> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_42> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_03> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_23> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_33> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_reg_r_43> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_29> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_28> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_27> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_26> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_25> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_23> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_22> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_21> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_20> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_30> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_31> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_32> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_33> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_34> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_35> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_36> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_37> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_38> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_39> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_8> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_9> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_10> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_14> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_15> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_16> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_17> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_18> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dlyval_dq_19> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <dlyinc_dq_r> is unconnected in block <mig_7series_v1_8_ddr_phy_rdlvl>.
WARNING:Xst:1710 - FF/Latch <cal2_po_dly_cnt_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_po_dly_cnt_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_po_dly_cnt_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_po_dly_cnt_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_po_dly_cnt_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_rd_cnt_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_rd_cnt_1> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_rd_cnt_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <po_dec_cnt_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_23> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_21> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_18> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_17> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_15> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_9> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_fine_cnt_3_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index1_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index1_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index1_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index1_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index1_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pass_start_index_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <tmp_mr2_r_3_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tmp_mr2_r_3_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tmp_mr1_r_3_9> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tmp_mr1_r_3_10> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tmp_mr1_r_3_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_bank_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_address_14> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <phy_address_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <mr2_r<0>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <mr2_r<0>_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <mr1_r<0>_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <mr1_r<0>_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <tmp_mr2_r_3_0> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr2_r_3_1> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr2_r_3_2> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr2_r_3_3> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr2_r_3_4> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr2_r_3_5> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_0> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_1> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_2> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_3> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_4> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_5> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_6> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_7> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:2677 - Node <tmp_mr1_r_3_8> of sequential type is unconnected in block <mig_7series_v1_8_ddr_phy_init>.
WARNING:Xst:1710 - FF/Latch <pi_fine_overflow> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_counter_read_val_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_counter_read_val_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_counter_read_val_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_counter_read_val_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_counter_read_val_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_counter_read_val_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_phase_locked> (without init value) has a constant value of 1 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pi_dqs_out_of_range> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_4lanes_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <trans_buf_out_r1_1> of sequential type is unconnected in block <mig_7series_v1_8_axi_mc_r_channel>.
WARNING:Xst:2677 - Node <ax_burst_r_0> of sequential type is unconnected in block <mig_7series_v1_8_axi_mc_cmd_translator>.
WARNING:Xst:1710 - FF/Latch <addr_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_24> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_25> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_26> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_27> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_28> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_29> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_30> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <addr_31> (without init value) has a constant value of 0 in block <mig_7series_v1_8_tg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <walk0_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_data_gen_chk>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <error_dqs> (without init value) has a constant value of 0 in block <mig_7series_v1_8_chk_win>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <read_valid_r> is unconnected in block <mig_7series_v1_8_chk_win>.
INFO:Xst:1901 - Instance u_bufh_auxout_clk in unit mig_7series_v1_8_infrastructure of type BUFH has been replaced by BUFHCE
INFO:Xst:2261 - The FF/Latch <lfsr_q_1> in Unit <mig_7series_v1_8_ddr_prbs_gen> is equivalent to the following FF/Latch, which will be removed : <lfsr_q_33> 
INFO:Xst:2261 - The FF/Latch <phy_tmp_odt_r> in Unit <mig_7series_v1_8_ddr_phy_init> is equivalent to the following FF/Latch, which will be removed : <mr1_r<0>_0> 

Optimizing unit <mig_7series_v1_8_ddr_byte_group_io_4> ...

Optimizing unit <mig_7series_v1_8_ddr_byte_group_io_5> ...

Optimizing unit <example_top> ...

Optimizing unit <ddr3_interface_fast> ...

Optimizing unit <mig_7series_v1_8_mc> ...

Optimizing unit <mig_7series_v1_8_rank_cntrl> ...

Optimizing unit <mig_7series_v1_8_rank_common> ...

Optimizing unit <mig_7series_v1_8_round_robin_arb_1> ...

Optimizing unit <mig_7series_v1_8_bank_state_1> ...

Optimizing unit <mig_7series_v1_8_bank_queue_1> ...

Optimizing unit <mig_7series_v1_8_bank_state_2> ...

Optimizing unit <mig_7series_v1_8_bank_queue_2> ...

Optimizing unit <mig_7series_v1_8_bank_state_3> ...

Optimizing unit <mig_7series_v1_8_bank_queue_3> ...

Optimizing unit <mig_7series_v1_8_bank_state_4> ...

Optimizing unit <mig_7series_v1_8_bank_queue_4> ...

Optimizing unit <mig_7series_v1_8_arb_select> ...
WARNING:Xst:1710 - FF/Latch <rnk_config_r_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_arb_select>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <mig_7series_v1_8_arb_row_col> ...

Optimizing unit <mig_7series_v1_8_round_robin_arb_3> ...

Optimizing unit <mig_7series_v1_8_bank_common> ...
WARNING:Xst:1710 - FF/Latch <generate_maint_cmds.send_cnt_r_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_bank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <generate_maint_cmds.send_cnt_r_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_bank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <generate_maint_cmds.send_cnt_r_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_bank_common>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <generate_maint_cmds.send_cnt_r_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_bank_common>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <mig_7series_v1_8_col_mach> ...

Optimizing unit <mig_7series_v1_8_ddr_phy_top> ...

Optimizing unit <mig_7series_v1_8_ddr_calib_top> ...

Optimizing unit <mig_7series_v1_8_ddr_phy_dqs_found_cal> ...
WARNING:Xst:1710 - FF/Latch <rd_byte_data_offset<0>_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_dqs_found_cal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_byte_data_offset<0>_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_dqs_found_cal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <detect_rd_cnt_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_dqs_found_cal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <final_data_offset_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_dqs_found_cal>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <mig_7series_v1_8_ddr_phy_rdlvl> ...
WARNING:Xst:1710 - FF/Latch <cal1_cnt_cpt_r_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rd_mux_sel_r_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_rdlvl>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <mig_7series_v1_8_ddr_phy_prbs_rdlvl> ...

Optimizing unit <mig_7series_v1_8_ddr_phy_wrlvl> ...

Optimizing unit <mig_7series_v1_8_ddr_phy_oclkdelay_cal> ...

Optimizing unit <mig_7series_v1_8_ddr_phy_wrcal> ...
WARNING:Xst:1710 - FF/Latch <cal2_pass_fail_1> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_3> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_4> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_5> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_6> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_7> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_8> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_9> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_10> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_11> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_12> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_13> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_14> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_15> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cal2_pass_fail_16> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_wrcal>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <mig_7series_v1_8_ddr_phy_tempmon> ...

Optimizing unit <mig_7series_v1_8_ddr_prbs_gen> ...
INFO:Xst:2261 - The FF/Latch <lfsr_q_2> in Unit <mig_7series_v1_8_ddr_prbs_gen> is equivalent to the following FF/Latch, which will be removed : <lfsr_q_34> 
INFO:Xst:2261 - The FF/Latch <lfsr_q_2> in Unit <mig_7series_v1_8_ddr_prbs_gen> is equivalent to the following FF/Latch, which will be removed : <lfsr_q_34> 

Optimizing unit <mig_7series_v1_8_ddr_phy_init> ...
WARNING:Xst:1710 - FF/Latch <phy_address_0> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <num_reads_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <mig_7series_v1_8_ddr_phy_ck_addr_cmd_delay> ...

Optimizing unit <mig_7series_v1_8_ddr_mc_phy_wrapper> ...

Optimizing unit <mig_7series_v1_8_ddr_mc_phy> ...

Optimizing unit <mig_7series_v1_8_ddr_phy_4lanes_1> ...

Optimizing unit <mig_7series_v1_8_ddr_byte_lane_1> ...

Optimizing unit <mig_7series_v1_8_ddr_byte_group_io_1> ...

Optimizing unit <mig_7series_v1_8_ddr_byte_lane_2> ...

Optimizing unit <mig_7series_v1_8_ddr_byte_lane_3> ...

Optimizing unit <mig_7series_v1_8_ddr_byte_lane_4> ...

Optimizing unit <mig_7series_v1_8_ddr_phy_4lanes_2> ...

Optimizing unit <mig_7series_v1_8_ddr_of_pre_fifo_1> ...

Optimizing unit <mig_7series_v1_8_axi_mc> ...

Optimizing unit <mig_7series_v1_8_axi_mc_r_channel> ...

Optimizing unit <mig_7series_v1_8_axi_mc_simple_fifo_3> ...

Optimizing unit <mig_7series_v1_8_axi_mc_simple_fifo_4> ...

Optimizing unit <mig_7series_v1_8_ddr_axic_register_slice_5> ...

Optimizing unit <mig_7series_v1_8_ddr_w_upsizer> ...

Optimizing unit <mig_7series_v1_8_ddr_comparator_sel> ...

Optimizing unit <mig_7series_v1_8_ddr_axic_register_slice_11> ...

Optimizing unit <mig_7series_v1_8_ddr_a_upsizer_1> ...

Optimizing unit <mig_7series_v1_8_ddr_command_fifo> ...

Optimizing unit <mig_7series_v1_8_ddr_a_upsizer_2> ...

Optimizing unit <mig_7series_v1_8_ddr_r_upsizer> ...

Optimizing unit <mig_7series_v1_8_axi_mc_aw_channel> ...

Optimizing unit <mig_7series_v1_8_axi_mc_cmd_translator> ...

Optimizing unit <mig_7series_v1_8_axi_mc_incr_cmd> ...

Optimizing unit <mig_7series_v1_8_axi_mc_wrap_cmd> ...

Optimizing unit <mig_7series_v1_8_axi_mc_wr_cmd_fsm> ...

Optimizing unit <mig_7series_v1_8_axi_mc_w_channel> ...

Optimizing unit <mig_7series_v1_8_axi_mc_simple_fifo_1> ...

Optimizing unit <mig_7series_v1_8_axi_mc_simple_fifo_2> ...

Optimizing unit <mig_7series_v1_8_axi_mc_ar_channel> ...

Optimizing unit <mig_7series_v1_8_axi_mc_cmd_fsm> ...

Optimizing unit <mig_7series_v1_8_axi_mc_cmd_arbiter> ...

Optimizing unit <mig_7series_v1_8_ui_rd_data> ...

Optimizing unit <mig_7series_v1_8_ui_wr_data> ...

Optimizing unit <mig_7series_v1_8_ui_cmd> ...

Optimizing unit <mig_7series_v1_8_iodelay_ctrl> ...

Optimizing unit <mig_7series_v1_8_infrastructure> ...

Optimizing unit <mig_7series_v1_8_tempmon> ...

Optimizing unit <mig_7series_v1_8_axi4_wrapper> ...

Optimizing unit <mig_7series_v1_8_tg> ...

Optimizing unit <mig_7series_v1_8_data_gen_chk> ...

Optimizing unit <mig_7series_v1_8_chk_win> ...
WARNING:Xst:1710 - FF/Latch <num_reads_2> (without init value) has a constant value of 0 in block <mig_7series_v1_8_ddr_phy_init>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1303 - From in and out of unit u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top, both signals calib_in_common and u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/calib_in_common have a KEEP attribute, signal calib_in_common will be lost.
WARNING:Xst:1303 - From in and out of unit u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy, both signals if_empty and u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/if_empty have a KEEP attribute, signal if_empty will be lost.
WARNING:Xst:1303 - From in and out of unit temp_mon_enabled.u_mig_7series_v1_8_tempmon, both signals rst and u_ddr3_infrastructure/rstdiv0_sync_r<12> have a KEEP attribute, signal rst will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<64> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<63> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<62> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<61> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<60> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<59> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<58> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<43> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<42> and ddr3_vio_async_in_twm<40> have a KEEP attribute, signal ddr3_vio_async_in_twm<40> will be lost.
WARNING:Xst:2716 - In unit example_top, both signals ddr3_vio_async_in_twm<40> and ddr3_vio_async_in_twm<39> have a KEEP attribute, signal ddr3_vio_async_in_twm<39> will be lost.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_837> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_838> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_839> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_840> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_841> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_842> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_843> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_844> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_845> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_846> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_847> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_848> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_849> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_850> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_851> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_852> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_853> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_854> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_855> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_856> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_857> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_858> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_859> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_860> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_812> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_813> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_814> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_815> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_816> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_817> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_818> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_819> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_820> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_821> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_822> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_823> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_824> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_825> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_826> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_827> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_828> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_829> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_830> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_831> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_832> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_833> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_834> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_835> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_836> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_886> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_887> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_888> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_889> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_890> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_891> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_892> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_893> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_894> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_895> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_896> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_897> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_898> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_899> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_900> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_901> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_902> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_903> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_904> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_905> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_906> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_907> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_908> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_909> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_910> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_861> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_862> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_863> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_864> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_865> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_866> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_867> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_868> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_869> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_870> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_871> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_872> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_873> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_874> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_875> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_876> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_877> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_878> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_879> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_880> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_881> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_882> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_883> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_884> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_885> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_570> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_571> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_572> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_573> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_574> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_575> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_576> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_577> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_578> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_579> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_580> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_581> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_582> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_583> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_584> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_585> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_586> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_587> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_588> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_589> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_590> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_591> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_592> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_593> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_594> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_525> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_526> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_527> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_528> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_529> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_550> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_551> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_552> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_553> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_554> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_555> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_556> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_557> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_558> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_559> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_560> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_561> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_562> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_563> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_564> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_565> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_566> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_567> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_568> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_569> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_787> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_788> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_789> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_790> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_791> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_792> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_793> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_794> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_795> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_796> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_797> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_798> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_799> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_800> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_801> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_802> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_803> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_804> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_805> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_806> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_807> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_808> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_809> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_810> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_811> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_595> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_596> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_597> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_598> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_599> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_600> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_601> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_602> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_603> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_604> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_605> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_606> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_607> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_608> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_609> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_610> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_611> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_612> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_613> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_614> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_615> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_616> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_617> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_618> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_619> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_105> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_106> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_107> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_108> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_109> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_110> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_111> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_112> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_113> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_114> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_115> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_116> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_117> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_118> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_119> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_compare0/req_col_r_1> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_compare0/req_col_r_2> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_compare0/req_col_r_0> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_compare0/req_col_r_1> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_compare0/req_col_r_2> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_compare0/req_col_r_0> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_col_r_1> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_col_r_2> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_col_r_0> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_col_r_0> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1011> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1012> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1013> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1014> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1015> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1016> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1017> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1018> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1019> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1020> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1021> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1022> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1023> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_18> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_94> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_95> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_96> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_97> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_98> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_99> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_100> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_101> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_102> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_103> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_basic_104> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_bank_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_bank_10> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_bank_9> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/maint_sre_r_lcl> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/maint_srx_r_lcl> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/grant_r_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/temp_wrcal_done> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_0_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/temp_lmr_done> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_wd_i1_26> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/r_ignore_end_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_33> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_32> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_31> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_30> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AADDR_q_3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AADDR_q_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AADDR_q_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AADDR_q_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_cmd_r2_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_hi_pri_r1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_cmd_r1_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_addr_r1_2> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_addr_r1_1> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_addr_r1_0> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_col_r_2> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_col_r_1> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_59> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_58> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_57> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_56> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_55> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_54> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_53> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_52> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_51> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_50> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_49> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_48> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_47> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_46> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_45> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cas_slot_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_data_offset_2_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_data_offset_2_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_data_offset_2_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_ras_n_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_we_n_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cs_n_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cas_n_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_936> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_937> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_938> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_939> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_940> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_941> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_942> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_943> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_944> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_945> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_946> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_947> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_948> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_949> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_950> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_951> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_952> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_953> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_954> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_955> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_956> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_957> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_958> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_959> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_960> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_911> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_912> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_913> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_914> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_915> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_916> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_917> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_918> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_919> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_920> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_921> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_922> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_923> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_924> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_925> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_926> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_927> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_928> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_929> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_930> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_931> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_932> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_933> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_934> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_935> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_986> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_987> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_988> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_989> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_990> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_991> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_992> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_993> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_994> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_995> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_996> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_997> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_998> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_999> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1000> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1001> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1002> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1003> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1004> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1005> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1006> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1007> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1008> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1009> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_1010> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_961> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_962> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_963> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_964> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_965> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_966> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_967> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_968> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_969> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_970> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_971> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_972> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_973> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_974> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_975> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_976> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_977> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_978> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_979> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_980> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_981> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_982> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_983> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_984> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_985> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_157> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_158> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_159> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_160> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_161> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_162> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_163> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_170> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_171> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_172> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_173> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_174> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_175> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_176> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_177> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_178> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_179> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_180> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_181> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_182> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_183> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_184> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_185> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_186> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_187> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_35> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_36> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_37> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_38> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_39> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_48> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_49> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_139> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_140> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_141> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_142> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_143> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_144> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_145> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_146> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_147> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_148> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_149> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_150> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_151> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_152> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_153> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_154> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_155> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_156> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_252> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_253> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_254> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_255> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_256> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_257> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_258> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_259> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_260> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_261> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_262> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_263> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_264> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_265> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_266> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_267> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_268> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_269> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_270> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_271> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_272> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_273> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_274> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_275> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_276> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_202> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_204> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_205> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_230> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_231> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_232> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_233> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_234> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_235> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_236> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_237> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_238> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_239> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_240> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_241> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_242> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_243> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_244> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_245> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_246> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_247> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_248> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_249> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_250> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_251> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_94> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_95> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_120> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_121> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_122> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_123> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_124> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_125> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_126> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_127> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_128> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_129> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_130> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_131> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_132> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_133> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_134> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_135> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_136> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_137> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_138> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_139> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_140> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_141> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_142> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_5> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_9> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_21> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_22> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_23> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_24> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_25> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_26> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_27> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_28> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_29> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_30> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_31> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_63> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_68> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_69> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_82> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_83> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_84> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_85> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_86> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_87> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_91> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_92> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_93> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_244> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_245> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_246> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_247> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_248> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_249> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_250> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_251> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_252> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_253> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_254> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_255> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_8> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_9> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_10> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_11> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_20> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_21> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_22> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_23> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_30> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_31> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_32> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_33> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_34> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_143> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_144> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_145> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_146> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_147> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_148> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_149> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_162> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_163> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_164> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_165> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_166> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_167> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_168> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_169> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_170> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_171> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_172> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_173> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_174> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_175> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_176> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_241> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_242> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_243> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_450> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_451> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_452> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_453> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_454> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_455> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_456> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_457> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_458> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_459> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_460> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_461> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_462> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_463> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_464> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_465> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_466> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_467> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_468> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_469> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_470> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_471> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_472> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_473> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_474> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_401> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_402> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_403> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_404> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_405> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_406> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_407> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_408> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_409> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_410> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_411> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_412> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_413> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_414> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_415> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_416> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_417> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_418> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_419> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_420> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_421> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_446> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_447> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_448> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_449> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_500> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_501> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_502> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_503> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_504> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_505> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_506> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_507> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_508> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_509> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_510> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_511> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_512> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_513> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_514> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_515> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_516> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_517> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_518> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_519> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_520> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_521> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_522> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_523> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_524> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_475> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_476> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_477> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_478> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_479> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_480> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_481> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_482> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_483> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_484> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_485> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_486> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_487> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_488> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_489> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_490> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_491> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_492> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_493> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_494> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_495> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_496> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_497> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_498> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_499> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_302> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_303> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_304> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_305> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_306> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_307> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_308> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_309> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_310> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_311> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_312> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_313> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_338> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_339> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_340> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_341> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_342> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_343> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_344> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_345> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_346> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_347> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_348> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_349> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_350> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_277> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_278> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_279> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_280> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_281> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_282> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_283> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_284> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_285> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_286> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_287> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_288> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_289> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_290> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_291> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_292> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_293> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_294> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_295> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_296> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_297> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_298> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_299> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_300> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_301> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_376> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_377> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_378> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_379> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_380> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_381> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_382> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_383> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_384> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_385> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_386> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_387> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_388> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_389> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_390> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_391> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_392> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_393> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_394> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_395> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_396> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_397> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_398> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_399> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_400> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_351> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_352> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_353> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_354> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_355> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_356> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_357> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_358> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_359> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_360> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_361> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_362> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_363> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_375> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_374> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_373> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_372> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_371> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_370> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_369> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_368> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_367> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_366> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_365> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_364> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_common0/maint_controller.maint_srx_r1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_addr_r2_2> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_addr_r2_1> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_addr_r2_0> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_wd_i2_26> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <app_rd_data_valid_r1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_4> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_5> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_6> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_7> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_8> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_13> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_14> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_15> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_16> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_17> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_18> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_19> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_20> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_21> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_22> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_23> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_24> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_25> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_26> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_27> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_28> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_29> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_30> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_31> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_32> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_33> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_34> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_35> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <ddr3_vio_sync_out_45> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <app_rd_data_valid_r2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_compare0/rank_busy_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_compare0/rank_busy_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/rank_busy_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/rank_busy_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_rank_cnt> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out0_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out0_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out0_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out0_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out1_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out1_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out1_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_aux_out1_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_odt_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/app_sr_active_r> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_mux.col_size_r> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_mux.col_rmw_r> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/sent_col_lcl_r> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/last_master_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/last_master_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/last_master_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/last_master_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/grant_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/grant_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/grant_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/config_arb0/grant_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/second_fail_taps_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/second_fail_taps_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/second_fail_taps_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/second_fail_taps_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/second_fail_taps_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/second_fail_taps_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/second_fail_detect> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_fall0_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/prev_rd_rise0_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_fall0_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/sel_rd_rise0_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt1_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt1_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt1_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt1_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/stable_pass_cnt1_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_11> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_10> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_9> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_8> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_coarse_tap_cnt_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_dec_cnt_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_dec_cnt_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_dec_cnt_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_dec_cnt_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_dec_cnt_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_16> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_15> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_14> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_13> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_12> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_11> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_10> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_9> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_8> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/po_fine_tap_cnt_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/restart_stable_cnt1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/restart_stable_cnt> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_pass_fail_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_po_dly_load> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_done_r1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_2_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_2_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_2_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_2_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_2_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_2_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/no_rst_tg_mc> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_writes> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i2_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i2_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i2_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i2_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i2_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i2_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i1_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i1_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i1_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i1_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i1_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/data_offset_2_i1_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/pi_dqs_found> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/pi_dqs_out_of_range> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/pi_phase_locked> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/pi_fine_overflow> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/po_fine_overflow> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/po_coarse_overflow> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem141> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem142> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem13> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_79> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_78> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_77> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_76> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_75> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_74> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_73> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_72> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_71> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_70> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_69> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_68> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_67> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r_66> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem141> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem142> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem13> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_79> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_78> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_77> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_76> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_75> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_74> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_73> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_72> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem141> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem142> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem13> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_79> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_78> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_77> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_76> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_75> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_74> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_73> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_72> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem141> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem142> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem13> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_79> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_78> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_77> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_76> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_75> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_74> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_73> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_72> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/pi_dqs_found> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/po_fine_overflow> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/po_coarse_overflow> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/entry_cnt_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/entry_cnt_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/entry_cnt_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/entry_cnt_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25852_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25850_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25854_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25848_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25846_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25842_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25840_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_43> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_42> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_41> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_40> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_39> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_38> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_37> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_36> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_35> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_34> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_33> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_32> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_26> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_25> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_24> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_23> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_22> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_21> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_20> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_19> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_18> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_17> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/_o25844_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r1_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r1_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r1_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/trans_buf_out_r1_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/r_ignore_begin_r> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/r_arid_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/r_arid_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/r_arid_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/r_arid_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/Mshreg_dout_256_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/Mshreg_dout_6_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/Mshreg_dout_5_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/Mshreg_dout_4_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/Mshreg_dout_3_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/transaction_fifo_0/Mshreg_dout_1_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_65> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_64> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_63> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_62> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_61> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_60> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_16> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_15> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_14> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_13> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_12> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_11> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_10> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_9> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_8> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/storage_data1_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_65> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_64> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_63> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_62> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_61> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_60> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_16> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_15> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_14> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_13> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_12> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_11> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_10> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_9> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_8> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/storage_data1_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_data_inst/USE_REGISTER.M_AXI_WLAST_q> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data2_262> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data2_261> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data2_260> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data2_259> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data2_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data2_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data1_262> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data1_261> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data1_260> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data1_259> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data1_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/storage_data1_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AADDR_q_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AADDR_q_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ABURST_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ASIZE_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ASIZE_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ASIZE_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AQOS_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AQOS_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AQOS_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AQOS_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AREGION_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AREGION_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AREGION_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AREGION_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ALOCK_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_ALOCK_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_APROT_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_APROT_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_APROT_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AID_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AID_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AID_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AID_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AADDR_q_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AADDR_q_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ABURST_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ASIZE_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ASIZE_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ASIZE_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AQOS_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AQOS_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AQOS_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AQOS_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AREGION_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AREGION_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AREGION_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AREGION_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ACACHE_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ALOCK_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_ALOCK_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_APROT_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_APROT_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_APROT_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AID_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AID_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AID_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AID_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_data_inst/rresp_wrap_buffer_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_data_inst/rresp_wrap_buffer_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_data_inst/rid_wrap_buffer_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_data_inst/rid_wrap_buffer_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_data_inst/rid_wrap_buffer_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_data_inst/rid_wrap_buffer_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_7> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awlen_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awid_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awid_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awid_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/awid_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/Mshreg_dout_2_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/Mshreg_dout_1_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/Mshreg_dout_3_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_fifo_0/Mshreg_dout_0_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/wrap_boundary_axaddr_r_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/axaddr_wrap_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_30> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axaddr_incr_31> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/arid_r_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/arid_r_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/arid_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/arid_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_sz_r2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_cmd_r2_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_sz_r1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_cmd_r1_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_cntr_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_cntr_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_cntr_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_cntr_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_7> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_6> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_5> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_4> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rd_len_cntr_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wr_cntr_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wr_cntr_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wr_cntr_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wr_cntr_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_fsm_sts_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_fsm_sts_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_fsm_sts_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/bresp_r_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/bresp_r_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/brespid_r_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/brespid_r_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/brespid_r_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/brespid_r_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/err_resp> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/rrid_err> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_31> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_30> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_31> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_30> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/dbg_rd_sts_vld> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/dbg_wr_sts_vld> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_15> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_14> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_13> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_12> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_11> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_10> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_9> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_8> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_7> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_6> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_5> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_4> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/rdata_sts_r_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_15> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_14> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_13> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_12> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_11> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_10> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_9> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_8> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_7> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_6> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_5> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_4> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/wdata_sts_r_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_7> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_6> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_5> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_4> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_3> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_2> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_1> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <mig_7series_v1_8_axi4_tg_inst/traffic_gen_inst/data_gen_chk_inst/wrd_cntr_0> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win/win_clr_error> of sequential type is unconnected in block <example_top>.
WARNING:Xst:2677 - Node <CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win/po_win_tg_rst> of sequential type is unconnected in block <example_top>.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_hi_pri_r2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_compare0/req_cmd_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_compare0/req_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_compare0/req_cmd_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_compare0/req_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_cmd_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_compare0/req_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_cmd_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_queue0/q_has_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_queue0/q_has_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_queue0/q_has_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_queue0/q_has_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/cke_r> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_common0/was_priority> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_11> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_27> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_19> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cke_1> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cke_2> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cke_3> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/sr_cntrl.ckesr_timer.ckesr_timer_r_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/sr_cntrl.ckesr_timer.ckesr_timer_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/last_master_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/grant_r_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AADDR_q_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AADDR_q_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AADDR_q_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AADDR_q_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_WRITE.write_addr_inst/USE_REGISTER.M_AXI_AADDR_q_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/USE_READ.read_addr_inst/USE_REGISTER.M_AXI_AADDR_q_4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cke_0> (without init value) has a constant value of 1 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_14> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_16> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_19> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_20> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_22> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_9> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_10> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_11> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_7> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_8> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/po_stg3_dec> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/stg2_dec2_cnt_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/stg2_inc2_cnt_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_cnt_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_cnt_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_cnt_r_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_cnt_r_3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_cnt_r_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_cnt_r_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/cnt_dqs_r_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_data_control.wb_wr_data_addr0_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axlen_cnt_8> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/axlen_cnt_8> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delaydec_cnt_r_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_cnt_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_cnt_r_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_cnt_r_3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_cnt_r_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_cnt_r_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_1_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_wr_cnt_3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclk_wr_cnt_3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/enable_wrlvl_cnt_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/dqs_po_stg2_c_incdec> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_po_dly_req> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_act_req> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_corse_cnt_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_7> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_8> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_10> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_fine_cnt_3_13> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<7>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cal1_wait_cnt_r_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/regl_rank_cnt_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/regl_rank_cnt_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/regl_dqs_cnt_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/stable_idel_cnt_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/final_data_offset_mc<0>_0> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/final_do_max_0_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dec_cnt_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/demand_act_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/act_starve_limit_cntr_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/act_starve_limit_cntr_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/demand_act_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/act_starve_limit_cntr_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/act_starve_limit_cntr_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/demand_act_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/act_starve_limit_cntr_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/act_starve_limit_cntr_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/demand_act_priority_r> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/act_starve_limit_cntr_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/act_starve_limit_cntr_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/wr_data_offset_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_6> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_7> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_8> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_9> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_10> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/corse_dec_3_11> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/rank_cnt_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/rank_cnt_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/prbs_dqs_cnt_r_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rnk_cnt_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rnk_cnt_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/rnk_cnt_r_0> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/rnk_cnt_r_1> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<0>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<1>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<2>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<3>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<4>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<5>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pb_cnt_eye_size_r<6>_4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/po_en_stg3> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/regl_dqs_cnt_r_2> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/final_data_offset_mc<0>_6> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/final_data_offset<0>_6> has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:638 - in unit u_ddr3_interface_fast Conflict on KEEP property on signal u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/wr_data_offset and u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<5> u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<5> signal will be lost.
WARNING:Xst:638 - in unit u_ddr3_interface_fast Conflict on KEEP property on signal u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<5> and u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<4> u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<4> signal will be lost.
WARNING:Xst:638 - in unit u_ddr3_interface_fast Conflict on KEEP property on signal u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<4> and u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/dqs_po_stg2_c_incdec u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/dqs_po_stg2_c_incdec signal will be lost.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ck_addr_cmd_delay_done_r6> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ck_addr_cmd_delay_done_r5> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ck_addr_cmd_delay_done_r4> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ck_addr_cmd_delay_done_r3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ck_addr_cmd_delay_done_r2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ck_addr_cmd_delay_done_r1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/count_3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/count_2> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/count_1> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/count_0> of sequential type is unconnected in block <u_ddr3_interface_fast>.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_state_r_FSM_FFd4> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_state_r_FSM_FFd10> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:638 - in unit u_ddr3_interface_fast Conflict on KEEP property on signal u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<4> and u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_state_r_FSM_FFd4 u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_state_r_FSM_FFd4 signal will be lost.
WARNING:Xst:1710 - FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_state_r_FSM_FFd5> (without init value) has a constant value of 0 in block <u_ddr3_interface_fast>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:638 - in unit u_ddr3_interface_fast Conflict on KEEP property on signal u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel<4> and u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_state_r_FSM_FFd5 u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_state_r_FSM_FFd5 signal will be lost.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_wrpath_90> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_29> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_169> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ddr3_ila_rdpath_768> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win/byte_cntr_3> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <CHIPSCOPE_INST.u_mig_7series_v1_8_chk_win/byte_cntr_2> (without init value) has a constant value of 0 in block <example_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:638 - in unit example_top Conflict on KEEP property on signal ddr3_vio_async_in_twm<103> and ddr3_vio_async_in_twm<50> ddr3_vio_async_in_twm<50> signal will be lost.
WARNING:Xst:638 - in unit example_top Conflict on KEEP property on signal ddr3_vio_async_in_twm<103> and ddr3_vio_async_in_twm<49> ddr3_vio_async_in_twm<49> signal will be lost.
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_100> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_68> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_36> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_4> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_101> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_69> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_37> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_5> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_102> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_70> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_38> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_6> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_103> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_71> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_39> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_7> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_104> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_72> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_40> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_8> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_110> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_78> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_46> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_14> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_105> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_73> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_41> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_9> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_111> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_79> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_47> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_15> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_106> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_74> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_42> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_10> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_112> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_80> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_48> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_16> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_107> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_75> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_43> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_11> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_113> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_81> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_49> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_17> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_108> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_76> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_44> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_12> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_114> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_82> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_50> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_18> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_109> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_77> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_45> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_13> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_120> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_88> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_56> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_24> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_115> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_83> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_51> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_19> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_121> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_89> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_57> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_25> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_116> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_84> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_52> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_20> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_122> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_90> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_58> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_26> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_117> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_85> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_53> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_21> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_123> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_91> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_59> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_27> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_118> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_86> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_54> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_22> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_124> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_92> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_60> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_28> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_119> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_87> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_55> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_23> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_125> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_93> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_61> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_29> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_126> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_94> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_62> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_30> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_127> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_95> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_63> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_31> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_100> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_68> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_36> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_4> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_101> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_69> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_37> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_5> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_102> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_70> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_38> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_6> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_103> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_71> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_39> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_7> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_96> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_64> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_32> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_0> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_104> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_72> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_40> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_8> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_97> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_65> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_33> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_1> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_105> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_73> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_41> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_9> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_110> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_78> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_46> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_14> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_98> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_66> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_34> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_2> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_106> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_74> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_42> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_10> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_111> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_79> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_47> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_15> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_100> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_68> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_36> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_4> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_107> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_75> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_43> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_11> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_112> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_80> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_48> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_16> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_99> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_67> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_35> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_3> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_101> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_69> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_37> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_5> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_108> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_76> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_44> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_12> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_113> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_81> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_49> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_17> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_102> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_70> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_38> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_6> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_109> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_77> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_45> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_13> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_114> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_82> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_50> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_18> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_103> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_71> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_39> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_7> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_115> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_83> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_51> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_19> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_120> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_88> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_56> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_24> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_104> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_72> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_40> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_8> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_116> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_84> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_52> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_20> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_121> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_89> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_57> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_25> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_110> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_78> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_46> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_14> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_117> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_85> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_53> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_21> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_122> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_90> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_58> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_26> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_105> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_73> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_41> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_9> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_111> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_79> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_47> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_15> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_118> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_86> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_54> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_22> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_123> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_91> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_59> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_27> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_106> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_74> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_42> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_10> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_112> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_80> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_48> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_16> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_119> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_87> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_55> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_23> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_124> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_92> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_60> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_28> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_107> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_75> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_43> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_11> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_113> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_81> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_49> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_17> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_96> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_64> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_32> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_0> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_125> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_93> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_61> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_29> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_108> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_76> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_44> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_12> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_114> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_82> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_50> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_18> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_97> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_65> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_33> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_1> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_126> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_94> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_62> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_30> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_109> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_77> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_45> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_13> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_120> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_88> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_56> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_24> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_98> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_66> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_34> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_2> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_127> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_95> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_63> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_31> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_115> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_83> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_51> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_19> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_121> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_89> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_57> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_25> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_99> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_67> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_35> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r2_3> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_116> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_84> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_52> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_20> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_122> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_90> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_58> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_26> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_117> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_85> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_53> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_21> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_123> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_91> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_59> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_27> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_118> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_86> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_54> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_22> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_124> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_92> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_60> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_28> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_119> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_87> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_55> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_23> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_125> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_93> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_61> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_29> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_126> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_94> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_62> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_30> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_127> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_95> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_63> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/axi_wd_data_31> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrap_r> in Unit <example_top> is equivalent to the following 8 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/ctl_r_1> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/ctl_r_0> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_29> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_28> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_27> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_26> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_25> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_r_24> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrap_w> in Unit <example_top> is equivalent to the following 12 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_29> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_28> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_27> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_26> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_25> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_24> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_3> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_2> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_1> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/addr_w_0> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/ctl_w_1> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/ctl_w_0> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_96> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_64> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_32> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_0> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_97> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_65> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_33> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_1> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_98> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_66> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_34> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_2> 
INFO:Xst:2261 - The FF/Latch <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_99> in Unit <example_top> is equivalent to the following 3 FFs/Latches, which will be removed : <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_67> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_35> <mig_7series_v1_8_axi4_tg_inst/axi4_wrapper_inst/wrdata_r1_3> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_data_offset_2_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cmd_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_data_offset_2_3> in Unit <u_ddr3_interface_fast> is equivalent to the following 2 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_data_offset_2_1> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/mc_aux_out_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buf_indx_copy_r_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/rd_buf_indx_r_0> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buf_indx_copy_r_1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/rd_buf_indx_r_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buf_indx_copy_r_2> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/rd_buf_indx_r_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buf_indx_copy_r_3> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/rd_buf_indx_r_3> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buf_indx_copy_r_4> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/rd_buf_indx_r_4> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/phy_mc_cmd_full_r> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/phy_mc_cmd_full_r> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/phy_mc_cmd_full_r> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/phy_mc_ctl_full_r> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/phy_mc_ctl_full_r> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/phy_mc_ctl_full_r> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_10> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_10> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_11> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_11> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_12> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_12> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_13> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_13> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_14> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_14> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_20> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_20> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_15> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_15> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_21> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_21> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_16> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_16> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_22> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_22> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_17> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_17> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_23> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_23> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_18> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_18> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_19> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_19> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/areset_d_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/areset_d_0> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/aw_pipe/areset_d_1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/si_register_slice_inst/ar_pipe/areset_d_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/maint_zq_r_lcl> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/maintenance_request.maint_arb0/last_master_r_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cmd_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/sent_col_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/rd_active_r> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_0> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26575_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_2> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_3> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_3> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/final_do_index_0_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_pwron_ce_r_0> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_4> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_4> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_27> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_ras_n_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/prbs_rdlvl_done_r1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_5> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_5> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_6> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_6> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_29> in Unit <u_ddr3_interface_fast> is equivalent to the following 8 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_28> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_26> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_17> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_16> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_address_15> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cmd_2> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cs_n_1> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cas_n_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_7> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_7> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_8> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_8> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/largest_3_9> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_3_9> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/app_wdf_end_r1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/app_wdf_wren_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_prbs_gen/phy_if_empty_r> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_if_empty_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26579_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/aw_cmd_fsm_0/init_complete_r1> in Unit <u_ddr3_interface_fast> is equivalent to the following 2 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/mc_init_complete_r1> <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/ar_cmd_fsm_0/init_complete_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_mux.col_data_buf_addr_r_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_0> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/sel_first> in Unit <u_ddr3_interface_fast> is equivalent to the following 2 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/sel_first> <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/axi_mc_cmd_translator_0/sel_first> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_mux.col_data_buf_addr_r_1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_mux.col_data_buf_addr_r_2> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_mux.col_data_buf_addr_r_3> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_3> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26581_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_mux.col_data_buf_addr_r_4> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_4> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/override_demand_r> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/override_demand_r> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/override_demand_r> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/override_demand_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_73> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_65> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26585_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_75> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26573_67> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/mc_init_complete_r> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/aw_cmd_fsm_0/init_complete_r> <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/mc_init_complete_r> <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_ar_channel_0/ar_cmd_fsm_0/init_complete_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_done> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_tmp_odt_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/rank_mach0/rank_common0/periodic_read_request.periodic_rd_r_cnt> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/bank_common0/periodic_rd_cntr_r> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_ras_n_2> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cs_n_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26577_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/rd_active_r1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/rd_active_r2> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/rd_active_r3> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/rd_active_r4> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r4> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/fine_inc_cnt_5> in Unit <u_ddr3_interface_fast> is equivalent to the following 5 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/fine_inc_cnt_4> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/fine_inc_cnt_3> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/fine_inc_cnt_2> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/fine_inc_cnt_1> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/fine_inc_cnt_0> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/rdlvl_stg1_done_r1> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_stg1_done_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_55> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26571_47> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/dec_cnt_2> in Unit <u_ddr3_interface_fast> is equivalent to the following 2 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/dec_cnt_1> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/dec_cnt_0> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_select0/col_rd_wr_r> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/col_rd_wr_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r1> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/rst_r1> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/rst_r1> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r1> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r2> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/rst_r2> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/rst_r2> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r3> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/rst_r3> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/rst_r3> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r3> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r4> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/rst_r4> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/rst_r4> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_55> in Unit <u_ddr3_interface_fast> is equivalent to the following 3 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_54> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_53> <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26583_52> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_26> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/_o26587_2> 
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/sel_first> in Unit <u_ddr3_interface_fast> is equivalent to the following 2 FFs/Latches, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_incr_cmd_0/sel_first> <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_aw_channel_0/axi_mc_cmd_translator_0/axi_mc_wrap_cmd_0/sel_first> 

Mapping all equations...
WARNING:Xst:2677 - Node <u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/app_wdf_rdy_r_copy3> of sequential type is unconnected in block <u_ddr3_interface_fast>.
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/mc_cas_slot_0> in Unit <u_ddr3_interface_fast> is equivalent to the following FF/Latch, which will be removed : <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_zero_ctrl_0> 
Found area constraint ratio of 100 (+ 0) on block example_top, actual ratio is 4.
FlipFlop u_ddr3_interface_fast/u_ddr3_infrastructure/rstdiv0_sync_r_11 has been replicated 11 time(s)
FlipFlop u_ddr3_interface_fast/u_ddr3_infrastructure/rstdiv0_sync_r_12 has been replicated 119 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_in_common has been replicated 9 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel_0 has been replicated 11 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel_1 has been replicated 11 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_sel_3 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_zero_inputs_0 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/calib_zero_inputs_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/idelay_inc_r2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete has been replicated 86 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_po_dec_done has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wr_level_done has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/ocal_done_r has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_calib_complete has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cal1_cnt_cpt_r_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/cal1_cnt_cpt_r_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/mpr_rdlvl_done_r has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/rdlvl_stg1_done has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_dqs_cnt_r_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_dqs_cnt_r_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_dqs_cnt_r_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 has been replicated 43 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_0 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_1 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_0 has been replicated 24 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_full_1 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_0 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_1 has been replicated 15 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_2 has been replicated 14 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_3 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_3 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 has been replicated 43 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_0 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_1 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_0 has been replicated 24 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_full_1 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_0 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_1 has been replicated 15 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_2 has been replicated 14 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_3 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_3 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 has been replicated 43 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_0 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_1 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_0 has been replicated 24 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_full_1 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_0 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_1 has been replicated 15 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_2 has been replicated 14 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_3 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_3 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 has been replicated 43 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_3 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_0 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/rd_ptr_1 has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_empty_r_3 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_0 has been replicated 24 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_full_1 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_0 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_1 has been replicated 15 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_2 has been replicated 14 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_3 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_3 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_0 has been replicated 14 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_0 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_1 has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_2 has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_3 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_0 has been replicated 12 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_empty_2 has been replicated 2 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/my_full_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_0 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_1 has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_2 has been replicated 7 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_3 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_0 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_1 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr_2 has been replicated 1 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/wr_data_addr_0 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/wr_data_addr_1 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/wr_data_addr_2 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/wr_data_addr_3 has been replicated 4 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/reset has been replicated 3 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/state_0 has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/USE_UPSIZER.upsizer_d2/mi_register_slice_inst/r_pipe/state_1 has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_0 has been replicated 26 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_1 has been replicated 26 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_2 has been replicated 26 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_3 has been replicated 26 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_r_channel_0/rd_data_fifo_0/cnt_read_4 has been replicated 25 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wr_data_fifo_0/cnt_read_0 has been replicated 29 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wr_data_fifo_0/cnt_read_1 has been replicated 29 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wr_data_fifo_0/cnt_read_2 has been replicated 29 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_cmd0/app_rdy_r has been replicated 8 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/app_rd_data_valid has been replicated 26 time(s)
FlipFlop u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/ram_init_done_r_lcl has been replicated 2 time(s)

Final Macro Processing ...

Processing Unit <u_ddr3_interface_fast> :
	Found 9-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9>.
	Found 3-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r5>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/rst_dqs_find_r2>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/sr_valid_r2>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_rdlvl/pi_fine_dly_dec_done>.
	Found 5-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5>.
	Found 4-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/delay_done_r4>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/rd_active_r3>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/pat_match_rise3_r_7>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/pat_match_rise3_r_3>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/pat_match_rise2_r_4>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/pat_match_rise2_r_0>.
	Found 3-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r3>.
	Found 6-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_5>.
	Found 6-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7>.
	Found 15-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_14>.
	Found 15-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_15>.
	Found 5-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_5>.
	Found 3-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_wd_i2_24>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_wd_i2_23>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/phy_ctl_wr_i2>.
	Found 12-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_11>.
	Found 4-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r4>.
	Found 12-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_11>.
	Found 2-bit shift register for signal <u_mig_7series_v1_8_memc_ui_top_axi/u_axi_mc/mc_init_complete_r>.
INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal <u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/mcGo_r_15> and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL32 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <u_ddr3_interface_fast> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 13172
 Flip-Flops                                            : 13172
# Shift Registers                                      : 26
 12-bit shift register                                 : 2
 15-bit shift register                                 : 2
 2-bit shift register                                  : 12
 3-bit shift register                                  : 3
 4-bit shift register                                  : 2
 5-bit shift register                                  : 2
 6-bit shift register                                  : 2
 9-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                                                                                                                                                                                            | Clock buffer(FF name)                                                                                                                                                                                                          | Load  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
u_ddr3_interface_fast/u_ddr3_infrastructure/clk_pll_i                                                                                                                                                   | BUFG                                                                                                                                                                                                                           | 13968 |
u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clk_delayed| NONE(u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/dqs_gen.oddr_dqsts)| 2     |
u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clk_delayed| NONE(u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/dqs_gen.oddr_dqs)  | 2     |
u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clk_delayed| NONE(u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs)  | 2     |
u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clk_delayed| NONE(u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs)  | 2     |
u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clk        | NONE(u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck)| 1     |
sys_clk_i                                                                                                                                                                                               | PLLE2_ADV:CLKOUT5                                                                                                                                                                                                              | 59    |
sys_clk_i                                                                                                                                                                                               | PLLE2_ADV:CLKOUT4                                                                                                                                                                                                              | 1     |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 5.552ns (Maximum Frequency: 180.120MHz)
   Minimum input arrival time before clock: 1.940ns
   Maximum output required time after clock: 2.954ns
   Maximum combinational path delay: 1.053ns

=========================================================================
Release 14.4 - Xilinx CORE Generator P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/coregen.log
Resolving generic values...
Finished resolving generic values.
Generating IP...
Configuring files for ddr_icon root...
Gathering HDL files for ddr_icon root...
Creating XST project for ddr_icon...
Creating XST script file for ddr_icon...
Creating XST instantiation file for ddr_icon...
Running XST for ddr_icon...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Not generating VHDL wrapper
Not generating Verilog wrapper
Skipping VHDL instantiation template for ddr_icon...
Skipping Verilog instantiation template for ddr_icon...
Finished Generation.
Generating IP instantiation template...
Generating ASY schematic symbol...
Generating metadata file...
Generating ISE project...
XCO file found: ddr_icon.xco
XMDF file found: ddr_icon_xmdf.tcl
WARNING: ddr_icon.vhd does not exist, will not be added to ISE project.
WARNING: ddr_icon.vho does not exist, will not be added to ISE project.
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_icon.asy -view all -origin_type imported
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_icon.ngc -view all -origin_type created
Checking file
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_icon.ngc" for project device match ...
File
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_icon.ngc" device information matches project
device.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/ddr_icon"
Generating README file...
Generating FLIST file...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
Release 14.4 - Xilinx CORE Generator P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/coregen.log
Resolving generic values...
Finished resolving generic values.
Generating IP...
Configuring files for ddr_ila_basic root...
Gathering HDL files for ddr_ila_basic root...
Creating XST project for ddr_ila_basic...
Creating XST script file for ddr_ila_basic...
Creating XST instantiation file for ddr_ila_basic...
Running XST for ddr_ila_basic...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Not generating VHDL wrapper
Not generating Verilog wrapper
Skipping VHDL instantiation template for ddr_ila_basic...
Skipping Verilog instantiation template for ddr_ila_basic...
Finished Generation.
Generating IP instantiation template...
Generating ASY schematic symbol...
Generating metadata file...
Generating ISE project...
XCO file found: ddr_ila_basic.xco
XMDF file found: ddr_ila_basic_xmdf.tcl
WARNING: ddr_ila_basic.vhd does not exist, will not be added to ISE project.
WARNING: ddr_ila_basic.vho does not exist, will not be added to ISE project.
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_ila_basic.asy -view all -origin_type imported
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_ila_basic.ngc -view all -origin_type created
Checking file
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_ila_basic.ngc" for project device match ...
File
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_ila_basic.ngc" device information matches project
device.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/ddr_ila_basic"
Generating README file...
Generating FLIST file...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
Release 14.4 - Xilinx CORE Generator P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/coregen.log
Resolving generic values...
Finished resolving generic values.
Generating IP...
Configuring files for ddr_ila_wrpath root...
Gathering HDL files for ddr_ila_wrpath root...
Creating XST project for ddr_ila_wrpath...
Creating XST script file for ddr_ila_wrpath...
Creating XST instantiation file for ddr_ila_wrpath...
Running XST for ddr_ila_wrpath...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Not generating VHDL wrapper
Not generating Verilog wrapper
Skipping VHDL instantiation template for ddr_ila_wrpath...
Skipping Verilog instantiation template for ddr_ila_wrpath...
Finished Generation.
Generating IP instantiation template...
Generating ASY schematic symbol...
Generating metadata file...
Generating ISE project...
XCO file found: ddr_ila_wrpath.xco
XMDF file found: ddr_ila_wrpath_xmdf.tcl
WARNING: ddr_ila_wrpath.vhd does not exist, will not be added to ISE project.
WARNING: ddr_ila_wrpath.vho does not exist, will not be added to ISE project.
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_ila_wrpath.asy -view all -origin_type imported
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_ila_wrpath.ngc -view all -origin_type created
Checking file
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_ila_wrpath.ngc" for project device match ...
File
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_ila_wrpath.ngc" device information matches project
device.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/ddr_ila_wrpath"
Generating README file...
Generating FLIST file...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
Release 14.4 - Xilinx CORE Generator P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/coregen.log
Resolving generic values...
Finished resolving generic values.
Generating IP...
Configuring files for ddr_ila_rdpath root...
Gathering HDL files for ddr_ila_rdpath root...
Creating XST project for ddr_ila_rdpath...
Creating XST script file for ddr_ila_rdpath...
Creating XST instantiation file for ddr_ila_rdpath...
Running XST for ddr_ila_rdpath...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Not generating VHDL wrapper
Not generating Verilog wrapper
Skipping VHDL instantiation template for ddr_ila_rdpath...
Skipping Verilog instantiation template for ddr_ila_rdpath...
Finished Generation.
Generating IP instantiation template...
Generating ASY schematic symbol...
Generating metadata file...
Generating ISE project...
XCO file found: ddr_ila_rdpath.xco
XMDF file found: ddr_ila_rdpath_xmdf.tcl
WARNING: ddr_ila_rdpath.vhd does not exist, will not be added to ISE project.
WARNING: ddr_ila_rdpath.vho does not exist, will not be added to ISE project.
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_ila_rdpath.asy -view all -origin_type imported
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_ila_rdpath.ngc -view all -origin_type created
Checking file
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_ila_rdpath.ngc" for project device match ...
File
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_ila_rdpath.ngc" device information matches project
device.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/ddr_ila_rdpath"
Generating README file...
Generating FLIST file...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
Release 14.4 - Xilinx CORE Generator P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/coregen.log
Resolving generic values...
Finished resolving generic values.
Generating IP...
Configuring files for ddr_vio_sync_async_out72 root...
Gathering HDL files for ddr_vio_sync_async_out72 root...
Creating XST project for ddr_vio_sync_async_out72...
Creating XST script file for ddr_vio_sync_async_out72...
Creating XST instantiation file for ddr_vio_sync_async_out72...
Running XST for ddr_vio_sync_async_out72...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Not generating VHDL wrapper
Not generating Verilog wrapper
Skipping VHDL instantiation template for ddr_vio_sync_async_out72...
Skipping Verilog instantiation template for ddr_vio_sync_async_out72...
Finished Generation.
Generating IP instantiation template...
Generating ASY schematic symbol...
Generating metadata file...
Generating ISE project...
XCO file found: ddr_vio_sync_async_out72.xco
XMDF file found: ddr_vio_sync_async_out72_xmdf.tcl
WARNING: ddr_vio_sync_async_out72.vhd does not exist, will not be added to ISE
project.
WARNING: ddr_vio_sync_async_out72.vho does not exist, will not be added to ISE
project.
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_vio_sync_async_out72.asy -view all -origin_type
imported
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_vio_sync_async_out72.ngc -view all -origin_type
created
Checking file
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_vio_sync_async_out72.ngc" for project device match
...
File
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_vio_sync_async_out72.ngc" device information
matches project device.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/ddr_vio_sync_async_out72"
Generating README file...
Generating FLIST file...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
Release 14.4 - Xilinx CORE Generator P.49d (lin64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/coregen.log
Resolving generic values...
Finished resolving generic values.
Generating IP...
Configuring files for ddr_vio_async_in_sync_out root...
Gathering HDL files for ddr_vio_async_in_sync_out root...
Creating XST project for ddr_vio_async_in_sync_out...
Creating XST script file for ddr_vio_async_in_sync_out...
Creating XST instantiation file for ddr_vio_async_in_sync_out...
Running XST for ddr_vio_async_in_sync_out...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Not generating VHDL wrapper
Not generating Verilog wrapper
Skipping VHDL instantiation template for ddr_vio_async_in_sync_out...
Skipping Verilog instantiation template for ddr_vio_async_in_sync_out...
Finished Generation.
Generating IP instantiation template...
Generating ASY schematic symbol...
Generating metadata file...
Generating ISE project...
XCO file found: ddr_vio_async_in_sync_out.xco
XMDF file found: ddr_vio_async_in_sync_out_xmdf.tcl
WARNING: ddr_vio_async_in_sync_out.vhd does not exist, will not be added to ISE
project.
WARNING: ddr_vio_async_in_sync_out.vho does not exist, will not be added to ISE
project.
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_vio_async_in_sync_out.asy -view all -origin_type
imported
Adding
/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/ex
ample_design/par/tmp/_cg/ddr_vio_async_in_sync_out.ngc -view all -origin_type
created
Checking file
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_vio_async_in_sync_out.ngc" for project device
match ...
File
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/tmp/_cg/ddr_vio_async_in_sync_out.ngc" device information
matches project device.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/ddr_vio_async_in_sync_out"
Generating README file...
Generating FLIST file...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.

Command Line: /opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd ../synth/_ngo -nt timestamp -uc example_top.ucf -p xc7k410t-ffg900-2
example_top.ngc example_top.ngd

Reading NGO file
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/example_top.ngc" ...
Loading design module
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_ila_basic.ngc"...
Loading design module
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_ila_wrpath.ngc"...
Loading design module
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_ila_rdpath.ngc"...
Loading design module
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_vio_sync_async_out72.ngc"...
Loading design module
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_vio_async_in_sync_out.ngc"...
Loading design module
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_icon.ngc"...
Applying constraints in
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_ila_basic.ncf" to module
"CHIPSCOPE_INST.u_ddr_ila_basic"...
Checking Constraint Associations...
Applying constraints in
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_ila_wrpath.ncf" to module
"CHIPSCOPE_INST.u_ddr_ila_wrpath"...
Checking Constraint Associations...
Applying constraints in
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_ila_rdpath.ncf" to module
"CHIPSCOPE_INST.u_ddr_ila_rdpath"...
Checking Constraint Associations...
Applying constraints in
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_vio_sync_async_out72.ncf" to module
"CHIPSCOPE_INST.u_ddr_vio_sync_async_out72"...
Checking Constraint Associations...
Applying constraints in
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_vio_async_in_sync_out.ncf" to module
"CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out"...
Checking Constraint Associations...
Applying constraints in
"/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b250/coregen/ddr3_interface_fast/e
xample_design/par/ddr_icon.ncf" to module "CHIPSCOPE_INST.u_icon"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "example_top.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem - TNM : D_CLK was distributed to a DCM but new TNM
   constraints were not derived. This TNM is used in the following user groups
   or specifications:
   <TIMESPEC TS_J_TO_D = FROM "J_CLK" TO "D_CLK" TIG;>
   <TIMESPEC TS_D_TO_J = FROM "D_CLK" TO "J_CLK" TIG;>





























Done...

Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
   'CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/reset_f_edge/I_H2L.U_DOUT
   ' has unconnected output pin
WARNING:NgdBuild:452 - logical net 'N115' has no driver
WARNING:NgdBuild:452 - logical net 'N116' has no driver
WARNING:NgdBuild:452 - logical net 'N117' has no driver
WARNING:NgdBuild:452 - logical net 'N118' has no driver
WARNING:NgdBuild:452 - logical net 'N119' has no driver
WARNING:NgdBuild:452 - logical net 'N120' has no driver
WARNING:NgdBuild:452 - logical net 'N121' has no driver
WARNING:NgdBuild:452 - logical net 'N122' has no driver
WARNING:NgdBuild:452 - logical net 'N123' has no driver
WARNING:NgdBuild:452 - logical net 'N124' has no driver
WARNING:NgdBuild:452 - logical net 'N125' has no driver
WARNING:NgdBuild:452 - logical net 'N126' has no driver
WARNING:NgdBuild:452 - logical net 'N127' has no driver
WARNING:NgdBuild:452 - logical net 'N128' has no driver
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N138' has no driver
WARNING:NgdBuild:452 - logical net 'N139' has no driver
WARNING:NgdBuild:452 - logical net 'N140' has no driver
WARNING:NgdBuild:452 - logical net 'N141' has no driver
WARNING:NgdBuild:452 - logical net 'N142' has no driver
WARNING:NgdBuild:452 - logical net 'N143' has no driver
WARNING:NgdBuild:452 - logical net 'N144' has no driver
WARNING:NgdBuild:452 - logical net 'N145' has no driver
WARNING:NgdBuild:452 - logical net 'N146' has no driver
WARNING:NgdBuild:452 - logical net 'N147' has no driver
WARNING:NgdBuild:452 - logical net 'N148' has no driver
WARNING:NgdBuild:452 - logical net 'N149' has no driver
WARNING:NgdBuild:452 - logical net 'N150' has no driver
WARNING:NgdBuild:452 - logical net 'N151' has no driver
WARNING:NgdBuild:452 - logical net 'N152' has no driver
WARNING:NgdBuild:452 - logical net 'N153' has no driver
WARNING:NgdBuild:452 - logical net 'N154' has no driver

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  42

Writing NGD file "example_top.ngd" ...
Total REAL time to NGDBUILD completion: 1 min  8 sec
Total CPU time to NGDBUILD completion:  1 min  7 sec

Writing NGDBUILD log file "example_top.bld"...

NGDBUILD done.
Using target part "7k410tffg900-2".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 1 mins 9 secs 
Total CPU  time at the beginning of Placer: 1 mins 8 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:45752056) REAL time: 1 mins 23 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:45752056) REAL time: 1 mins 25 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:ca91595f) REAL time: 1 mins 25 secs 

Phase 4.2  Initial Placement for Architecture Specific Features

Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:64701dab) REAL time: 1 mins 47 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:64701dab) REAL time: 1 mins 47 secs 

Phase 6.3  Local Placement Optimization
Phase 6.3  Local Placement Optimization (Checksum:64701dab) REAL time: 1 mins 47 secs 

Phase 7.5  Local Placement Optimization
Phase 7.5  Local Placement Optimization (Checksum:64701dab) REAL time: 1 mins 48 secs 

Phase 8.8  Global Placement
........................................
........................................
..
..........................................................................................
..............................................................................................................................
..............................................................
Phase 8.8  Global Placement (Checksum:3d5393d6) REAL time: 4 mins 18 secs 

Phase 9.5  Local Placement Optimization
Phase 9.5  Local Placement Optimization (Checksum:3d5393d6) REAL time: 4 mins 19 secs 

Phase 10.18  Placement Optimization
Phase 10.18  Placement Optimization (Checksum:854dcc38) REAL time: 5 mins 9 secs 

Phase 11.5  Local Placement Optimization
Phase 11.5  Local Placement Optimization (Checksum:854dcc38) REAL time: 5 mins 9 secs 

Phase 12.34  Placement Validation
Phase 12.34  Placement Validation (Checksum:854dcc38) REAL time: 5 mins 10 secs 

Total REAL time to Placer completion: 6 mins 58 secs 
Total CPU  time to Placer completion: 6 mins 56 secs 
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:  513
Slice Logic Utilization:
  Number of Slice Registers:                18,334 out of 508,400    3%
    Number used as Flip Flops:              18,306
    Number used as Latches:                      3
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:               25
  Number of Slice LUTs:                     13,626 out of 254,200    5%
    Number used as logic:                   10,634 out of 254,200    4%
      Number using O6 output only:           8,732
      Number using O5 output only:             323
      Number using O5 and O6:                1,579
      Number used as ROM:                        0
    Number used as Memory:                   2,507 out of  90,600    2%
      Number used as Dual Port RAM:            680
        Number using O6 output only:           120
        Number using O5 output only:            11
        Number using O5 and O6:                549
      Number used as Single Port RAM:            0
      Number used as Shift Register:         1,827
        Number using O6 output only:         1,136
        Number using O5 output only:             0
        Number using O5 and O6:                691
    Number used exclusively as route-thrus:    485
      Number with same-slice register load:    400
      Number with same-slice carry load:        85
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 7,409 out of  63,550   11%
  Number of LUT Flip Flop pairs used:       21,130
    Number with an unused Flip Flop:         4,700 out of  21,130   22%
    Number with an unused LUT:               7,504 out of  21,130   35%
    Number of fully used LUT-FF pairs:       8,926 out of  21,130   42%
    Number of unique control sets:             969
    Number of slice register sites lost
      to control set restrictions:           4,800 out of 508,400    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                        75 out of     500   15%
    Number of LOCed IOBs:                       75 out of      75  100%
    IOB Flip Flops:                              9
    IOB Master Pads:                             5
    IOB Slave Pads:                              5

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                 42 out of     795    5%
    Number using RAMB36E1 only:                 42
    Number using FIFO36E1 only:                  0
  Number of RAMB18E1/FIFO18E1s:                  3 out of   1,590    1%
    Number using RAMB18E1 only:                  3
    Number using FIFO18E1 only:                  0
  Number of BUFG/BUFGCTRLs:                      3 out of      32    9%
    Number used as BUFGs:                        3
    Number used as BUFGCTRLs:                    0
  Number of IDELAYE2/IDELAYE2_FINEDELAYs:       32 out of     500    6%
    Number used as IDELAYE2s:                   32
    Number used as IDELAYE2_FINEDELAYs:          0
  Number of ILOGICE2/ILOGICE3/ISERDESE2s:       32 out of     500    6%
    Number used as ILOGICE2s:                    0
  Number used as  ILOGICE3s:                     0
    Number used as ISERDESE2s:                  32
  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0 out of     150    0%
  Number of OLOGICE2/OLOGICE3/OSERDESE2s:       69 out of     500   13%
    Number used as OLOGICE2s:                    5
    Number used as OLOGICE3s:                    0
    Number used as OSERDESE2s:                  64
  Number of PHASER_IN/PHASER_IN_PHYs:            4 out of      40   10%
    Number used as PHASER_INs:                   0
    Number used as PHASER_IN_PHYs:               4
      Number of LOCed PHASER_IN_PHYs:            4 out of       4  100%
  Number of PHASER_OUT/PHASER_OUT_PHYs:          7 out of      40   17%
    Number used as PHASER_OUTs:                  0
    Number used as PHASER_OUT_PHYs:              7
      Number of LOCed PHASER_OUT_PHYs:           7 out of       7  100%
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHCEs:                             0 out of     168    0%
  Number of BUFRs:                               0 out of      40    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DNA_PORTs:                           0 out of       1    0%
  Number of DSP48E1s:                            2 out of   1,540    1%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE2_CHANNELs:                      0 out of      16    0%
  Number of GTXE2_COMMONs:                       0 out of       4    0%
  Number of IBUFDS_GTE2s:                        0 out of       8    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         1 out of      10   10%
  Number of IN_FIFOs:                            4 out of      40   10%
    Number of LOCed IN_FIFOs:                    4 out of       4  100%
  Number of MMCME2_ADVs:                         1 out of      10   10%
    Number of LOCed MMCME2_ADVs:                 1 out of       1  100%
  Number of OUT_FIFOs:                           7 out of      40   17%
    Number of LOCed OUT_FIFOs:                   7 out of       7  100%
  Number of PCIE_2_1s:                           0 out of       1    0%
  Number of PHASER_REFs:                         2 out of      10   20%
    Number of LOCed PHASER_REFs:                 2 out of       2  100%
  Number of PHY_CONTROLs:                        2 out of      10   20%
    Number of LOCed PHY_CONTROLs:                2 out of       2  100%
  Number of PLLE2_ADVs:                          1 out of      10   10%
    Number of LOCed PLLE2_ADVs:                  1 out of       1  100%
  Number of STARTUPs:                            0 out of       1    0%
  Number of XADCs:                               1 out of       1  100%

Average Fanout of Non-Clock Nets:                3.03

Peak Memory Usage:  2335 MB
Total REAL time to MAP completion:  7 mins 13 secs 
Total CPU time to MAP completion:   7 mins 11 secs 

Mapping completed.
See MAP report file "example_top_map.mrp" for details.



Constraints file: example_top.pcf.
Loading device for application Rf_Device from file '7k410t.nph' in environment /opt/Xilinx/14.4/ISE_DS/ISE/.
   "example_top" is an NCD, version 3.2, device xc7k410t, package ffg900, speed -2

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.970 Volts. (default - Range: 0.970 to 1.030 Volts)


Device speed data version:  "PRODUCTION 1.08 2012-12-17".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                18,334 out of 508,400    3%
    Number used as Flip Flops:              18,306
    Number used as Latches:                      3
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:               25
  Number of Slice LUTs:                     13,626 out of 254,200    5%
    Number used as logic:                   10,634 out of 254,200    4%
      Number using O6 output only:           8,732
      Number using O5 output only:             323
      Number using O5 and O6:                1,579
      Number used as ROM:                        0
    Number used as Memory:                   2,507 out of  90,600    2%
      Number used as Dual Port RAM:            680
        Number using O6 output only:           120
        Number using O5 output only:            11
        Number using O5 and O6:                549
      Number used as Single Port RAM:            0
      Number used as Shift Register:         1,827
        Number using O6 output only:         1,136
        Number using O5 output only:             0
        Number using O5 and O6:                691
    Number used exclusively as route-thrus:    485
      Number with same-slice register load:    400
      Number with same-slice carry load:        85
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 7,409 out of  63,550   11%
  Number of LUT Flip Flop pairs used:       21,130
    Number with an unused Flip Flop:         4,700 out of  21,130   22%
    Number with an unused LUT:               7,504 out of  21,130   35%
    Number of fully used LUT-FF pairs:       8,926 out of  21,130   42%
    Number of slice register sites lost
      to control set restrictions:               0 out of 508,400    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                        75 out of     500   15%
    Number of LOCed IOBs:                       75 out of      75  100%
    IOB Flip Flops:                              9
    IOB Master Pads:                             5
    IOB Slave Pads:                              5

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                 42 out of     795    5%
    Number using RAMB36E1 only:                 42
    Number using FIFO36E1 only:                  0
  Number of RAMB18E1/FIFO18E1s:                  3 out of   1,590    1%
    Number using RAMB18E1 only:                  3
    Number using FIFO18E1 only:                  0
  Number of BUFG/BUFGCTRLs:                      3 out of      32    9%
    Number used as BUFGs:                        3
    Number used as BUFGCTRLs:                    0
  Number of IDELAYE2/IDELAYE2_FINEDELAYs:       32 out of     500    6%
    Number used as IDELAYE2s:                   32
    Number used as IDELAYE2_FINEDELAYs:          0
  Number of ILOGICE2/ILOGICE3/ISERDESE2s:       32 out of     500    6%
    Number used as ILOGICE2s:                    0
  Number used as  ILOGICE3s:                     0
    Number used as ISERDESE2s:                  32
  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0 out of     150    0%
  Number of OLOGICE2/OLOGICE3/OSERDESE2s:       69 out of     500   13%
    Number used as OLOGICE2s:                    5
    Number used as OLOGICE3s:                    0
    Number used as OSERDESE2s:                  64
  Number of PHASER_IN/PHASER_IN_PHYs:            4 out of      40   10%
    Number used as PHASER_INs:                   0
    Number used as PHASER_IN_PHYs:               4
      Number of LOCed PHASER_IN_PHYs:            4 out of       4  100%
  Number of PHASER_OUT/PHASER_OUT_PHYs:          7 out of      40   17%
    Number used as PHASER_OUTs:                  0
    Number used as PHASER_OUT_PHYs:              7
      Number of LOCed PHASER_OUT_PHYs:           7 out of       7  100%
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHCEs:                             0 out of     168    0%
  Number of BUFRs:                               0 out of      40    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DNA_PORTs:                           0 out of       1    0%
  Number of DSP48E1s:                            2 out of   1,540    1%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE2_CHANNELs:                      0 out of      16    0%
  Number of GTXE2_COMMONs:                       0 out of       4    0%
  Number of IBUFDS_GTE2s:                        0 out of       8    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         1 out of      10   10%
  Number of IN_FIFOs:                            4 out of      40   10%
    Number of LOCed IN_FIFOs:                    4 out of       4  100%
  Number of MMCME2_ADVs:                         1 out of      10   10%
    Number of LOCed MMCME2_ADVs:                 1 out of       1  100%
  Number of OUT_FIFOs:                           7 out of      40   17%
    Number of LOCed OUT_FIFOs:                   7 out of       7  100%
  Number of PCIE_2_1s:                           0 out of       1    0%
  Number of PHASER_REFs:                         2 out of      10   20%
    Number of LOCed PHASER_REFs:                 2 out of       2  100%
  Number of PHY_CONTROLs:                        2 out of      10   20%
    Number of LOCed PHY_CONTROLs:                2 out of       2  100%
  Number of PLLE2_ADVs:                          1 out of      10   10%
    Number of LOCed PLLE2_ADVs:                  1 out of       1  100%
  Number of STARTUPs:                            0 out of       1    0%
  Number of XADCs:                               1 out of       1  100%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx
   Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis.  REAL time: 41 secs 
Finished initial Timing Analysis.  REAL time: 42 secs 

WARNING:Par:288 - The signal V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_61_ML_NEW_IBUFDISABLE has no load.  PAR will not attempt to
   route this signal.
WARNING:Par:288 - The signal V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_59_ML_NEW_IBUFDISABLE has no load.  PAR will not attempt to
   route this signal.
WARNING:Par:288 - The signal V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_63_ML_NEW_IBUFDISABLE has no load.  PAR will not attempt to
   route this signal.
WARNING:Par:288 - The signal V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_57_ML_NEW_IBUFDISABLE has no load.  PAR will not attempt to
   route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_UPDATE_OUT[255].UPDATE_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_UPDATE_OUT[287].UPDATE_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<28> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<29> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<30> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<31> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<0> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<1> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<2> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<3> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<24> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<25> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<26> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<27> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<4> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<5> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<6> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<7> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<32> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<33> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<34> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<35> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<20> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<21> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<22> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<23> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<16> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<17> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<18> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<19> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<12> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<13> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<14> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<15> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<36> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<37> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<38> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<39> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<8> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<9> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<10> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<11> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<40> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<41> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<42> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<43> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/reset_f_edge/iDOUT<1> has no load.  PAR will not attempt to
   route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<44> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<45> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<46> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<47> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<48> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<49> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<50> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<51> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<52> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<53> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<54> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<55> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<56> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<57> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<58> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<59> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<60> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<61> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<62> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<63> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<68> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<69> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<70> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<71> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<64> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<65> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<66> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<67> has no load.  PAR will not attempt to route this
   signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMA_D1_DPO has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.status_ram.RAM32M0_RAMB_D1_DPO has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.status_ram.RAM32M0_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/out_temp has no load.  PAR
   will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_mach0/read_fifo.fifo_ram[0].RAM32M0_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMA_D1_DP
   O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMA_D1_DPO has no load.  PAR will
   not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem1_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMC_D1_DPO has no load.  PAR will
   not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem10_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem11_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem12_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMA_D1_DPO has no load.  PAR will
   not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem6_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem7_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem4_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem8_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data0/not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_RAMD_D1_O
   has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem9_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem3_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem5_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMA_D1_DPO has no load.  PAR will
   not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mram_mem2_RAMD_D1_O has no load.  PAR will not
   attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r<7> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r<7> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/rd_data_r<65> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O has no
   load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr
   _phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_data_r<7> has no load.  PAR will not attempt to route this signal.
Starting Router


Phase  1  : 103665 unrouted;      REAL time: 50 secs 

Phase  2  : 80350 unrouted;      REAL time: 54 secs 

Phase  3  : 24643 unrouted;      REAL time: 1 mins 28 secs 

Phase  4  : 24643 unrouted; (Setup:0, Hold:493268, Component Switching Limit:0)     REAL time: 1 mins 41 secs 

Updating file: example_top.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:452233, Component Switching Limit:0)     REAL time: 2 mins 4 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:452233, Component Switching Limit:0)     REAL time: 2 mins 4 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:452233, Component Switching Limit:0)     REAL time: 2 mins 4 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:452233, Component Switching Limit:0)     REAL time: 2 mins 4 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 13 secs 
Total REAL time to Router completion: 2 mins 13 secs 
Total CPU time to Router completion: 2 mins 17 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk | BUFGCTRL_X0Y1| No   | 5437 |  0.722     |  1.925      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_basic_contr |              |      |      |            |             |
|               ol<0> |BUFGCTRL_X0Y31| No   |  723 |  0.631     |  1.879      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|           t/clk_ref | BUFGCTRL_X0Y0| No   |   20 |  0.427     |  1.699      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|              m<103> |         Local|      | 1117 |  4.981     |  5.413      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<14> |         Local|      |    3 |  0.000     |  0.425      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[121].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<73> |         Local|      |   67 |  0.004     |  1.409      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<36> |         Local|      |   35 |  0.081     |  1.243      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<35> |         Local|      |   36 |  0.000     |  1.192      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<37> |         Local|      |   33 |  0.087     |  1.456      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<34> |         Local|      |   36 |  0.098     |  1.197      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[107].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.375      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<23> |         Local|      |    3 |  0.000     |  0.485      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<33> |         Local|      |    9 |  0.176     |  0.895      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<71> |         Local|      |   69 |  0.173     |  1.137      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<69> |         Local|      |   69 |  0.213     |  0.513      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<74> |         Local|      |   66 |  0.033     |  1.736      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<75> |         Local|      |   35 |  0.000     |  1.571      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<72> |         Local|      |   68 |  0.087     |  0.670      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<70> |         Local|      |   68 |  0.088     |  0.887      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<13> |         Local|      |    3 |  0.185     |  0.671      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<51> |         Local|      |    9 |  0.087     |  0.804      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<52> |         Local|      |   10 |  0.085     |  0.952      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<53> |         Local|      |   10 |  0.013     |  1.121      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<54> |         Local|      |   10 |  0.065     |  1.197      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<55> |         Local|      |   10 |  0.081     |  1.025      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<56> |         Local|      |   10 |  0.102     |  0.811      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<57> |         Local|      |    8 |  0.022     |  0.608      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[5].ASYNC_IN_CEL |              |      |      |            |             |
|         L/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<83> |         Local|      |    3 |  0.212     |  0.549      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<26> |         Local|      |    6 |  0.043     |  0.448      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<27> |         Local|      |    6 |  0.005     |  0.428      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<28> |         Local|      |    6 |  0.067     |  0.541      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<29> |         Local|      |    6 |  0.018     |  0.437      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<30> |         Local|      |    6 |  0.000     |  0.331      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<31> |         Local|      |    6 |  0.054     |  0.427      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<93> |         Local|      |    3 |  0.198     |  0.880      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<41> |         Local|      |    8 |  0.098     |  0.744      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_ddr3_clk_ibuf/sy |              |      |      |            |             |
|         s_clk_ibufg |         Local|      |    1 |  0.000     |  0.923      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_rdpath_w<75 |              |      |      |            |             |
|                  0> |         Local|      |   10 |  0.095     |  1.630      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_rdpath_w<75 |              |      |      |            |             |
|                  2> |         Local|      |   10 |  0.080     |  2.161      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_B.ddr_byte_lane_B |              |      |      |            |             |
|/oserdes_clk_delayed |              |      |      |            |             |
|                     |         Local|      |    1 |  0.000     |  0.328      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_C.ddr_byte_lane_C |              |      |      |            |             |
|/oserdes_clk_delayed |              |      |      |            |             |
|                     |         Local|      |    1 |  0.000     |  0.337      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_A.ddr_byte_lane_A |              |      |      |            |             |
|/oserdes_clk_delayed |              |      |      |            |             |
|                     |         Local|      |    1 |  0.000     |  0.343      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_rdpath_w<74 |              |      |      |            |             |
|                  8> |         Local|      |    8 |  0.000     |  1.508      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_D.ddr_byte_lane_D |              |      |      |            |             |
|/oserdes_clk_delayed |              |      |      |            |             |
|                     |         Local|      |    1 |  0.000     |  0.351      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_rdpath_w<74 |              |      |      |            |             |
|                  9> |         Local|      |    8 |  0.158     |  1.493      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_rdpath_w<75 |              |      |      |            |             |
|                  1> |         Local|      |    9 |  0.323     |  1.048      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[50].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.375      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_rdpath_w<75 |              |      |      |            |             |
|                  3> |         Local|      |    9 |  0.095     |  1.684      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<32> |         Local|      |    9 |  0.088     |  0.951      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<66> |         Local|      |    4 |  0.000     |  0.305      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_1.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_D.ddr_byte_lane_D |              |      |      |            |             |
|        /oserdes_clk |         Local|      |   11 |  0.004     |  0.343      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_wrpath_cont |              |      |      |            |             |
|             rol<13> |         Local|      |    4 |  0.000     |  0.356      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[123].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[39].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<21> |         Local|      |    3 |  0.033     |  0.448      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[38].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.375      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|                m<0> |         Local|      |    9 |  0.413     |  1.206      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_D.ddr_byte_lane_D |              |      |      |            |             |
|        /oserdes_clk |         Local|      |   18 |  0.005     |  0.343      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_D.ddr_byte_lane_D |              |      |      |            |             |
|     /oserdes_clkdiv |         Local|      |   11 |  0.352     |  0.352      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_C.ddr_byte_lane_C |              |      |      |            |             |
|        /oserdes_clk |         Local|      |   18 |  0.005     |  0.329      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_C.ddr_byte_lane_C |              |      |      |            |             |
|     /oserdes_clkdiv |         Local|      |   11 |  0.338     |  0.338      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_D.ddr_byte_lane_D |              |      |      |            |             |
|        /iserdes_clk |         Local|      |   16 |  0.005     |  0.360      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_D.ddr_byte_lane_D |              |      |      |            |             |
|     /iserdes_clkdiv |         Local|      |    9 |  0.355     |  0.355      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_1.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_C.ddr_byte_lane_C |              |      |      |            |             |
|        /oserdes_clk |         Local|      |   12 |  0.005     |  0.329      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_1.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_C.ddr_byte_lane_C |              |      |      |            |             |
|     /oserdes_clkdiv |         Local|      |   13 |  0.338     |  0.338      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_B.ddr_byte_lane_B |              |      |      |            |             |
|        /oserdes_clk |         Local|      |   18 |  0.005     |  0.331      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_B.ddr_byte_lane_B |              |      |      |            |             |
|     /oserdes_clkdiv |         Local|      |   11 |  0.332     |  0.332      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_1.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_D.ddr_byte_lane_D |              |      |      |            |             |
|     /oserdes_clkdiv |         Local|      |   11 |  0.352     |  0.352      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_A.ddr_byte_lane_A |              |      |      |            |             |
|        /oserdes_clk |         Local|      |   18 |  0.005     |  0.341      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_A.ddr_byte_lane_A |              |      |      |            |             |
|     /oserdes_clkdiv |         Local|      |   11 |  0.343     |  0.343      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_A.ddr_byte_lane_A |              |      |      |            |             |
|        /iserdes_clk |         Local|      |   16 |  0.005     |  0.360      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_A.ddr_byte_lane_A |              |      |      |            |             |
|     /iserdes_clkdiv |         Local|      |    9 |  0.361     |  0.361      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_1.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_B.ddr_byte_lane_B |              |      |      |            |             |
|     /oserdes_clkdiv |         Local|      |    3 |  0.330     |  0.330      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_C.ddr_byte_lane_C |              |      |      |            |             |
|     /iserdes_clkdiv |         Local|      |    9 |  0.342     |  0.342      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_C.ddr_byte_lane_C |              |      |      |            |             |
|        /iserdes_clk |         Local|      |   16 |  0.005     |  0.345      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_B.ddr_byte_lane_B |              |      |      |            |             |
|        /iserdes_clk |         Local|      |   16 |  0.005     |  0.346      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_0.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_B.ddr_byte_lane_B |              |      |      |            |             |
|     /iserdes_clkdiv |         Local|      |    9 |  0.347     |  0.347      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_mig_7series_v1_8 |              |      |      |            |             |
|_memc_ui_top_axi/mem |              |      |      |            |             |
|_intfc0/ddr_phy_top0 |              |      |      |            |             |
|/u_ddr_mc_phy_wrappe |              |      |      |            |             |
|r/u_ddr_mc_phy/ddr_p |              |      |      |            |             |
|hy_4lanes_1.u_ddr_ph |              |      |      |            |             |
|y_4lanes/ddr_byte_la |              |      |      |            |             |
|ne_B.ddr_byte_lane_B |              |      |      |            |             |
|        /oserdes_clk |         Local|      |    2 |  0.002     |  0.328      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|       t/freq_refclk |         Local|      |   13 |  0.273     |  1.225      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|        t/mem_refclk |         Local|      |   13 |  0.236     |  1.204      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[113].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[2].ASYNC_IN_CEL |              |      |      |            |             |
|         L/user_in_n |         Local|      |    1 |  0.000     |  0.345      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[106].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.346      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_ddr3_infrastruct |              |      |      |            |             |
|        ure/pll_clk3 |         Local|      |    1 |  0.000     |  2.155      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ico |              |      |      |            |             |
|    n/U0/iUPDATE_OUT |         Local|      |    1 |  0.000     |  0.650      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<76> |         Local|      |    3 |  0.091     |  0.486      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<22> |         Local|      |    3 |  0.142     |  0.476      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|              m<102> |         Local|      |    3 |  0.000     |  0.935      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<46> |         Local|      |    6 |  0.000     |  1.095      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<81> |         Local|      |    3 |  0.082     |  0.502      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<20> |         Local|      |    3 |  0.113     |  0.459      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<91> |         Local|      |    3 |  0.086     |  0.593      |
+---------------------+--------------+------+------+------------+-------------+
|u_ddr3_interface_fas |              |      |      |            |             |
|t/u_ddr3_infrastruct |              |      |      |            |             |
|    ure/pll_clkfbout |         Local|      |    1 |  0.000     |  0.012      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<16> |         Local|      |    3 |  0.016     |  0.347      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[63].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.375      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[4].ASYNC_IN_CEL |              |      |      |            |             |
|         L/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_basic_contr |              |      |      |            |             |
|              ol<13> |         Local|      |    4 |  0.000     |  0.631      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[6].ASYNC_IN_CEL |              |      |      |            |             |
|         L/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<25> |         Local|      |   12 |  0.190     |  0.985      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<47> |         Local|      |   38 |  0.128     |  0.842      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<48> |         Local|      |   37 |  0.043     |  1.133      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<44> |         Local|      |   12 |  0.189     |  1.179      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<84> |         Local|      |    3 |  0.082     |  0.650      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<45> |         Local|      |   12 |  0.087     |  1.082      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<92> |         Local|      |    3 |  0.021     |  0.774      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<82> |         Local|      |    3 |  0.085     |  0.578      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<90> |         Local|      |    3 |  0.241     |  0.570      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<89> |         Local|      |    3 |  0.207     |  0.688      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<80> |         Local|      |    3 |  0.041     |  0.428      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<88> |         Local|      |    3 |  0.003     |  0.328      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<79> |         Local|      |    3 |  0.000     |  0.437      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<87> |         Local|      |    3 |  0.104     |  0.431      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<78> |         Local|      |    3 |  0.082     |  0.502      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<86> |         Local|      |    3 |  0.082     |  0.405      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<77> |         Local|      |    3 |  0.194     |  0.578      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<85> |         Local|      |    3 |  0.018     |  0.345      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<24> |         Local|      |    3 |  0.000     |  0.404      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<18> |         Local|      |    3 |  0.000     |  0.339      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<17> |         Local|      |    3 |  0.134     |  0.618      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<15> |         Local|      |    3 |  0.051     |  0.396      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<19> |         Local|      |    3 |  0.199     |  0.597      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<96> |         Local|      |    4 |  0.088     |  0.836      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[117].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<67> |         Local|      |    4 |  0.026     |  0.431      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<68> |         Local|      |    3 |  0.000     |  0.337      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_ila_rdpath_cont |              |      |      |            |             |
|             rol<13> |         Local|      |    4 |  0.000     |  0.322      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[112].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.207      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<65> |         Local|      |    4 |  0.077     |  0.469      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[64].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[126].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<99> |         Local|      |    3 |  0.012     |  1.269      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<97> |         Local|      |    3 |  0.026     |  0.734      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<98> |         Local|      |    4 |  0.097     |  0.747      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<95> |         Local|      |    3 |  0.181     |  0.988      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|               m<94> |         Local|      |    4 |  0.175     |  1.009      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[49].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[43].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.403      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[116].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.403      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[127].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|              m<101> |         Local|      |    3 |  0.000     |  0.907      |
+---------------------+--------------+------+------+------------+-------------+
|ddr3_vio_async_in_tw |              |      |      |            |             |
|              m<100> |         Local|      |    4 |  0.000     |  0.800      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[111].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[58].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.483      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[119].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[115].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[124].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.395      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[120].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[118].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[125].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.403      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[114].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[3].ASYNC_IN_CEL |              |      |      |            |             |
|         L/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[40].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.375      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[1].ASYNC_IN_CEL |              |      |      |            |             |
|         L/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[109].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[61].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[42].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.345      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[62].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.375      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[108].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.345      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[105].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[122].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[110].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.345      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[59].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[60].ASYNC_IN_CE |              |      |      |            |             |
|        LL/user_in_n |         Local|      |    1 |  0.000     |  0.483      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[104].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.316      |
+---------------------+--------------+------+------+------------+-------------+
|CHIPSCOPE_INST.u_ddr |              |      |      |            |             |
|_vio_async_in_sync_o |              |      |      |            |             |
|ut/U0/I_VIO/GEN_ASYN |              |      |      |            |             |
|C_IN[103].ASYNC_IN_C |              |      |      |            |             |
|       ELL/user_in_n |         Local|      |    1 |  0.000     |  0.380      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 18

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_clk_ref_i = PERI | SETUP       |     0.131ns|     3.551ns|       0|           0
  OD TIMEGRP         "u_ddr3_interface_fast | HOLD        |     0.171ns|            |       0|           0
  _clk_ref_i" TS_sys_clk / 2.4 HIGH 50%     | MINPERIOD   |     0.165ns|     4.000ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_ddr3_infrastru | SETUP       |     0.374ns|     6.290ns|       0|           0
  cture_clk_pll_i = PERIOD TIMEGRP          | HOLD        |     0.000ns|            |       0|           0
  "u_ddr3_interface_fast_u_ddr3_infrastruct |             |            |            |        |            
  ure_clk_pll_i"         TS_u_ddr3_interfac |             |            |            |        |            
  e_fast_u_ddr3_infrastructure_pll_clk3 HIG |             |            |            |        |            
  H 50%                                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_freq_refclk = PE | MINPERIOD   |     0.594ns|     1.072ns|       0|           0
  RIOD TIMEGRP         "u_ddr3_interface_fa |             |            |            |        |            
  st_freq_refclk" TS_sys_clk / 6 PHASE 1.56 |             |            |            |        |            
  1875 ns         HIGH 50%                  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_sys_clk = PERIOD TIMEGRP "TNM_sys_clk" | MINLOWPULSE |     5.996ns|     4.000ns|       0|           0
   9.996 ns HIGH 50%                        |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_B_ddr_byte_lane_B_iserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_B_ddr_byte_lane_B |             |            |            |        |            
  _iserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_freq_refclk HIGH 50%                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_A_ddr_byte_lane_A_iserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_A_ddr_byte_lane_A |             |            |            |        |            
  _iserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_freq_refclk HIGH 50%                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_B_ddr_byte_lane_B_oserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_B_ddr_byte_lane_B |             |            |            |        |            
  _oserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_mem_refclk HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_mem_refclk = PER | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  IOD TIMEGRP         "u_ddr3_interface_fas |             |            |            |        |            
  t_mem_refclk" TS_sys_clk / 6 HIGH 50%     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_C_ddr_byte_lane_C_iserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_C_ddr_byte_lane_C |             |            |            |        |            
  _iserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_freq_refclk HIGH 50%                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_C_ddr_byte_lane_C_oserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_C_ddr_byte_lane_C |             |            |            |        |            
  _oserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_mem_refclk HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_ISERDES_CLOCK = PERIOD TIMEGRP "TNM_IS | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  ERDES_CLK" 1.666 ns HIGH 50%              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_D_ddr_byte_lane_D_oserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_D_ddr_byte_lane_D |             |            |            |        |            
  _oserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_mem_refclk HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_D_ddr_byte_lane_D_iserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_D_ddr_byte_lane_D |             |            |            |        |            
  _iserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_freq_refclk HIGH 50%                |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_D_ddr_byte_lane_D_oserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_D_ddr_byte_lane_D |             |            |            |        |            
  _oserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_mem_refclk HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_C_ddr_byte_lane_C_oserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_C_ddr_byte_lane_C |             |            |            |        |            
  _oserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_mem_refclk HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_A_ddr_byte_lane_A_oserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_0_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_A_ddr_byte_lane_A |             |            |            |        |            
  _oserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_mem_refclk HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | MINPERIOD   |     0.596ns|     1.070ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top |             |            |            |        |            
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p |             |            |            |        |            
  hy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_B_ddr_byte_lane_B_oserdes_clk         = |             |            |            |        |            
   PERIOD TIMEGRP         "u_ddr3_interface |             |            |            |        |            
  _fast_u_mig_7series_v1_8_memc_ui_top_axi_ |             |            |            |        |            
  mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_wrap |             |            |            |        |            
  per_u_ddr_mc_phy_ddr_phy_4lanes_1_u_ddr_p |             |            |            |        |            
  hy_4lanes_ddr_byte_lane_B_ddr_byte_lane_B |             |            |            |        |            
  _oserdes_clk"         TS_u_ddr3_interface |             |            |            |        |            
  _fast_mem_refclk HIGH 50%                 |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     1.827ns|     1.505ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.515ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_C_ddr_byte_lane_C_iserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_C_ddr_byte_lan |             |            |            |        |            
  e_C_iserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_freq_refclk * 2 HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     1.822ns|     1.510ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.518ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_B_ddr_byte_lane_B_iserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_B_ddr_byte_lan |             |            |            |        |            
  e_B_iserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_freq_refclk * 2 HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     1.814ns|     1.518ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.521ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_D_ddr_byte_lane_D_iserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_D_ddr_byte_lan |             |            |            |        |            
  e_D_iserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_freq_refclk * 2 HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     2.345ns|     0.987ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.064ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_A_ddr_byte_lane_A_oserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_A_ddr_byte_lan |             |            |            |        |            
  e_A_oserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_mem_refclk * 2 HIGH 50%       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     1.808ns|     1.524ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.523ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_A_ddr_byte_lane_A_iserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_A_ddr_byte_lan |             |            |            |        |            
  e_A_iserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_freq_refclk * 2 HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     2.212ns|     1.120ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.068ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_B_ddr_byte_lane_B_oserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_B_ddr_byte_lan |             |            |            |        |            
  e_B_oserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_mem_refclk * 2 HIGH 50%       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     2.340ns|     0.992ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.066ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_C_ddr_byte_lane_C_oserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_C_ddr_byte_lan |             |            |            |        |            
  e_C_oserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_mem_refclk * 2 HIGH 50%       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     2.353ns|     0.979ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.058ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     1.206ns|     2.126ns|       0|           0
  hy_4lanes_0_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_D_ddr_byte_lane_D_oserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_0_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_D_ddr_byte_lan |             |            |            |        |            
  e_D_oserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_mem_refclk * 2 HIGH 50%       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_ddr3_infrastru | MINLOWPULSE |     3.664ns|     3.000ns|       0|           0
  cture_pll_clk3 = PERIOD TIMEGRP         " |             |            |            |        |            
  u_ddr3_interface_fast_u_ddr3_infrastructu |             |            |            |        |            
  re_pll_clk3" TS_sys_clk /         1.5 HIG |             |            |            |        |            
  H 50%                                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     5.685ns|     0.979ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.058ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     4.538ns|     2.126ns|       0|           0
  hy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_D_ddr_byte_lane_D_oserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_D_ddr_byte_lan |             |            |            |        |            
  e_D_oserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_mem_refclk * 4 HIGH 50%       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     5.668ns|     0.996ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.066ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     4.538ns|     2.126ns|       0|           0
  hy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_C_ddr_byte_lane_C_oserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_C_ddr_byte_lan |             |            |            |        |            
  e_C_oserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_mem_refclk * 4 HIGH 50%       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_u_mig_7series_v1 | SETUP       |     5.667ns|     0.997ns|       0|           0
  _8_memc_ui_top_axi_mem_intfc0_ddr_phy_top | HOLD        |     0.075ns|            |       0|           0
  0_u_ddr_mc_phy_wrapper_u_ddr_mc_phy_ddr_p | MINPERIOD   |     4.538ns|     2.126ns|       0|           0
  hy_4lanes_1_u_ddr_phy_4lanes_ddr_byte_lan |             |            |            |        |            
  e_B_ddr_byte_lane_B_oserdes_clkdiv        |             |            |            |        |            
    = PERIOD TIMEGRP         "u_ddr3_interf |             |            |            |        |            
  ace_fast_u_mig_7series_v1_8_memc_ui_top_a |             |            |            |        |            
  xi_mem_intfc0_ddr_phy_top0_u_ddr_mc_phy_w |             |            |            |        |            
  rapper_u_ddr_mc_phy_ddr_phy_4lanes_1_u_dd |             |            |            |        |            
  r_phy_4lanes_ddr_byte_lane_B_ddr_byte_lan |             |            |            |        |            
  e_B_oserdes_clkdiv"         TS_u_ddr3_int |             |            |            |        |            
  erface_fast_mem_refclk * 4 HIGH 50%       |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_MULTICYCLEPATH = MAXDELAY FROM TIMEGRP | SETUP       |     4.687ns|     5.308ns|       0|           0
   "TNM_SOURCE_IDLE" TO TIMEGRP         "TN | HOLD        |     0.026ns|            |       0|           0
  M_DEST_ISERDES" TS_ISERDES_CLOCK * 6      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    13.122ns|     1.878ns|       0|           0
   TO TIMEGRP "J_CLK" 15 ns                 | HOLD        |     0.576ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    14.459ns|     0.541ns|       0|           0
   TO TIMEGRP "U_CLK" 15 ns                 | HOLD        |     0.204ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC = MAXD | MAXDELAY    |    16.584ns|     3.416ns|       0|           0
  ELAY TO TIMEGRP         "TNM_MULTICYCLEPA | HOLD        |     0.236ns|            |       0|           0
  TH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_u_ddr3_interface_fast_sync_pulse = PER | SETUP       |    25.567ns|     1.089ns|       0|           0
  IOD TIMEGRP         "u_ddr3_interface_fas | HOLD        |     0.320ns|            |       0|           0
  t_sync_pulse" TS_sys_clk / 0.375 PHASE 0. | MINHIGHPULSE|    18.096ns|     8.560ns|       0|           0
  728875         ns HIGH 6.25%              |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns H | SETUP       |    18.521ns|    11.479ns|       0|           0
  IGH 50%                                   | HOLD        |     0.104ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_J4_TO_D2_path" TIG               | SETUP       |         N/A|     3.417ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_J3_TO_D2_path" TIG               | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  PATH "TS_J2_TO_D2_path" TIG               | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  PATH "TS_D2_TO_T2_path" TIG               | SETUP       |         N/A|     1.986ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_D_TO_J_path" TIG                 | SETUP       |         N/A|     3.667ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_J_TO_D_path" TIG                 | SETUP       |         N/A|     5.541ns|     N/A|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk                     |      9.996ns|      4.000ns|      9.600ns|            0|            0|            0|       397287|
| TS_u_ddr3_interface_fast_u_ddr|      6.664ns|      3.000ns|      6.290ns|            0|            0|            0|       396693|
| 3_infrastructure_pll_clk3     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_dd|      6.664ns|      6.290ns|          N/A|            0|            0|       396693|            0|
|  r3_infrastructure_clk_pll_i  |             |             |             |             |             |             |             |
| TS_u_ddr3_interface_fast_freq_|      1.666ns|      1.072ns|      1.070ns|            0|            0|            0|          128|
| refclk                        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_A_ddr_by|             |             |             |             |             |             |             |
|  te_lane_A_iserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           32|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_A_ddr_by|             |             |             |             |             |             |             |
|  te_lane_A_iserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_B_ddr_by|             |             |             |             |             |             |             |
|  te_lane_B_iserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           32|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_B_ddr_by|             |             |             |             |             |             |             |
|  te_lane_B_iserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_C_ddr_by|             |             |             |             |             |             |             |
|  te_lane_C_iserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           32|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_C_ddr_by|             |             |             |             |             |             |             |
|  te_lane_C_iserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_D_ddr_by|             |             |             |             |             |             |             |
|  te_lane_D_iserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           32|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_D_ddr_by|             |             |             |             |             |             |             |
|  te_lane_D_iserdes_clkdiv     |             |             |             |             |             |             |             |
| TS_u_ddr3_interface_fast_mem_r|      1.666ns|      1.070ns|      1.070ns|            0|            0|            0|          240|
| efclk                         |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_A_ddr_by|             |             |             |             |             |             |             |
|  te_lane_A_oserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           36|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_A_ddr_by|             |             |             |             |             |             |             |
|  te_lane_A_oserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_B_ddr_by|             |             |             |             |             |             |             |
|  te_lane_B_oserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           36|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_B_ddr_by|             |             |             |             |             |             |             |
|  te_lane_B_oserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_C_ddr_by|             |             |             |             |             |             |             |
|  te_lane_C_oserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           36|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_C_ddr_by|             |             |             |             |             |             |             |
|  te_lane_C_oserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_D_ddr_by|             |             |             |             |             |             |             |
|  te_lane_D_oserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      3.332ns|      2.126ns|          N/A|            0|            0|           36|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_0_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_D_ddr_by|             |             |             |             |             |             |             |
|  te_lane_D_oserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_1_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_D_ddr_by|             |             |             |             |             |             |             |
|  te_lane_D_oserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      6.664ns|      2.126ns|          N/A|            0|            0|           40|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_1_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_D_ddr_by|             |             |             |             |             |             |             |
|  te_lane_D_oserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_1_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_C_ddr_by|             |             |             |             |             |             |             |
|  te_lane_C_oserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      6.664ns|      2.126ns|          N/A|            0|            0|           48|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_1_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_C_ddr_by|             |             |             |             |             |             |             |
|  te_lane_C_oserdes_clkdiv     |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      1.666ns|      1.070ns|          N/A|            0|            0|            0|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_1_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_B_ddr_by|             |             |             |             |             |             |             |
|  te_lane_B_oserdes_clk        |             |             |             |             |             |             |             |
|  TS_u_ddr3_interface_fast_u_mi|      6.664ns|      2.126ns|          N/A|            0|            0|            8|            0|
|  g_7series_v1_8_memc_ui_top_ax|             |             |             |             |             |             |             |
|  i_mem_intfc0_ddr_phy_top0_u_d|             |             |             |             |             |             |             |
|  dr_mc_phy_wrapper_u_ddr_mc_ph|             |             |             |             |             |             |             |
|  y_ddr_phy_4lanes_1_u_ddr_phy_|             |             |             |             |             |             |             |
|  4lanes_ddr_byte_lane_B_ddr_by|             |             |             |             |             |             |             |
|  te_lane_B_oserdes_clkdiv     |             |             |             |             |             |             |             |
| TS_u_ddr3_interface_fast_clk_r|      4.165ns|      4.000ns|          N/A|            0|            0|          224|            0|
| ef_i                          |             |             |             |             |             |             |             |
| TS_u_ddr3_interface_fast_sync_|     26.656ns|      8.560ns|          N/A|            0|            0|            2|            0|
| pulse                         |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_ISERDES_CLOCK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_ISERDES_CLOCK               |      1.666ns|      1.070ns|      0.885ns|            0|            0|            0|           64|
| TS_MULTICYCLEPATH             |      9.996ns|      5.308ns|          N/A|            0|            0|           64|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 415 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 2 mins 19 secs 
Total CPU time to PAR completion: 2 mins 23 secs 

Peak Memory Usage:  1899 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 417
Number of info messages: 1

Writing design to file example_top.ncd



PAR done!
Loading device for application Rf_Device from file '7k410t.nph' in environment
/opt/Xilinx/14.4/ISE_DS/ISE/.
   "example_top" is an NCD, version 3.2, device xc7k410t, package ffg900, speed
-2

Analysis completed Thu Jan 17 11:45:07 2013
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 46 secs 
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<103>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<14>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[121].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[107].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<23>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<13>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[5].ASYNC_IN_
   CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<83>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<93>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_rdpath_w<750> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_rdpath_w<752> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_rdpath_w<748> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_rdpath_w<749> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_rdpath_w<751> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[50].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_rdpath_w<753> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_wrpath_control<13>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[123].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[39].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<21>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[38].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[113].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[2].ASYNC_IN_
   CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[106].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<76>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<22>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<102>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<46>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<81>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<20>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<91>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<16>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[63].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[4].ASYNC_IN_
   CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_basic_control<13>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[6].ASYNC_IN_
   CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<84>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<45>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<92>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<82>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<90>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<89>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<80>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<88>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<79>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<87>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<78>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<86>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<77>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<85>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<24>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<18>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<17>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<15>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<19>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<96>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[117].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_ila_rdpath_control<13>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[112].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[64].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[126].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<99>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<97>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<98>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<95>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<94>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[49].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[43].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[116].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[127].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<101>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ddr3_vio_async_in_twm<100>
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[111].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[58].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[119].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[115].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[124].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[120].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[118].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[125].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[114].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[3].ASYNC_IN_
   CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[40].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[1].ASYNC_IN_
   CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[109].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[61].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[42].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[62].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[108].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[105].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[122].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[110].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[59].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[60].ASYNC_IN
   _CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[104].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_ASYNC_IN[103].ASYNC_I
   N_CELL/user_in_n is sourced by a combinatorial pin. This is not good design
   practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
   <V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_61_ML_NEW_IBUFDISABLE> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_59_ML_NEW_IBUFDISABLE> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_63_ML_NEW_IBUFDISABLE> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <V7_INS_DUMMY_IBUFDSIBUFDIS_ML_IBUFDS_IBUFDISABLE_57_ML_NEW_IBUFDISABLE> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_UPDATE_OUT[255].UPDA
   TE_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_UPDATE_OUT[287].UPDAT
   E_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<28>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<29>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<30>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<31>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<0>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<1>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<2>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<3>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<24>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<25>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<26>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<27>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<4>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<5>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<6>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<7>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<32>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<33>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<34>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<35>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<20>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<21>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<22>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<23>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<16>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<17>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<18>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<19>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<12>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<13>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<14>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<15>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<36>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<37>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<38>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<39>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<8>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<9>> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<10>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<11>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<40>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<41>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<42>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<43>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/reset_f_edge/iDOUT<1>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<44>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<45>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<46>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<47>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<48>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<49>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<50>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<51>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<52>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<53>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<54>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<55>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[113].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[112].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[114].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[115].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[111].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[116].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[120].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[119].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[118].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[117].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[122].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[105].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[104].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[103].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[108].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[102].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[109].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[110].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[101].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[121].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[100].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[123].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<56>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<57>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<58>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<59>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[106].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[107].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[124].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<60>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<61>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<62>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<63>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<68>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<69>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<70>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<71>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<64>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<65>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<66>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/UPDATE<67>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[125].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[126].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[127].SYNC_O
   UT_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT
   _CELL/out_temp> is incomplete. The signal does not drive any load pins in the
   design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_async_in_sync_out/U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/pointer_ram.rams[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/pointer_ram.rams[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/pointer_ram.rams[0].RAM32M0_RAMA_D1_DPO> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/pointer_ram.rams[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_
   mach0/read_fifo.fifo_ram[1].RAM32M0_RAMA_D1_DPO> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_
   mach0/read_fifo.fifo_ram[1].RAM32M0_RAMB_D1_DPO> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_
   mach0/read_fifo.fifo_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.status_ram.RAM32M0_RAMB_D1_DPO> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.status_ram.RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[17].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <CHIPSCOPE_INST.u_ddr_vio_sync_async_out72/U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OU
   T_CELL/out_temp> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/mc0/col_
   mach0/read_fifo.fifo_ram[0].RAM32M0_RAMD_D1_O> is incomplete. The signal does
   not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMA_D1_DPO> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem9_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem12_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem9_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem11_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem8_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem7_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem10_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[11].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem4_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem5_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[14].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[18].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem8_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem4_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem6_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem5_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem6_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem3_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem2_RAMA_D1_DPO> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem2_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[38].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem7_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem3_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem2_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem1_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem9_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem10_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem11_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[19].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[21].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem11_RAMC_D1_DPO> is incomplete. The signal does not drive any load pins
   in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem11_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem10_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem3_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem12_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem7_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem4_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[44].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[46].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[40].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem5_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem10_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem11_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem12_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem8_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem6_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[47].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[20].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[37].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[33].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[27].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem2_RAMA_D1_DPO> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem2_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem6_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem7_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem4_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem8_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_rd_data
   0/not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_RAMD_D1_O> is incomplete.
   The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem9_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem3_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem5_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem2_RAMA_D1_DPO> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/Mra
   m_mem2_RAMD_D1_O> is incomplete. The signal does not drive any load pins in
   the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_D.ddr_byte_lane_D/rd_data_r<7>> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_C.ddr_byte_lane_C/rd_data_r<7>> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[36].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[31].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[25].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[45].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[26].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_A.ddr_byte_lane_A/rd_data_r<65>> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[23].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[32].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[43].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[41].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[30].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[42].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[35].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[24].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[34].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[29].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[28].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/u_ui_top/ui_wr_data
   0/write_buffer.wr_buffer_ram[22].RAM32M0_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <u_ddr3_interface_fast/u_mig_7series_v1_8_memc_ui_top_axi/mem_intfc0/ddr_phy_
   top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_
   byte_lane_B.ddr_byte_lane_B/rd_data_r<7>> is incomplete. The signal does not
   drive any load pins in the design.
WARNING:PhysDesignRules:2487 - For MMCM_ADV block
   u_ddr3_interface_fast/u_ddr3_infrastructure/mmcm_i, the CLKOUT0_DIVIDE_F
   programming of <5.3312> is not supported. CLKOUT0_DIVIDE_F will be adjusted
   to the hardware granularity of a multiple of 0.125.
WARNING:PhysDesignRules:2245 - The PLLE2_ADV block
   <u_ddr3_interface_fast/u_ddr3_infrastructure/plle2_i> has CLKOUT pins that do
   not drive the same kind of BUFFER load. Routing from the different buffer
   types will not be phase aligned. 
